WO1998025339A1

WO1998025339A1 - Dynamic biasing circuit for amplifiers

Info

Publication number: WO1998025339A1
Application number: PCT/US1997/021590
Authority: WO
Inventors: Cynthia Blair
Original assignee: Ericsson Inc.
Priority date: 1996-12-02
Filing date: 1997-11-20
Publication date: 1998-06-11
Also published as: TW351030B; AU7627498A

Abstract

A dynamic biasing circuit monitors an input signal to a selected amplifier and compensates for variances in the amplifier's collector current by adjusting the amount of biasing DC quiescent current as the power amplitude of the input signal increases or decreases, respectively. To this end, the dynamic biasing circuit includes a detector section that detects and averages the input signal power, and a bias regulator that references a DC output signal from the detector section and accordingly adjusts a DC quiescent collector current of a biased amplifier device. The amplifier's collector current may thereby be maintained at a substantially optimum level in order to minimize negative intermodulation performance.

Description

DESCRIPTION

Dynamic Biasing Circuit For Amplifiers

Field of the Invention

The present invention pertains to the field of biasing circuits, such as those used in radio frequency ("RF") amplifiers.

Background

In the practical design of amplifiers, the transistor collector current must be controlled so that the amplifier operates within a linear range. This is usually done by biasing the transistor with a DC collector current, I_CQ, and then allowing the total transistor collector current to stray from this biasing collector current during operation. However, in some applications, it is desirable that the collector current remain at a substantially constant level so that the transistor operates in a substantially linear fashion, and the amplifier's power transfer characteristic, P₀__T/P_IN is therefore relatively constant over a given input power variance . Unfortunately, the resulting virtual class "A" bias current carries a heavy power and efficiency penalty. This is often the case when designing relatively high power RF systems that employ Class AB amplifiers. In particular, class A-B amplifiers are utilized for their high power efficiency, and also provide for a more simplistic and cost efficient design. One disadvantage of Class AB amplifier, however, is that their output exhibits a condition known as intermodulation, or "IMD", which is caused by inputting a multi-carrier signal through a non-linear device, thereby producing a power transfer characteristic that varies over time. IMD is undesirable because it generates new frequencies in the output signal that are not integrally related with the frequencies contained in the input signal .

When the input power to an AB amplifier is constant, IMD can be minimized by employing a conventional passive biasing circuit with a calculated I_CQ that holds the transistor collector current at an optimum level. To calculate the I_CQ, of the biasing circuit, the relationship) I_CoP ^=I _cQ ^+Ic_ac i-^s utilized, where I_Cop is the optimum collector current of the transistor, I_CQ is the quiescent collector current of the biasing circuit, and I_Cac is the collector current contribution from an input source. In particular, I_Cac can be derived from the specific input power and, for a given I_Cop, I_CQ is thereby determined. As long as the input power level remains constant throughout the operation of the amplifier, the collector current will remain optimum. However, if the input power level should vary, I_Cac will also vary. Because I_CQ remains constant, the collector current will thus diverge from I_C0P, resulting in a IMD performance problems. IMD performance is not usually a problem, so long as the amplifier specifications call for operation within a narrow power band, since the input power will not vary greatly from the optimized level. However, if the amplifier is required it to operate over a broad input power band, such as in many CDMA, TDMA, or MCPA applications, the input power level at any give time may vary greatly from the optimized level, resulting in poor IMD performance over portions of the input power band. This problem is readily apparent when analyzing the power variance of a multi-channel amplifier, defined as the number of operating channels squared, times the power per channel. For example, in the case of a sixteen channel amplifier at one watt per channel, the total peak power ranges from one to (16² * 1 =) two hundred fifty-six Watts. In the case of broadband power systems, the designer of the RF power amplifier is thus faced with the difficult problem of biasing the amplifier such that the transistor remains as linear as possible over the range of possible input power levels, since, as noted above, an AB amplifier can only be optimized for a specific power level using known passive biasing methods. For instance, when biasing an amplifier to operate at a low input power input, which will have a corresponding low I_Cac, the biasing circuit is designed such that I_CQ is high enough to allow the collector current to hover near I_Cop when the transistor is being operated at low power. However, when this particular amplifier is operated at a high power input level, the I_Cac is high and, because I_CQ is fixed, the biasing circuit cannot correct for the increased I_Cac. Thus, the transistor will be operating with a collector current that is far above I_Cop. As a result, the transistor will become non-linear, thus degrading the output IMD performance .

By way of further illustration of the problem, FIG. 1 graphically illustrates shows the IMD output performance of a class AB amplifier over a large dynamic input power range, employing conventional biasing methods. In particular, the IMD of an AB amplifier output is depicted versus the amplifier signal input power. Series 1 represents the results with a high current bias setting and series 2 represents the results with an "optimum" setting for 100% power output. As can be seen, although the series 1 setting provides good IMD performance at low input power levels (PEP) , the IMD performance degrades at higher power levels. On the other hand, the series 2 biasing circuit is designed such that I_CQ is low enough to allow the collector current to hover near I_Cop when the transistor is being operated at high power. However, when this particular amplifier is operated at a low power input level, the I_Cac is low. Because I_CQ is fixed, the biasing circuit cannot correct for the decreased I_Cac, and thus, the transistor will be operating with a collector current that is far below I_Cop. As a result, the transistor will become non- linear, thus degrading the output IMD performance. It is thus desirable to provide a biasing circuit for an RF power transistor that varies its quiescent collector current I_CQ in order to dynamically compensate for variances in the collector current contributed by the input signal, such that the total transistor collector current is thereby maintained at an optimum level.

Summary of the Invention

The present invention overcomes the afore-described disadvantages of prior art passive biasing circuits by employing a dynamic biasing circuit that monitors an input signal to a selected amplifier and compensates for variances in the amplifier's collector current by adjusting the biasing DC quiescent current as the amplitude of the input signal increases or decreases. To this end, and as employed in a preferred embodiment, a dynamic biasing circuit includes a detector section that detects and averages the input signal power, and a bias regulator that references an output signal from the detector section and accordingly adjusts the base bias current of a biased amplifier device. The amplifier's collector current may thereby be maintained at an optimum level .

More particularly, in a preferred embodiment, a directional coupler is connected to the input of a selected amplifier device to be biased. As an input signal passes through the directional coupler, a small sample of the signal is input into a dynamic biasing circuit, with the remainder of the input signal otherwise passing virtually undisturbed to the amplifier device. The sample portion of the input signal is passed through an average power detector, which detects the amplitude peaks of the input signal by employing a biased diode. The detector preferably further includes a bank of capacitors that remove any residual AC components from the substantially DC signal output from the biased diode. A first amplifier boosts the DC signal to a level that can be used by the bias regulator, wherein an RC circuit preferably shapes the signal to prevent the bias regulator from modulating based on information received over only a short time duration. An output of the first amplifier is input into a second amplifier, which acts as an active bias point of the amplifier device, An adjustable resistor is preferably placed between the respective first and second amplifiers to adjust the amount of control the detector section has on the bias regulator. In accordance with a more specific aspect of the invention, the output from the second amplifier is used to activate a pass transistor in order to control the input current flow into the amplifier device. More particularly, in a preferred embodiment, the pass transistor is connected between the output of the second amplifier and a base of the amplifier device being biased. The pass transistor is thereby used as a current source, which proportionally increases or decreases a current leading to the base of the amplifier device as the voltage at the output to the second amplifier either increases or decreases .

By controlling the current in the base of the amplifier device, the amplifier device is thereby dynamically biased. In particular, as the input signal to the amplifier device increases or decreases in power, thereby increasing or decreasing a collector current contributed from the input signal, respectively, the DC quiescent collector current component supplied by the biasing circuit accordingly decreases or increases, respectively, so that the amplifier device's total collector current remains at an optimum level.

In certain preferred embodiments, such as when biasing a voltage sensitive device such as a JFET or MOSFET, rather than a current sensitive device such as a BJT, the pass transistor can be excluded. In this case, the output of the second amplifier can instead be connected to a gate terminal of the JFET or MOSFET, in order to control its gate-to-source voltage.

As will be apparent to those skilled in the art, other and further objects and advantages will appear hereinafter.

Brief Description of the Drawings

The drawings illustrate both the design and utility of preferred embodiments of the present invention, in which: FIG. 1 is a graph illustrating IMD performance of a class AB amplifier over a large dynamic range when using conventional biasing methods;

FIG. 2 is a schematic diagram of a preferred dynamic biasing circuit in accordance with the invention; and FIG. 3 is a graph illustrating IMD Performance of a class AB amplifier over a large dynamic range when employing the dynamic biasing circuit of FIG. 2.

Detailed Description of the Preferred Embodiments

Referring to FIG. 2, a preferred dynamic biasing circuit 22 includes a microstrip directional coupler 26 that receives an AC input signal 24 through an input port 32. A base terminal 25 of an RF amplifier device 20 is connected to a first output port 28 of the coupler 26. A second output port 30 of the coupler 26 is connected to an input node 27 of the dynamic biasing circuit 22. An input port 32 of the coupler 26 receives the AC input signal 24. The coupler 26 has a selected coupling value, CV1, so that only a very small percentage (or sample) of the AC input signal 24 entering port 32 of coupler 26 passes through port 30 to node 27, with the vast majority portion of the AC input signal 24 passing virtually undisturbed through port 28 to the amplifier device 20. A resistor 38 of the coupler's characteristic impedance is provided between a second input port 34 of coupler 26 and ground to provide for impedance matching. By way of nonlimiting example, in a currently preferred embodiment, a resistance value of fifty ohms is used for resistor 38.

The amplitude of the signal at node 43 (also connected to node 27) is controlled as follows: A first resistor 40 having a selected resistance value Rl is inserted between node 27 and ground; a second resistor 42 having a selected resistance value R2 is inserted between node 27 and a bridge node 43; and a third resistor 44 also having a resistance value Rl is inserted between node 43 and ground. By this configuration, the voltage level at node 43 is reduced by a factor of R1/R1+R2. To filter out DC signals, a capacitor 46 is inserted between bridge node 43 and a further node 47. The capacitance value Cl of capacitor 46 is preferably selected so that capacitor 46 is a virtual open circuit to any DC signals, and a virtual short circuit to signals with frequencies equal to that of input signal 24.

A diode 48 having its cathode connected to node 47 conducts and rejects the positive and negative portions of the sample portion of input signal 24, as follows:

An adjustable resistor 50 having an adjusted resistance value R3 is inserted between node 47 and a voltage supply 49. By way of example, in a currently preferred embodiment, voltage supply 49 is selected to be eight volts. A resistor 52 having a selected resistance value R4 is inserted between the anode of diode 48 and ground. Resistance values R3 and R4 are preferably selected so that diode 48 is at a conduction point when no signal is present at node 47. In order to decouple the voltage supply 49 from the signal at node 47, a capacitor 54 having a selected capacitance value C2 is inserted between the voltage supply 49 and ground. C2 is preferably selected so that capacitor 54 is a virtual open circuit to voltage supply 49, and a virtual short circuit to a signal having a frequency equal to that of input signal 24. In order to decouple the voltage supply 49 from the input signal 24 and any detected modulation at op amp 62 or op amp 86 (described below) , a capacitor 82 having a selected capacitance value C6 is inserted between the voltage supply 49 and ground. C6 is preferably selected so that capacitor 82 is a virtual open circuit to voltage supply 49, and a virtual short circuit to a signal having a frequency equal to that of the input signal 24.

The AC input signal 24 at the anode of diode 48 is peak averaged by the use of capacitors 56, 58, and 60 with selected capacitance values C3 , C4 , and C5 , respectively, that are inserted between the anode of diode 48 and ground. Capacitance values C3 , C4 , C5 are preferably selected to obtain differing slopes of the peak averages caused by modulation and/or signal differences in input signal 24. The signal level at the anode of diode 48 is amplified through an operational amplifier ("op amp") 62. To "power up" the op amp 62, a positive power terminal 64 is connected to the voltage supply 49, and a negative power terminal 66 of op amp 62 is connected to ground, respectively. In order to set the gain through op amp 62, a resistor 72 having a selected resistance value R5 is inserted between a negative input terminal 70 of op amp 62 and ground; an adjustable resistor 76 having an adjusted resistance value R6 is inserted between terminal 70 and an output node 74; and a resistor 78 having a selected resistance value R7 is inserted between an output 77 of the op amp 62 and output node 74. In this manner, the op amp 62 amplifies the voltage at the anode of diode 48 by a factor of 1+(R6+R7/R5) . A resistor 80 having selected resistance value R8 is inserted between the anode of diode

48 and a positive input terminal 68 of the op amp 62, wherein resistor 80 provides isolation and gain limiting. To this end, the resistance value R8 of resistor 80 is preferably selected so that the proper saturation curve of the detector circuitry is obtained for the type of amplifier used, e.g., FET or BiPolar. The signal from op amp output 77 is preferably shaped, so that short time amplitude variations of the AC input signal 24 are not taken into account when biasing amplifier device 20. In the illustrated preferred embodiment, this is accomplished by a capacitor 84 having a selected capacitance C7 working in concert with the resistor 78 (R7) inserted between output node 74 and ground, so that the signal across capacitor 84 has a RC time constant. A second op amp 86 is employed as a feedback-type bias regulator for controlling a pass transistor 102, as follows :

A resistor 108 having a selected resistance value Rll is inserted between nodes 100 and 105, and an adjustable resistor 110 having an adjusted resistance value R12 is inserted between a bridging node 92 and node 100, respectively. Resistors 108 and 110 thereby provide a voltage derived from the power supply 49 to bridging node 92, which in turn supplies power to a temperature compen- sation diode 114. Diode 114 is thermally coupled to the amplifier device 20, thereby decreasing or increasing the voltage at a negative (i.e., non-inverting) input terminal 90 of op amp 86, as the temperature of the amplifier device 20 increases or decreases, respectively. A capa- citor 130 having a capacitance value CIO is inserted between the cathode terminal of diode 114 and ground to decouple any RF or modulating voltages inadvertently detected by diode 114.

Bridging node 92 also supplies a voltage divider formed by resistors 106 and 112, which have resistance values R10 and R13 , respectively, and which provide a reference voltage to a positive input terminal 94 of OP amp 86. A feedback resistor 98 having a resistance value R9 is inserted between the negative terminal 90 and an emitter terminal 104 of the pass transistor 102.

Resistance values R9 , R10, R13 are preferably selected so that the gain of the bias regulator (i.e. of op amp 86) will hover around unity from node 92 to the emitter terminal 104. An adjustable resistor 96 having an adjusted resistance value R8 is inserted between node 74 and the negative input terminal 90 of op amp 86 to provide an adjustable control of signal 77 output from op amp 62. In order to decouple the voltage supply 49 from the signal at node 105, a pair of capacitors 126 and 128 having capacitance values C8 and C9, respectively, are inserted between voltage supply 49 and node 100, and are connected to ground, respectively. In order to decouple the voltage supply 49 from the signal across diode 114, capacitance values C8 and C9 are preferably selected so that the respective capacitors are virtual open circuits to voltage supply 49, and virtual short circuits to a signal having a frequency equalling that of input signal 24 and any modulating frequencies.

An output signal 116 of op amp 86 is supplied to a base terminal 118 of the pass transistor 102. A resistor 122 having a selected resistance value R14 is inserted between voltage supply 49 and a collector terminal 124 of pass transistor 102 to provide current limiting. The emitter 104 of pass transistor 102 is connected to a base terminal 125 of amplifier device 20. In this manner, the current 1₁ , from the emitter 104 of pass transistor 102 is combined with a varying current I₂ from the input signal 24 to maintain an optimum operating point of the amplifier device 20.

In order to decouple the voltage supply 49 from the signal across the amplifier device 20, capacitors 132 and 134 having capacitance values Cll and C12, respectively, are inserted between the emitter terminal 104 and ground and an inductor 107 is inserted between node 104 and the amplifier device 20. Capacitance values Cll and C12 are preferably selected so that capacitors 132 and 134 act as virtual open circuits to bias supply 49, and virtual short circuits to a signal having a frequency equal to that of input signal 24 and any modulating signals. As will be apparent to those skilled in the art, when biasing a voltage sensitive amplifier device such as a JFET or MOSFET, rather than a current sensitive amplifier device such as a BJT, the pass transistor 102 can be excluded. In this case, the output signal 116 of op amp 86 can be directly connected to the source (collector) terminal of the respective JFET or MOSFET, in order to control its drain to source voltage drop.

The IMD performance of an AB amplifier device employing the dynamic biasing circuit 22 is shown in FIG.

3. For purposes of illustration, the conventional high and low current biasing represented by series 1 and 2, respectively, of FIG. 1 are also included in FIG. 3.

Series 3 represents the IMD performance of an AB amplifier that employs the preferred dynamic biasing circuit 22. As can be seen, the IMD performance of the dynamically biased

AB amplifier is much improved over the IMD performance of the conventionally biased amplifiers at every power level.

Thus, a preferred embodiment of a dynamic biasing circuit in accordance with the present invention has been shown and described. As will be apparent to one of ordinary skill in the art that numerous alterations to the afore-described preferred embodiment may be made without departing from the spirit or scope of the invention. By way of example only, instead of employing a directional coupler to divert a sample portion of the input signal into the biasing circuit, a current sensor coupled with a signal generator could be used to regenerate a signal of proportional power as the input signal, without disturbing any portion of the actual input signal.

Thus, the invention is not to be limited except in accordance with the appended claims.

Claims

1. A dynamic biasing circuit for biasing a collector current of an amplifier device receiving a variable power input signal, comprising: means for obtaining a sample signal representative of the input signal; a signal level detection circuit configured to detect successive amplitude peaks of the sample signal and output a corresponding DC signal; and a bias regulator connected to a control terminal of the amplifier.

2. The biasing circuit of claim 1, wherein the means for obtaining a sample signal proportional to the input signal comprise a directional coupler connected to an input of the amplifier and configured to divert a small portion of the input signal into the signal level detection circuit.

3. The biasing circuit of claim 1, wherein the signal level detection circuit comprises a biased diode.

4. The biasing circuit of claim 3, further comprising one or more capacitors configured to remove residual AC components of the sample signal passed through the biased diode.

5. The biasing circuit of claim 1, further comprising a first operational amplifier configured to receive and amplify the DC signal from the signal level detection circuit .

6. The biasing circuit of claim 5, further comprising a shaping circuit configured to shape an output of the first amplifier.

7. The biasing circuit of claim 6, wherein the shaping circuit comprises an RC circuit .

8. The biasing circuit of claim 5, further comprising an adjustable resistor configured to selectively adjust an output of the first amplifier.

9. The biasing circuit of claim 5, further comprising a second operational amplifier configured to receive an output of the first operational amplifier.

10. The biasing circuit of claim 9, wherein an output of the second operational amplifier is connected to an input terminal of, and thereby controls, the bias regulator.

11. A dynamic biasing circuit for biasing a collector current of an amplifier receiving a variable power input signal, comprising: means for obtaining a sample signal representative of the input signal; means for generating a DC signal corresponding to the sample signal; and means responsive to the DC signal level for adjusting the amplifier collector current.

12. The biasing circuit of claim 11, wherein the means for generating a DC signal comprise a signal level detection circuit that employs a biased diode to detect successive amplitude peaks of the sample signal and includes one or more capacitors configured to remove residual AC components of the sample signal passed through the biased diode.

13. The biasing circuit of claim 12, wherein the means for generating a DC signal further comprise a first operational amplifier configured to receive an input signal from a cathode terminal of the biased diode.

14. The biasing circuit of claim 13, wherein the means for adjusting the amplifier collector current comprise a second operational amplifier configured to receive an output of the first operational amplifier.

15. The biasing circuit of claim 14, wherein the second operational amplifier acts as an active bias point of the amplifier being biased.

16. The biasing circuit of claim 14, wherein an output of the second operational amplifier is connected to a gate terminal of the amplifier being biased.

17. The biasing circuit of claim 14, wherein the means for adjusting the amplifier collector current further comprise a pass transistor configured to receive, and be controlled by, an output of the second operational amplifier.

18. The biasing circuit of claim 17, wherein the pass transistor has an emitter terminal connected to a base terminal of the amplifier being biased.

19. The biasing circuit of claim 11, wherein the means for adjusting the amplifier collector current comprise a pass transistor having an emitter terminal connected to a base terminal of the amplifier.

20. A dynamic biasing circuit for biasing a collector current of an amplifier device receiving a variable power input signal, comprising: means for obtaining a portion of the input signal ; a biased diode configured to detect and conduct successive amplitude peaks of the sample signal to thereby output a corresponding DC signal; and a pass transistor configured to receive a input signal proportional to the DC signal and having an emitter terminal connected to a base terminal of the amplifier.