WO1998019172A1 - Circuit for the hysteresis-related detection of the threshold value of the peak value of a periodic input signal - Google Patents

Circuit for the hysteresis-related detection of the threshold value of the peak value of a periodic input signal Download PDF

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Publication number
WO1998019172A1
WO1998019172A1 PCT/AT1997/000231 AT9700231W WO9819172A1 WO 1998019172 A1 WO1998019172 A1 WO 1998019172A1 AT 9700231 W AT9700231 W AT 9700231W WO 9819172 A1 WO9819172 A1 WO 9819172A1
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Prior art keywords
input signal
threshold value
output
input
threshold
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PCT/AT1997/000231
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German (de)
French (fr)
Inventor
Bernhard Rzepa
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Mikroprozessor Handels-Ges.Mbh & Co. Kg
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Publication of WO1998019172A1 publication Critical patent/WO1998019172A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/1659—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 to indicate that the value is within or outside a predetermined range of values (window)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses

Definitions

  • the present invention relates to a circuit arrangement for hysteresis-dependent threshold value detection of the peak value of a periodic input signal.
  • the input signal is rectified and sieved in order to receive an approximation signal for the temporal change in the peak value, which is fed to a Schmitt trigger, which generates the desired hysteresis behavior.
  • the time constant of the sieve element must be chosen to be sufficiently large, which increases the reaction time of the detection accordingly, so that a rapid drop in the peak value below the threshold value can only be detected with a delay, especially when the input voltage initially exceeds the threshold value.
  • the aim of the invention is to create a circuit arrangement of the type mentioned in the introduction with which the exceeding or falling below certain threshold values of the peak value can be quickly and reliably, i.e. while maintaining the hysteresis behavior of the known circuit arrangements.
  • This goal is achieved with a circuit arrangement which is characterized according to the invention in that the input signal is fed to a threshold value switch with a controllable threshold value, which is followed by a retriggerable timer with a time constant in the order of magnitude of the basic period of the input signal, the output of which is the output of the circuit arrangement forms and is fed to the control input of the threshold switch and reduces its threshold value in the triggered state.
  • the response time to a drop in the peak value is a maximum of the hold time of the timing element, which is of the order of the basic period of the input signal and thus clearly below the time constant of conventional filter elements.
  • a particularly advantageous embodiment of the invention which is intended for zero-line-symmetrical input signals, is characterized in that the threshold value switch is preceded by a full-wave rectifier and the time constant of the timing element is less than half the basic period of the input signal, which further reduces the response time.
  • the threshold switch preferably has a comparator, at one input of which the input signal and at the other input of which the output of a controllable reference voltage source is guided, which is controlled by the output of the timing element, which enables a particularly simple embodiment.
  • FIG. 1 shows the relationship between input and output signal in a conventional Schmitt trigger according to the prior art, which is controlled via a rectifier and a filter element
  • FIG. 2 shows a block diagram of the circuit arrangement according to the invention
  • FIG. 3 shows the relationship between input and output signal in the circuit arrangement of FIG. 2.
  • the uppermost curve in FIG. 1 shows a keyed input signal UN > whose keying represents the information content to be detected.
  • the middle curve shows the timing of an approximation signal Us for the peak value of the input signal Uj ⁇ which has been generated by conventional rectification and screening and is led to the input of a Schmitt trigger with the switch-on threshold Ug and the switch-off threshold U ⁇ .
  • the output signal UQTJT i st i n the lowermost curve shown. It can be seen that a drop in the peak value of UJN below the switch-off threshold value U ⁇ is only recognized after a delay time ⁇ T, which is determined by the time constant of the filter element used.
  • the circuit arrangement according to the invention for hysteresis-dependent threshold value detection of the peak value of a periodic input signal in succession has a full-wave rectifier 1, a threshold switch 2 and a timing element 3.
  • the threshold value U sw of the threshold switch 2 is controlled via a control input 4 by the output of the timing element 3, which at the same time forms the output U ou t of the circuit arrangement.
  • the threshold switch 2 essentially contains a comparator 5, at whose one input the rectified input signal U j 'and at the other input of which a controllable reference voltage source 6 is connected, which can be set via the control input 4.
  • the timing element 3 is of the retriggerable type and has a time constant .DELTA.t which is in the order of the basic period P of the input signal Uj ⁇ , preferably in the range of half the basic period.
  • the timing element 3 is preferably formed by a monoflop, but can also be an R / C element with a shortened charging time constant. The operation of the circuit is explained with reference to FIG. 3, which shows the timing of the voltage UJ_N a circuit input, the voltage UJN 'at the input of the threshold switch and the voltage UOTJT a circuit output one above the other. If the rectified input signal UJ .
  • N ' reaches the threshold value Usw of the threshold switch 2, this triggers the timing element 3 and the output signal U Q UT changes to the "high” state.
  • the "high" signal at the circuit output instructs the reference voltage source 6 to reduce the threshold value Usw for the threshold value switch 2 to a lower threshold value Usw ' z u.
  • the rising edges of the subsequent half-waves of the rectified input signal Uj ⁇ 'each time trigger the timer 3 again, as long as they exceed the reduced threshold value Usw'. If the peak value of the rectified input signal Uj N 'falls below the reduced threshold value U S ', the retriggering of the timing element 3 is omitted and the output signal UQ T falls after a delay time which corresponds to the time constant ⁇ t of the monoflop 3, return to "low".
  • a preferred application of the circuit arrangement is the use in a digital coupling element which is controlled with an alternating signal or works internally with one (e.g. for feeding an inductive transformer for galvanic input / output separation), the keying of the alternating signal being the digital information to be detected with hysteresis represents.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

This invention concerns a circuit for the hysteresis-related detection of the threshold value of a periodic input signal. The input signal (UIN, UIN') is fed to a threshold value switch (2) with a controllable threshold value (USW) to which a retriggerable timer element (3) with a time constant (Δt) in the order of magnitude of the primitive period (P) of the input signal (UIN, UIN') is connected at the output side. The output of the retriggerable timer element (3) forms the output (UOUT) of the circuit and is fed to the control input (4) of the switch (2) and reduces (USW') its threshold value (USW) when it is in the triggered state.

Description

Schaltungsanordnung zur hysteresebehafteten Schwellwertdetek- tion des Spitzenwertes eines periodischen EingangssignalesCircuit arrangement for hysteresis-based threshold value detection of the peak value of a periodic input signal
Die vorliegende Erfindung betrifft eine Schaltungsanord- nung zur hysteresebehafteten Schwellwertdetektion des Spitzenwertes eines periodischen Eingangssignales.The present invention relates to a circuit arrangement for hysteresis-dependent threshold value detection of the peak value of a periodic input signal.
Bei bekannten Schaltungsanordnungen der genannten Art wird das Eingangssignal gleichgerichtet und gesiebt, um ein Näherungssignal für die zeitliche Änderung des Spitzenwertes zu er- halten, das einem Schmitt-Trigger zugeführt wird, welcher das gewünschte Hystereseverhalten erzeugt. Für eine ausreichende Siebung des gleichgerichteten Eingangssignales muß die Zeitkonstante des Siebgliedes entsprechend groß gewählt werden, was die Reaktionszeit der Detektion entsprechend erhöht, so daß speziell bei einer den Schwellwert zunächst wesentlich übersteigenden Eingangsspannung ein rascher Abfall des Spitzenwertes unter den Schwellwert nur verzögert erkannt werden kann.In known circuit arrangements of the type mentioned, the input signal is rectified and sieved in order to receive an approximation signal for the temporal change in the peak value, which is fed to a Schmitt trigger, which generates the desired hysteresis behavior. For a sufficient sieving of the rectified input signal, the time constant of the sieve element must be chosen to be sufficiently large, which increases the reaction time of the detection accordingly, so that a rapid drop in the peak value below the threshold value can only be detected with a delay, especially when the input voltage initially exceeds the threshold value.
Die Erfindung setzt sich zum Ziel, eine Schaltungsanordnung der einleitend genannten Art zu schaffen, mit welcher das Über- oder Unterschreiten bestimmter Schwellwerte des Spitzenwertes rasch und zuverlässig, d.h. unter Beibehaltung des Hystereseverhaltens der bekannten Schaltungsanordnungen, erkannt werden kann. Dieses Ziel wird mit einer Schaltungsanordnung erreicht, die sich gemäß der Erfindung dadurch auszeichnet, daß das Eingangssignal einem Schwellwertschalter mit steuerbarem Schwellwert zugeführt ist, welchem ein retriggerbares Zeitglied mit einer Zeitkonstante in der Größenordnung der Grundperiodendauer des Eingangssignales nachgeschaltet ist, dessen Ausgang den Ausgang der Schaltungsanordnung bildet sowie dem Steuerein- gang des Schwellwertschalters zugeführt ist und im getriggerten Zustand dessen Schwellwert reduziert.The aim of the invention is to create a circuit arrangement of the type mentioned in the introduction with which the exceeding or falling below certain threshold values of the peak value can be quickly and reliably, i.e. while maintaining the hysteresis behavior of the known circuit arrangements. This goal is achieved with a circuit arrangement which is characterized according to the invention in that the input signal is fed to a threshold value switch with a controllable threshold value, which is followed by a retriggerable timer with a time constant in the order of magnitude of the basic period of the input signal, the output of which is the output of the circuit arrangement forms and is fed to the control input of the threshold switch and reduces its threshold value in the triggered state.
Auf diese Weise beträgt die Reaktionszeit auf einen Abfall des Spitzenwertes maximal die Haltezeit des Zeitgliedes, welche in der Größenordnung der Grundperiodendauer des Eingangssi- gnales und damit deutlich unter der Zeitkonstante herkömmlicher Siebglieder liegt. Durch das Verändern der Schaltschwelle des Schwellwertschalters im gesetzten Zustand des Zeitgliedes, d.h. dem Detektionszustand, wird dem Schwellwertschalter ein Hystereseverhalten auferlegt.In this way, the response time to a drop in the peak value is a maximum of the hold time of the timing element, which is of the order of the basic period of the input signal and thus clearly below the time constant of conventional filter elements. By changing the switching threshold of the threshold switch when the timer is set, ie the detection state, hysteresis behavior is imposed on the threshold switch.
Eine besonders vorteilhafte Ausführungsform der Erfindung, welche für nulliniensymmetrische Eingangssignale bestimmt ist, zeichnet sich dadurch aus, daß dem Schwellwertschalter ein Vollwellengleichrichter vorgeschaltet ist und die Zeitkonstante des Zeitgliedes kleiner als die halbe Grundperiodendauer des Eingangssignales ist, was die Reaktionszeit noch weiter verringert. Bevorzugt weist der Schwellwertschalter einen Komparator auf, an dessen einen Eingang das Eingangssignal und an dessen anderen Eingang der Ausgang einer steuerbaren Referenzspannungsquelle geführt ist, welche vom Ausgang des Zeitgliedes angesteuert ist, was eine besonders einfache Ausführung er- möglicht.A particularly advantageous embodiment of the invention, which is intended for zero-line-symmetrical input signals, is characterized in that the threshold value switch is preceded by a full-wave rectifier and the time constant of the timing element is less than half the basic period of the input signal, which further reduces the response time. The threshold switch preferably has a comparator, at one input of which the input signal and at the other input of which the output of a controllable reference voltage source is guided, which is controlled by the output of the timing element, which enables a particularly simple embodiment.
Die Erfindung wird nachstehend an Hand eines in den Zeichnungen dargestellten Ausführungsbeispieles näher erläutert. In den Zeichnungen zeigtThe invention is explained below with reference to an embodiment shown in the drawings. In the drawings shows
Fig. 1 die Beziehung zwischen Eingangs- und Ausgangssignal bei einem herkömmlichen, über einen Gleichrichter und ein Siebglied angesteuerten Schmitt-Trigger nach dem Stand der Technik, Fig. 2 ein Blockschaltbild der erfindungsgemäßen Schaltungsanordnung und1 shows the relationship between input and output signal in a conventional Schmitt trigger according to the prior art, which is controlled via a rectifier and a filter element, FIG. 2 shows a block diagram of the circuit arrangement according to the invention and
Fig. 3 die Beziehung zwischen Eingangs- und Ausgangssignal bei der Schaltungsanordnung von Fig. 2.3 shows the relationship between input and output signal in the circuit arrangement of FIG. 2.
Die oberste Kurve von Fig. 1 zeigt ein getastetes Eingangssignal U N> dessen Tastung den zu detektierenden Informationsgehalt darstellt. Die mittlere Kurve zeigt den Zeitablauf eines Näherungssignales Us für den Spitzenwert des Eingangssi- gnales Uj^ welches durch herkömmliche Gleichrichtung und Siebung erzeugt worden ist und an den Eingang eines Schmitt-Triggers mit der Einschaltschwelle Ug und der Ausschaltschwelle U^ geführt wird. Das Ausgangssignal UQTJT i-st i-n der untersten Kurve gezeigt. Es ist ersichtlich, daß ein Abfallen des Spit- zenwertes von UJN unter den Ausschaltschwellwert U^ erst nach einer Verzögerungszeit ΔT erkannt wird, welche von der Zeitkonstante des verwendeten Siebgliedes bestimmt ist. Gemäß Fig. 2 weist die erfindungsgemäße Schaltungsanordnung zur hysteresebehafteten Schwellwertdetektion des Spitzenwertes eines periodischen Eingangssignales in Aufeinanderfolge einen Vollwellengleichrichter 1, einen Schwellwertschalter 2 und ein Zeitglied 3 auf. Der Schwellwert Usw des Schwellwertschalters 2 wird über einen Steuereingang 4 vom Ausgang des Zeitgliedes 3 gesteuert, welcher gleichzeitig den Ausgang Uout der Schaltungsanordnung bildet.The uppermost curve in FIG. 1 shows a keyed input signal UN > whose keying represents the information content to be detected. The middle curve shows the timing of an approximation signal Us for the peak value of the input signal Uj ^ which has been generated by conventional rectification and screening and is led to the input of a Schmitt trigger with the switch-on threshold Ug and the switch-off threshold U ^. The output signal UQTJT i st i n the lowermost curve shown. It can be seen that a drop in the peak value of UJN below the switch-off threshold value U ^ is only recognized after a delay time ΔT, which is determined by the time constant of the filter element used. 2, the circuit arrangement according to the invention for hysteresis-dependent threshold value detection of the peak value of a periodic input signal in succession has a full-wave rectifier 1, a threshold switch 2 and a timing element 3. The threshold value U sw of the threshold switch 2 is controlled via a control input 4 by the output of the timing element 3, which at the same time forms the output U ou t of the circuit arrangement.
Der Schwellwertschalter 2 enthält im wesentlichen einen Komparator 5, an dessen einen Eingang das gleichgerichtete Eingangssignal U j' und an dessen anderen Eingang eine steuerbare Referenzspannungsquelle 6 angeschaltet ist, welche über den Steuereingang 4 einstellbar ist.The threshold switch 2 essentially contains a comparator 5, at whose one input the rectified input signal U j 'and at the other input of which a controllable reference voltage source 6 is connected, which can be set via the control input 4.
Das Zeitglied 3 ist von retriggerbare Typ und besitzt eine Zeitkonstante Δt, welche in der Größenordnung der Grundperiodendauer P des Eingangssignales Uj^ liegt, bevorzugt im Bereich der halben Grundperiodendauer. Das Zeitglied 3 wird bevorzugt durch ein Monoflop gebildet, kann aber auch ein R/C-Glied mit verkürzter Aufladezeitkonstante sein. Die Funktionsweise der Schaltung wird unter Bezugnahme auf Fig. 3 erläutert, welche den Zeitablauf der Spannung UJ_N a Schaltungseingang, der Spannung UJN' am Eingang des Schwellwertschalters und der Spannung UOTJT a Schaltungsausgang übereinander darstellt. Wenn das gleichgerichtete Eingangssignal UJ.N' den Schwellwert Usw des Schwellwertschalters 2 erreicht, triggert dieser das Zeitglied 3, und das Ausgangssignal UQUT geht in den Zustand "high" über. Das "high"-Signal am Schaltungsausgang weist die Referenzspannungsquelle 6 an, den Schwellwert Usw für den Schwellwertschalter 2 auf einen niedri- geren Schwellwert Usw' zu reduzieren.The timing element 3 is of the retriggerable type and has a time constant .DELTA.t which is in the order of the basic period P of the input signal Uj ^, preferably in the range of half the basic period. The timing element 3 is preferably formed by a monoflop, but can also be an R / C element with a shortened charging time constant. The operation of the circuit is explained with reference to FIG. 3, which shows the timing of the voltage UJ_N a circuit input, the voltage UJN 'at the input of the threshold switch and the voltage UOTJT a circuit output one above the other. If the rectified input signal UJ . N 'reaches the threshold value Usw of the threshold switch 2, this triggers the timing element 3 and the output signal U Q UT changes to the "high" state. The "high" signal at the circuit output instructs the reference voltage source 6 to reduce the threshold value Usw for the threshold value switch 2 to a lower threshold value Usw ' z u.
Die ansteigenden Flanken der anschließenden Halbwellen des gleichgerichteten Eingangssignales Uj^' triggern jedesmal das Zeitglied 3 von neuem, solange sie den reduzierten Schwellwert Usw' überschreiten. Wenn der Spitzenwert des gleichgerichteten Eingangssignales UjN' unter den reduzierten Schwellwert US ' fällt, unterbleibt das Nachtriggern des Zeitgliedes 3, und das Ausgangssignal UQ T fällt nach einer Verzögerungszeit, welche der Zeitkonstante Δt des Monoflops 3 entspricht, auf "low" zurück.The rising edges of the subsequent half-waves of the rectified input signal Uj ^ 'each time trigger the timer 3 again, as long as they exceed the reduced threshold value Usw'. If the peak value of the rectified input signal Uj N 'falls below the reduced threshold value U S ', the retriggering of the timing element 3 is omitted and the output signal UQ T falls after a delay time which corresponds to the time constant Δt of the monoflop 3, return to "low".
Eine bevorzugte Anwendung der Schaltungsanordnung ist der Einsatz in einem digitalen Koppelelement, welches mit einem Wechselsignal angesteuert wird oder intern mit einem solchen arbeitet (z.B. zur Speisung eines induktiven Übertragers zur galvanischen Eingangs/Ausgangstrennung) , wobei die Tastung des Wechselsignales die mit Hysterese zu detektierende Digitalinformation darstellt. A preferred application of the circuit arrangement is the use in a digital coupling element which is controlled with an alternating signal or works internally with one (e.g. for feeding an inductive transformer for galvanic input / output separation), the keying of the alternating signal being the digital information to be detected with hysteresis represents.

Claims

Patentansprüche : Claims:
1. Schaltungsanordnung zur hysteresebehafteten Schwell- wertdetektion des Spitzenwertes eines periodischen Eingangssi- gnales, dadurch gekennzeichnet, daß das Eingangssignal
Figure imgf000007_0001
UIN') einem Schwellwertschalter (2) mit steuerbarem Schwellwert (Usw) zugeführt ist, welchem ein retriggerbares Zeitglied (3) mit einer Zeitkonstante (Δt) in ■ der Größenordnung der Grundperiodendauer (P) des Eingangssignales (U ^, UIN') nachgeschaltet ist, dessen Ausgang den Ausgang (UQTJT) der Schaltungsanordnung bildet sowie dem Steuereingang (4) des Schwellwertschalters (2) zugeführt ist und im getriggerten Zustand dessen Schwellwert (Usw) reduziert (Usw')-1. Circuit arrangement for hysteresis-based threshold value detection of the peak value of a periodic input signal, characterized in that the input signal
Figure imgf000007_0001
UIN ') is supplied to a threshold switch (2) with a controllable threshold (Usw), which is followed by a retriggerable timer (3) with a time constant (Δt) in the order of magnitude ■ of the basic period (P) of the input signal (U ^, UIN') , the output of which forms the output (U Q TJT) of the circuit arrangement and is fed to the control input (4) of the threshold switch (2) and, in the triggered state, reduces its threshold (Usw) (Usw ') -
2. Schaltungsanordnung nach Anspruch 1 für nullinien- symmetrische Eingangssignale, dadurch gekennzeichnet, daß dem2. Circuit arrangement according to claim 1 for zero-line symmetrical input signals, characterized in that the
Schwellwertschalter (2) ein Vollwellengleichrichter (1) vorgeschaltet ist und die Zeitkonstante (Δt) des Zeitgliedes (3) im Bereich der halben Grundperiodendauer (P) des Eingangssignales (UIN) liegt. Threshold switch (2) a full wave rectifier (1) is connected upstream and the time constant (Δt) of the timing element (3) is in the range of half the basic period (P) of the input signal (UIN).
3. Schaltungsanordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Schwellwertschalter (2) einen Komparator (5) aufweist, an dessen einen Eingang das Eingangssignal (UIN UI ') und an dessen anderen Eingang der Ausgang einer steuerbaren Referenzspannungsquelle (6) geführt ist, welche vom Ausgang des Zeitgliedes (3) angesteuert ist. 3. Circuit arrangement according to claim 1 or 2, characterized in that the threshold switch (2) has a comparator (5), at one input the input signal (UIN UI ') and at the other input of the output of a controllable reference voltage source (6) which is controlled by the output of the timing element (3).
PCT/AT1997/000231 1996-10-29 1997-10-28 Circuit for the hysteresis-related detection of the threshold value of the peak value of a periodic input signal WO1998019172A1 (en)

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AT1885/96 1996-10-29
AT188596A AT412600B (en) 1996-10-29 1996-10-29 CIRCUIT ARRANGEMENT FOR HYSTERESIZED THRESHOLD DETECTION OF THE PEAK VALUE OF A PERIODIC INPUT SIGNAL

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1187330A2 (en) * 2000-08-29 2002-03-13 Alcatel Voltage comparator circuit for the envelope of an AC voltage and method of comparing
CN103472288A (en) * 2013-08-30 2013-12-25 西北工业大学 Peak voltage detection circuit
US8921527B2 (en) 2002-02-14 2014-12-30 Chugai Seiyaku Kabushiki Kaisha Antibody-containing solution formulations

Citations (3)

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Publication number Priority date Publication date Assignee Title
US3541457A (en) * 1966-12-14 1970-11-17 Bausch & Lomb Peak occurrence detector circuit
GB2100082A (en) * 1981-06-08 1982-12-15 Tektronix Inc Automatically detecting signal levels
DE4326538A1 (en) * 1993-08-07 1995-02-09 Rohde & Schwarz Analog peak-value measuring instrument

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Publication number Priority date Publication date Assignee Title
JPS57111116A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Comparator having hysteresis
JPS63238566A (en) * 1987-03-27 1988-10-04 Fuji Elelctrochem Co Ltd Method for detecting alternating current input voltage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541457A (en) * 1966-12-14 1970-11-17 Bausch & Lomb Peak occurrence detector circuit
GB2100082A (en) * 1981-06-08 1982-12-15 Tektronix Inc Automatically detecting signal levels
DE4326538A1 (en) * 1993-08-07 1995-02-09 Rohde & Schwarz Analog peak-value measuring instrument

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1187330A2 (en) * 2000-08-29 2002-03-13 Alcatel Voltage comparator circuit for the envelope of an AC voltage and method of comparing
EP1187330A3 (en) * 2000-08-29 2004-02-25 Alcatel Voltage comparator circuit for the envelope of an AC voltage and method of comparing
US8921527B2 (en) 2002-02-14 2014-12-30 Chugai Seiyaku Kabushiki Kaisha Antibody-containing solution formulations
CN103472288A (en) * 2013-08-30 2013-12-25 西北工业大学 Peak voltage detection circuit

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AT412600B (en) 2005-04-25

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