WO1997049457A1

WO1997049457A1 - Biphasic defibrillation circuitry

Info

Publication number: WO1997049457A1
Application number: PCT/US1997/011421
Authority: WO
Inventors: Gary B. Stendahl; James E. Brewer
Original assignee: Survivalink Corporation
Priority date: 1996-06-27
Filing date: 1997-06-26
Publication date: 1997-12-31
Also published as: AU3793597A

Abstract

This invention is an apparatus for providing and delivery biphasic waveform defibrillation pulse. One embodiment includes a source (12) for generating a train of high frequency pulses coupled through a pulse transformer (14), a high speed diode (18) connected to the pulse transformer, a filter capacitor (20) connected to the high speed diode, acting as a low pass filter for the train of pulses, and a plurality of solid state switches (24, 26) for selectively coupling and decoupling the voltage across the filter capacitor to one of a plurality of capacitor banks (40, 42) which make-up the biphasic high voltage defibrillation pulse supply. Another embodiment is an apparatus for selecting from a pair of capacitor banks for delivery of positive and negative polarity portions of a biphasic defibrillator pulse. A further embodiment is a solid state patient isolator circuit capable of conducting bipolar portions of a biphasic defibrillation pulse when the isolator circuit is ON, and further capable of isolating circuitry upstream or downstream of the patient isolator when the isolator circuit is OFF.

Description

BIPHASIC DEFIBRILLATION CIRCUITRY

BACKGROUND OF THE INVENTION

Cardiac arrest, exposure to high voltage power lines and other trauma to the body can result in heart fibrillation which is the rapid and uncoordinated contraction of the cardiac muscle. The use of external defibrillators to restore the heartbeat to its normal pace through the application of an electrical shock is a well recognized and important tool for resuscitating patients. External defibrillation is typically used in emergency settings in which the patient is either unconscious or otherwise unable to communicate. Time is of the essence since studies have shown that the chances for successful resuscitation diminish approximately ten percent per minute.

Commercially available defibrillators such as those available from SurvivaLink Corporation, the assignee of the present application, are currently configured to produce monophasic waveform defibrillation pulses. Monophasic (i.e., single polarity) pulses such as a damped sine waveform and a truncated exponential waveform have been demonstrated to be effective for defibrillation, and meet standards promulgated by the Association for Advancement of Medical Instrumentation (AAMI). Electrical circuits for producing monophasic waveform defibrillation pulses are generally known and disclosed, for example, in the Persson U.S. Patent 5,405,316 which is assigned to the assignee of the present invention and the disclosure of which is herein incorporated by reference.

The efficacy of biphasic waveform pulses (effectively two successive pulses of opposite polarities) has been established for implantable defibrillators. For example, studies conducted on implantable defibrillators have shown that biphasic waveform defibrillation pulses result in a lower defibrillation threshold than monophasic pulses. A variety of theories have been proposed to explain the defibrillation characteristics of biphasic waveform pulses but no definite conclusions have been reached. It is anticipated that the efficacy and advantages of biphasic waveform pulses that have been demonstrated in implantable defibrillators will be demonstrated in external defibrillators as well.

It has been known to use electromechanical vacuum or gas filled relays to switch the output of storage devices to form biphasic waveforms. These devices are electrically suitable for use in external defibrillators, but pose practical problems in that they are generally fragile, large and very expensive. One important shortcoming is that such devices are not suitable for breaking or interrupting large voltages and currents and, when called upon to do so, often damage the relay contacts. External defibrillators output defibrillation pulses in the range of 2000-3000 volts. The typical load for external defibrillators are in the range of approximately 25 - 225 ohms. At these voltages and resistances, the circuits must be able to handle currents in excess of 100 amps. This shortcoming is particularly significant when it is desired to truncate a first portion of a biphasic defibrillation pulse. In such circumstances, to truncate the pulse or waveform without damage to the contacts, it is known to short-circuit the capacitor bank supplying the pulse to be terminated or truncated. Such an approach suffers from the further shortcoming that the energy short- circuited is lost to the system, increasing inefficiency and adding electrical (and mechanical) stress to the components carrying short-circuit current. Thus, there is a continued need for a low cost, compact, and rugged switching circuit.

Known external defibrillators require outputs in excess of about 2000 volts. Currently, architecture constraints limit the energy delivery path to using capacitors having voltage ratings not greater than about 330 volts. Thus, a bank of capacitors stacked in series are required to deliver the 2000 volts needed. The support circuitry associated with the known systems is expensive and not always reliable. There is a continued need for a reliable cost effective circuit for charging capacitors for external defibrillators. Patient isolation circuits for defibrillators are not new. In known isolation circuits for monophasic defibrillation, solid state switches such as silicon controlled rectifiers (SCRs) or thyristors are used. Such devices are not readily adaptable to biphasic defibrillation since they are only capable of unipolar conduction. Thus, there is a continued need for a patient isolation circuit for biphasic defibrillation.

SUMMARY OF THE INVENTION

One aspect of the present invention provides an external defibrillator having a high voltage circuit for delivering biphasic waveform defibrillation pulses. In the embodiment of the present invention, the high voltage circuit includes first and second output terminals configured for electrical interconnection to electrodes, a supply terminal configured for electrical interconnection to a charge voltage potential, and two capacitor banks for storing electrical energy, with one bank used for the first (positive polarity) portion and the other bank for a second (negative polarity) portion of a biphasic defibrillation pulse. A pair of solid state charge switches are provided and are individually operable and responsive to charge control signals from a pair of charge control circuits to selectively electrically connect each of the capacitor banks to the pulse generator to charge the capacitor banks to a desired charge voltage potential. Another aspect of the present invention provides a low cost, compact and rugged external defibrillator having a high voltage and current switching circuit for delivering biphasic waveform defibrillation pulses. In this embodiment of the present invention, the high voltage circuit includes first and second output terminals configured for electrical interconnection to electrodes, a supply terminal configured for electrical interconnection to a charge voltage potential, and two capacitor banks for storing electrical energy, with one bank used for the first (positive polarity) portion and the other bank for a second (negative polarity) portion of a biphasic defibrillation pulse. A pair of solid state charge switches are provided and are individually operable and responsive to charge control signals from a pair of charge control circuits to selectively electrically connect each of the capacitor banks to the pulse generator to charge the capacitor banks to a desired charge voltage potential.

Each of a pair of solid state selector circuits are connected to and individually responsive to respective selector driver circuits to selectively electrically connect one of the capacitor banks to output circuitry for providing one portion of the biphasic defibrillation pulse. Each of the driver circuits is responsive to a respective selector control circuit to control the state of the selector circuit to which it is connected. Each selector circuit preferably includes a pair of insulated gate bipolar transistors (IGBT's) connected in series and voltage balancing resistors connected in parallel therewith.

Another aspect of the present invention provides a patient isolation circuit for biphasic defibrillation. The output circuit of this embodiment includes a pair of isolator circuits and an isolator control circuit operable to selectively couple biphasic high voltage pulses to patient leads, and is further operable to isolate the internal circuitry of the defibrillator. The isolation serves two fundamental purposes. The first is to isolate the patient from high voltages during charging. The second is to isolate the circuitry from damage due to externally generated electrical energy which may appear on the patient leads from sources such as another defibrillation charge from another source. The patient isolator of the present invention utilizes steering diodes in combination with low-cost conventional SCRs to allow bipolar and thus biphasic defibrillation pulse delivery.

Yet another aspect of the present invention provides a low cost, reliable circuit for charging capacitors in an external defibrillator. The switches of this embodiment are capable of handling higher voltages which are able to utilize capacitors having higher voltage ratings. Thus, the same defibrillation output voltage can be achieved with fewer capacitors. This provides significant economies of scale by substantially reducing the size, weight and cost of the circuit.

A final aspect of the present invention has a power source which is connected to an input terminal. The input terminal is connected to a plurality of capacitors connected in series. A plurality of switching devices are also connected in series with the plurality of capacitors. A first string of diodes are provided in parallel with the capacitors to provide clamping control. A second string of diodes are provided in parallel with the capacitors to distribute current to the plurality of capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a capacitor charge control circuit in accordance with the present invention. Figure 2 illustrates a passive filter along with a pictorial representation of a signal before and after the filter.

Figure 3 illustrates one embodiment of a monitoring circuit of the circuit illustrated in Figure 1.

Figure 4 is a block diagram of a capacitor bank selector and isolation subsystem.

Figure 5 is a more detailed block diagram of an individual selector, driver and control from Figure 4.

Figure 6 is a simplified schematic diagram of an isolation circuit according to one embodiment of the present invention. Figure 7 is a schematic diagram of a fast isolated insulated gate bipolar transistor (IGBT) driver according to one embodiment of the present invention.

Figure 8 is a schematic diagram of a prior art defibrillation circuit. Figure 9 is a simplified circuit diagram of a charging and delivery circuit according to one embodiment of the present invention.

Figure 10 is an other embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to Figure 1, a charge control circuit 10 may be seen. Circuit 10 includes a pulse generator 12 connected to a pulse transformer

14 which is connected to a passive rectifying and filtering circuit 16. Circuit

16 is preferably made up of a high speed (fast recovery) diode 18, which is preferably a UF4007 type, available from General Instruments, and a capacitor 20 which may be in the range of 3-10 microfarads. It should be noted that active filters, as are commonly known, are also equally applicable. Circuit common is indicated by an inverted triangle 22, and an output 23 of the rectifying and filtering circuit 16 is connected to first and second charge switches 24, 26. Charge switches 24, 26 are each preferably formed of one or more solid state switching devices such as a silicon controlled rectifier (SCR), a field effect transistor (FET), or an insulated gate bipolar transistor (IGBT). Such devices may be connected in series (to increase voltage capability) or in parallel (to increase current capability) as is well known in the art. Each of the charge switches 24, 26 is controlled by a separate one of a pair of charge control circuits 28, 30.

The respective outputs 32, 34 of the charge switches 24, 26 are individually connected to one of a pair of capacitor banks 40, 42. Output 32 is connected to a first capacitor bank 40, and output 34 is connected to a second capacitor bank 42. This portion of the circuitry will be described in detail with reference to a pair of capacitor banks but it should be noted that additional capacitor banks may also be included without departing from the spirit or scope of the invention. The output of capacitor bank 40 is connected to an electrode terminal 47 and the output of capacitor bank 42 is connected to an electrode terminal 49.

The circuit is designed to output to electrode terminals 47 and 49 a high voltage defibrillation pulse in the range of approximately 2000 - 3000 volts in one embodiment. Because the typical impedance values present in external defibrillators is in the range of 25 - 225 ohms, currents in excess of 100 amps are present. It should be noted however that greater or lesser discharge voltages can also be delivered without departing from the spirit or scope of the invention. In order to generate and deliver the voltage levels desired for defibrillation, a two step process is required. The first step is that of charging the capacitors. The second step is that of discharging the capacitors. To charge low cost, reliable capacitors rapidly to the desired voltage levels, the present invention utilizes charge control circuits 28, 30 and charge switch circuits 24, 26 to charge the capacitors in parallel. When connected in parallel, the total capacitance of a particular capacitance bank is the sum of all the capacitors connected in parallel, while the voltage across each of the individual capacitors is equal. To discharge the capacitors to electrode terminals 47, 49, charge control circuits 28, 30 and charge switch circuits 24, 26 configure the capacitors of a capacitor bank in series. This reduces the total capacitance to a fractional value of the individual capacitors and increase the voltage to the sum of the voltages across each individual capacitor. The capacitor banks are preferably of differing capacitive values or differing voltage capacities. For example, in one embodiment, capacitor bank 40 has a total capacitance of 7200 microfarads while capacitor bank 42 has a total capacitance of 440 microfarads when connected in parallel for charging. Therefore, capacitor bank 42 will charge much more rapidly than will capacitor bank 40. During discharge, capacitor bank 40 has a total capacitance of 200 microfarads while capacitor bank 42 has a total capacitance of 110 microfarads while connected in series. It should be noted that many other capacitor banks could be utilized having many different capacitance values, or all having the same capacitance value without departing from the spirit or scope of the invention.

The operation of the charge control circuit 10 is as follows. Pulse generator 12 supplies a series, or train, of preferably square wave pulses, typically at a 50% duty cycle and having an amplitude of approximately 400 volts, at a frequency preferably between 5 KHz and 500 KHz. These pulses have a very rapid rise time. Since the fast rise times and high frequencies of the pulses cause avalanching of most common solid state devices of reasonable cost, the pulses are first passed through passive filter circuit 16. Diode 18 is a fast recovery diode that provides for charging of capacitor 20 and prevents discharge of the capacitor 20 through secondary 36 of pulse transformer 14. Capacitor 20 is preferably selected to be able to absorb and store the energy from at least one charge pulse from pulse generator 12.

As stated above, use of a pulse train with a very rapid rise time on individual pulses is desired, but would lead to avalanche breakdown of standard switches if coupled directly thereto. This would cause the switches to lose control of charging, and may lock the switches on, causing the capacitors to be continually charged until they are destroyed. This consequent loss of charging control is unacceptable. Use of rectifying and filtering circuit 16 avoids such avalanche triggering of solid state switches 24, 26 by keeping high dV/dt values from reaching switches 24, 26, allowing ordinary solid state devices to be used for switches 24, 26.

Figure 2 illustrates the passive filter along with a pictorial representation of a signal before and after the filter. As can be seen in waveform 19 illustrates the signal coming out of pulse generator 12. This signal is a series of square wave pulses having an amplitude of approximately 400 volts. After passing through filter 16, waveform 21 is obtained which is in the form of a DC level with a generally triangular ripple component. When the ON portion of waveform 19, illustrated at 19a, is seen at diode 18 the diode is forward biased allowing capacitor 20 to charge. Capacitor 20 is charged while diode 18 is forward biased. When signal 19 drops to zero, illustrated at 19b, diode 18 shuts off, halting the charging of capacitor 20.During the off period of diode 18 when the stored energy from capacitor 20 is transferred to the capacitor banks it's voltage drops slightly causing the triangular ripple voltage illustrated in waveform 21 at 21a. After capacitor 20 has a chance to discharge the energy stored therein, diode 18 turns back on due to the presence again of a positive voltage from pulse generator 12 causing waveform 21 to rise to a charged level, at 21b.

The DC charge on capacitor 20 is available to each of switches 24, 26 via lead 23 to be distributed to the capacitor banks as needed. It is to be understood that one or both of switches 24, 26 are on during charging. Both switches 24 and 26 may be on together or only one may be on, but at least one must be on during charging. When one or both of switches 24, 26 is on, the charge on capacitor 20 is coupled to the respective one or both of capacitor banks 40, 42. As previously stated, the value of capacitor 20 is preferably chosen to be able to absorb and store the energy from one pulse. The energy stored in capacitor 20, which is now in the form of a DC level with a generally triangular ripple component, is available to be delivered to either capacitor bank via charge switches 24 or 26. It is also to be understood that the capacitor banks include slower acting diodes (illustrated as DI et sec\. in Figure 3 of US Patent 5,405,361, the disclosure of which is hereby incorporated by reference). Thus the pulse provided by transformer 14 is not instantly applied to the capacitors and the energy that is not immediately applied is stored in capacitor 20 and continues to be delivered between pulses from generator 12.

Circuit 10 also includes voltage monitoring circuits 43, 45 for monitoring the voltage on capacitor banks 40 and 42, respectively. As can be seen in Fig. 1, monitor circuits 43 and 45 are connected to the respective capacitor banks and charge control circuit. Monitoring circuits 43 and 45 are illustrated schematically as block diagrams because there are many different embodiments of monitoring circuits that may be used without departing from the spirit or scope of the invention, such as analog circuitry, digital circuitry and solid state components, for example. Figure 3 illustrates one preferred embodiment of monitoring circuit 43. It should be noted that monitoring circuit 45 is the same as monitoring circuit 43. As can be seen, an operational amplifier 53 is provided as is an analog to digital converter 55 and a microprocessor 57. Amplifier 60 is connected to capacitor bank 40 via a plurality of resistors 59. In operation, monitoring circuit 43 has a database of preset values stored in microprocessor 57. When capacitor bank 40 reaches the preset value selected in processor 57, charge control circuit 28 is instructed to halt the charging of capacitor bank 40. In an alternative embodiment, microprocessor 57 has the capability of computing an appropriate predetermined value for charging the respective capacitor bank.

When in the charging mode, one or a plurality of capacitor banks may be charged simultaneously. In the embodiment illustrated in Figure 1 having first and second capacitor banks 40 and 42, if both capacitor banks 40 and 42 are being simultaneously charged, when capacitor bank 42 is fully charged, charge switch 26 is opened as a result of a command from monitoring circuit 45 and all of the charge available at capacitor 20 is then applied to capacitor bank 40 instead of splitting it between the two capacitor banks. When capacitor bank 40 is completely charged, charge switch 24 is opened as a result of a command from monitoring circuit 43. Capacitor banks 40 and 42 are now fully charged and ready to be switched into series for discharge. Referring now most particularly to Figure 4, an output circuit 50 suitable for providing biphasic defibrillation pulses may be seen. Output circuit 50 includes a capacitor bank circuit 52, a selector circuit 54, and an isolator circuit 56. The capacitor bank circuit includes first and second capacitor banks 40, 42, each of which have respective phase delivery command lines 44, 46. In the embodiment illustrated, capacitor bank 40 is configured to discharge a positive first phase of the biphasic output pulse while capacitor bank 42 is configured to discharge a negative second phase. It should be noted that additional capacitor banks can be added without departing from the spirit or scope of the invention. Selector circuit 54 has a pair of preferably identical selector subsystems. One subsystem 60 is indicated by a chain line. Subsystem 60 includes a solid state phase selector switch 62 connected to a phase selector driver 64 which in turn is connected to a select phase control 66. It is to be understood that select phase control 66 provides a signal on line 68 to activate and deactivate phase selector driver 64.

When phase selector driver 64 is activated, it drives phase selector switch 62 to a state of conduction (ON) between lines 72 and 74, connecting capacitor bank 42 to isolator circuit 56 and ultimately to a patient when isolator circuit is itself in a conducting state as will be described infra . When select phase control 66 deactivates phase select driver 64, phase selector switch 62 is rendered nonconductive (OFF) between lines 72 and 74, thus stopping any remainder of the portion of a biphasic defibrillation pulse from being delivered from the capacitor bank 42 to a patient 76. It is to be understood that the phase 1 selector subsystem (connected to capacitor bank 40) is formed of the same elements and operates identically to subsystem 60 in the embodiment shown in Figure 4. To provide a monophasic defibrillation pulse, only the phase 1 selector subsystem is activated, since capacitor bank 40 is connected to provide a positive polarity output and capacitor bank 42 is connected to provide a negative polarity output.

When providing biphasic defibrillation pulse, it has been found preferable to proceed according to the following sequence:

1. Turn phase 1 selector switch ON, providing a first, positive polarity, exponentially decaying portion of the pulse.

2. Turn phase 1 selector switch OFF, truncating the first portion of the pulse at a desired point. 3. After a time delay, turn phase 2 selector switch

ON,providing a second, negative polarity, exponentially decaying portion of the pulse.

4. Turn phase 2 selector switch OFF, truncating the second portion of the pulse at a desired point. One important aspect of this embodiment is the reduction of the transition time between phase 1 and phase 2. In known systems utilizing

SCRs as switching mechanisms, any charge in the capacitors must be reduced below the level of the holding current for the SCR before a phase shift can occur. This can take up to 10 seconds due to the large amount of charge typically remaining on the capacitors. This is so even though photoflash capacitors are typically utilized due to their rapid discharge. In these known systems, SCR dump circuits are also required which are complicated circuits which require many components for each capacitor in the capacitor bank and which force the device to throw away all current stored in the bank.

In this embodiment, the SCR's have been replaced by IGBT's and photoflash capacitors are no longer needed, allowing cheaper, mass- produced products to be used. The delay of switching between phase 1 and phase 2 depends only on the length of time to shut off phase 1 long enough to allow phase 2 to be energized. This time frame is on the order of microseconds. The discharge of current from either capacitor bank 40 or 42 may be halted at any time and is able to do so when voltage levels are in excess of 2000-3000 volts. The discharge of an extremely high voltage phase of opposite polarity is begun within 2-3 microseconds following the truncation of the first phase.

Referring now also to Figure 5, details of the phase selector switch 62 may be seen. This embodiment will be described with reference to a pair of IGBT's, but it should be noted that more may be used as will be described below. To withstand the high voltages encountered in providing defibrillation pulses (whether monophasic or biphasic) two IGBT's are connected in series. A first IGBT 80 has a power input 82 and a power output 84 and a signal input or gate 86. Similarly, a second IGBT 90 also has a power input 92, a power output 94, and a signal input, or gate, 96. Referring now also to Figure 4, power input 82 is connected to lead 72 carrying the output of capacitor bank 42. Power output 84 is connected to power input 92 and power output 94 is connected to lead 74. The connection 70 between phase selector driver 64 and phase selector switch 62 is actually made up of four connections 100, 102, 104, 106. Connections 100 and 102 couple an isolated driver 110 to IGBT 80. Similarly connection 68 between the select phase control 66 and the phase selector driver 64 actually includes two leads 112, 114. As is shown, driver 116 for IGBT 90 (and associated connections) is identical to that described in connection with driver 110. Each of IGBT's 80, 90 is preferably rated to deliver a 360 Joule pulse into a 25 ohm load [at pulse repetition rate of 1 per 5 seconds], and is also preferably rated to withstand 1200 volts in the OFF condition. One such IGBT is type is IXGH25N120A available from IXYS. To prevent unbalanced voltage between IGBT's 80, 90 in the OFF condition, resistors 120, 122 are connected in series with each other and in parallel as a voltage divider across the series connection of IGBT's 80, 90. The resistance of each resistor 120, 122 is preferably 3 mega ohms.

By adding additional IGBT's or by using IGBT's having higher current and voltage limits, the circuit can output each phase successfully at any current or voltage level. Specifically, this allows the switching from phase 1 to phase 2 at voltage levels greater than 1000 volts. For example, by putting four 1200 volt IGBT's in series for each phase, the circuit can withstand (or hold off) 4800 volts per phase or a total of 9600 volts.

The operation of selector subsystem 60 is as follows. When it is desired to turn phase selector switch 62 ON, a low level signal is generated by select phase control 66, providing a logic ON signal on lead 112 and removing a logic OFF signal on lead 114. Drivers 110 and 116 may be any type of voltage isolating driver circuits sufficient to meet the speed and voltage requirements of the defibrillator system. Presently, magnetically isolated conventional driver circuits are preferred. When it is time to turn off phase 1, IGBT's 80 and 90 are closed thus halting the output to the patient without dumping the charge through an auxiliary SCR dumping circuit. The same is done for phase 2. During the time that the current flows through the IGBT's, peak currents are all within the safe operating areas. Because dumping the charge in capacitor banks 40 and 42 is not needed to change phases, any dumping circuitry desired can be constructed from non-high speed components because time is not critical. This greatly reduces the cost of the components required.

The isolation circuit of the present invention protects in both directions. This is done to protect both the patient and the circuitry of the defibrillator. In one direction, the isolation circuit protects the patient from any leakage current or from large charges accidentally being applied to the patient. In the opposite direction, the isolation circuit prevents the internal circuitry from damage due to externally generated electrical energy which may appear on the electrodes from sources such as another defibrillator.

Referring now most particularly to Figures 4 and 6, the output of phase selector switches 62, 63 are combined on lead 74 and connected to a first patient isolator circuit 130. An output 132 of isolator circuit 130 is connected to the patient 76 via a first patient electrode 134. A second patient electrode 136 in contact with the patient is connected to a return line 138 which serves as an input to a second patient isolator circuit 140. An output from isolator circuit 140 on line 142 is connected to both capacitor banks 40, 42 to complete the output defibrillation circuit path. In the embodiment illustrated, patient isolator circuits 130, 140 are preferably identical. The details of each patient isolator circuit 130, 140 are illustrated in Figure 6, with circuit 130 used as an example.

A single isolator control circuit 144 is connected to both patient isolator circuits 130, 140, with the pulse control input connected to two gate drive circuits, only one of which is shown in Figure 6. Gate drive circuit 146 may be of conventional design appropriate to isolate and gate a pair of SCRs 150, 152 ON selectively, when commanded by the pulse control input. When ON, SCRs 150, 152 will conduct the positive polarity portion of a biphasic defibrillation pulse through diodes 158, 160. A pair of 3 mega ohm resistors 162, 164 provide voltage balancing between devices 150, 152 when in the OFF condition. Diodes 154, 156, 158, 160 will block conduction between leads 74 and 132 when SCRs 150, 152 are OFF. Furthermore, it is to be understood that the IGBTs in phase selector switches 62, 63 will provide rapid shutoff of the defibrillation pulse, and thus the lack of self commutation in SCRs 150, 152 will not impair system performance by delaying shutoff until the defibrillation pulse current falls below the holding current for the SCRs. It is further to be understood that other solid state devices such as FETs or IGBTs could also be used without departing from the spirit or scope of the present invention.

A further embodiment of the present invention is a fast isolated IGBT driver circuit for truncating waveforms at any point during the delivery to a patient. This embodiment will be described in detail with respect to Figure 7, however, reference will also be made to Figures 4 and 5.

Figure 7 illustrates the phase select drivers 64 from Figure 4 which are also illustrated at 110 and 116 in Figure 5. As previously stated, the drivers drive the selector circuits to activate or truncate waveforms in an AED. A single fast isolation driver (110 and 116) according to this embodiment is illustrated in Figure 6. As illustrated in Figure 6, the driver of the preferred embodiment is comprised of two identical portions, upper portion 151 and lower portion 153 for reasons to be described below.

Upper portion 151 has first and second field effect transistor (FET) drivers 155, 157, respectively that comprise an input circuit portion. In this embodiment these drivers are high current, low impedance drivers. An input line 159 is provided to driver 155 and an input line 161 is provided to driver 157. In the embodiment illustrated, inputs 159 and 161 receive a 30KHz, 50% duty cycle signal from select phase control circuit 66 as illustrated in Figure 5. Impedance driver 155 has an output 163 while impedance driver 157 has an output 165. An isolation transformer 166 is provided having a primary coil 168 and a secondary coil 170. Secondary coil 170 has first and second output terminals 172, 174 respectively. In the preferred embodiment illustrated isolation transformer 166 is a one to one transformer.

Biasing circuitry 175 is provided, connected to transformer 166. Biasing circuitry 175 is used to bias the IGBT as will be described in detail below. An N-type field effect transistor (FET) 176 is provided and is connected across secondary coil 170 of transformer 166. FET 176 has a gate 178, a source 180 and a drain 182. Source 180 is connected to first output terminal 172 of transformer 166 at node 184. A resistor 186 is provided and is connected between gate 178 and output terminal 174 at node 188. A P- type FET 190 is also provided having a gate 192, a source 194 and a drain 196. Source 194 is connected to node 184 while gate 192 is connected to node 188 through a resistor 198. In the preferred embodiment of the present invention, resistors 186 and 198 are one kiliohm resistors, however, it should be noted that greater or lesser resistance can also be used without departing from the spirit or scope of the present invention.

A pair of diodes 200 and 202 are provided having anodes 204, 206 and cathodes 208, 210, respectively as illustrated in Figure 7. Anode 204 of diode 200 is connected to drain 182 while anode 206 is connected to cathode 208 at node 212. Cathode 210 is connected to drain 196 of FET 190. A capacitor 214 is connected between nodes 212 and 188. In the preferred embodiment capacitor 212 is a .1 microfarad capacitor, however, it should be noted that larger or smaller capacitors could also be used without departing from the spirit or scope of the invention. An insulated gate bipolar transistor (IGBT) 216 is provided having a gate 218, a collector 220 and an emitter 222. Gate 218 is connected to node 212, emitter 222 is connecting to node 188 and collector 220 is output to isolator circuit 56, as illustrated in Figure 4.

As previously stated, lower portion 153 mirrors upper portion 151. Accordingly, each element in lower portion 153 is identified with the same element number as in upper portion 151 with the addition of a prime. In the embodiment illustrated in Figure 7, the maximum output defibrillation pulse is approximately 2,400 volts. In order to effectively handle this voltage, the IGBT's selected are rated at approximately 1200 volts breakdown. As can be seen, IGBT 216 and 216' are connected in series which allows approximately 2400 volts breakdown to be handled effectively. This allows the output waveform to be interrupted at any point in the delivery of energy to the patient which also allows a selection of either of the two phases when constructing the biphasic waveform output. Additional IGBT's could be also be placed in series for higher voltage levels. The operation of the circuit of Figure 7 will be described in detail with regards to upper portion 151, however, it should be understood that lower portion 153 operates just the same. When driver 155 is receiving a positive input signal and driver 157 is receiving a zero potential signal, the signal at output 165 remains zero while the signal at 163 is pulsing at a positive 12 volts. As stated before, isolation transformer 166 is a one to two transformer, therefore, output terminal 172 will be positive compared to output terminal 174. In this situation, gate 178 is negative with respect to source 180 which causes FET 176 to be turned on. At the same time, gate 192 is negative with respect to source 194 which turns FET 190 off. With FET 176 on, diode 200 is forward biased and the charge of energy from transformer 166 is stored in capacitor 214. This charge is replenished at each pulse and appears as direct current (DC) forward biasing IGBT 216 causing it to be turned on. With IGBT 216 on, a defibrillation pulse is allowed to be delivered to a patient.

When the signal and input 161 goes high, while the signal at 159 goes low, output 163 goes to zero while output 165 is pulsing at 12 volts. This causes a negative pulse to appear at output terminal 172 with respect to output terminal 174. When this occurs, FET 176 is turned off and FET 190 is forward biased, turning it on. The negative voltage at source 194 is felt at cathode 210 of diode 202 which passes it along to capacitor 214 and gate 218. Again this appears as DC and has the effect of making gate 218 negative with respect to emitter 222 which turns IGBT 216 off. When IGBT 216 shuts off, the defibrillation waveform is truncated.

The amount of energy transferred through the transformer with each pulse is enough to cause this action to occur at a very fast rate. The IGBT gate signal can switch from plus 20V to minus 20V and because of the negative gate bias, the time for IGBT turn off is reduced to be in the range of 200 to 400 nanoseconds. In one embodiment, the turn off time is reduced to less than 320 nanoseconds and preferably to about 300 nanoseconds. This is needed to truncate the defibrillator output pulse by turning the IGBTs OFF as fast as is practical to minimize the trajectory time through the active region.

A further embodiment of the present invention is a high voltage series diode circuit for charging capacitors in an external defibrillator. In U.S. Patent No. 5,405,361, issued to Persson, which is assigned to the Assignee of the present invention, the disclosure of which is herein incorporated by reference, a high voltage circuit 310 is disclosed which charges a plurality of main storage capacitors in parallel. This circuit is illustrated in Figure 8. Figure 8 illustrates a circuit having a plurality of capacitors C1-C6 connected in series. A plurality of thyristors TH1-TH6 are provided connected in series with capacitors C1-C6. A string of diodes Dl- D6 are provided, with each diode connected in parallel with its associated capacitor and thyristor. For instance, diode D2 is connected in parallel with capacitor C2 and thyristor TH2. A series string of MOSFETS Q1-Q6 are provided and are also connected with each MOSFET connected in parallel with its associated capacitor and thyristor. MOSFETS Q1-Q6 are 400 V MOSFETS. A plurality of photoisolators 312, 314, 316, 318, 320 and 322 are connected to MOSFETS Q1-Q6, respectively. Photoisolators 312, 314, 316 318, 320 and 322 are provided to control MOSFETS Q1-Q6. A pair of constant current drivers 324, 326 are also provided to drive the photo isolators.

In operation, a positive charge current is applied through diodes Dl- D6 which allow current to flow to the positive side of each capacitor but are reverse biased during the deliver cycle. The negative charge voltage is applied to the negative side of the capacitors through MOSFETs Q1-Q6, referred to as the "clamp" circuit 330, which is switched on during charge and switched off during delivery. As stated above, the string of MOSFETs is controlled by photoisolators 312, 314, 316, 318, 320 and 322, due to the fact that the first MOSFET will have n - 1 capacitor voltages applied to it.

The clamp circuit has proven to be the least reliable part of high voltage circuit 310, and a MOSFET will, on a rare occasion, fail due to a switching transient during delivery which exceeds the MOSFET breakdown voltage, marginally higher than the actual working voltage. This could be caused also by a short burst of switching noise on the clamp circuit control line during the delivery which can momentarily turn on the MOSFETs. Either failure results in catastrophic destruction of the high voltage circuit. This failure has always occurred during the test cycle in manufacturing and none have occurred in the field, but troubleshooting and repair costs can be high. Since the charging circuit is limited to the breakdown voltage of the clamp circuit MOSFETs, only about 375 volts can be safely applied to each capacitor C1-C6. With continued reference to Figure 8, assuming clamp control circuit 30 is asserted and MOSFETs Ql through Q6 are turned on, the positive side of the charge source is connected to DI which distributes the charge current to Cl and the rest of the capacitors. D2 further distributes the charge current to C2 and the rest of the capacitors and so on for each of the remaining diodes in the string. The negative side of capacitor Cl is connected directly to ground, which is also the negative charge current connection. C2 is connected to the negative charge through Ql in clamp circuit 330. C3 is connected to negative charge current through Q2 and Ql to ground. Ql handles the charge current for capacitors C2 through C6 in the same fashion. Each successive MOSFET in the chain handles one less capacitor's charging current. To avoid catastrophic failure when delivering energy to the output, clamp circuit 30 must be turned off before activating thyristor switches TH1 through TH7. One aspect of the present invention provides an improved high voltage circuit having switches capable of handling higher voltages which are able to utilize capacitors having higher voltage ratings. Thus the same defibrillation output voltage can be achieved with fewer capacitors. This substantially reduces the size, weight and cost of the circuit of the present invention.

Figure 9 illustrates a high voltage circuit 340 according to one aspect of the present invention. As can be seen, MOSFETs Q1-Q6 from Figure 8 are replaced with switching elements D13-D17. Switching elements D13- D17 have greater than 400 volt breakdown voltages in the off condition and cannot be accidently turned on during deliver. In the embodiment illustrated, the switching elements are diodes. It should be noted that the present invention is described and illustrated as having six charging capacitors, and six switching elements, but it is understood that more or less capacitors and switches can also be used without departing from the spirit or scope of the present invention.

A plurality of thyristors TH7-TH13 and a plurality of capacitors C7- C12 are connected in series as illustrated in Figure 9. A first series set of diodes D7-D12 are provided connected in parallel with thyristors TH7- TH13 and capacitors C7-C12. As stated above, diodes D13-D17 are provided as switches and are connected in parallel with thyristors TH7-TH13 and capacitors C7-C12 to distribute current to capacitors C7-C12. A negative charge current terminal 342 and a positive charge current terminal 344 are provided as illustrated, with a charge switch 346 connected between negative charge terminal 342 and the series of capacitors. The output of TH13 is approximately a 2000-3000 volt output pulse that is connected to electrodes (not shown). Thyristors TH7-TH13 are typically 400-1200 voltage rated thyristors and are utilized to control switching from charge and discharge states.

As a charge pulse is applied to the charge terminals, diodes D13 through D17 are forward biased, distributing current to capacitors C7-C12 negative terminals. It should be noted that the charge current for C7 flows from the positive plate of C7 through diode D7 to common, which is also charge current positive. The charge current for C12 flows through charge switch 346 directly to C12, then from the positive plate of C12 through the series string of diodes D7-D12. When the capacitors have been charged, the charge generator is turned off and charge switch 346 is also turned off. After charge switch 346 is turned off, series thyristors TH7-TH13 can now be triggered simultaneously to connect all six capacitors in series and deliver the total energy to the output terminals. Once again, it should be noted when the series thyristors are triggered, all diodes used for charging are reversed biased. The charge current switch must be rated to withstand n-1 capacitor voltages added in series, where n is the total number of capacitors charged.

Figure 10 illustrates a circuit 347 similar to Figure 9 except the charge voltage per capacitor is much higher therefore fewer support components are needed. In the circuit illustrated in Figure 10, capacitors C13-C16 are provided in series, with thyristors TH14-TH18 also connected in series. A first series set of diodes D18-D21 are provided in parallel with the capacitors and thyristors and a second series set of diodes D22-D24 are provided in parallel with the capacitors and thyristors. A charge switch 348 is provided between a negative charge terminal 350 and the capacitors.

The operation of circuit 347 is the same as that described above with reference to Figure 9. The capacitor voltage rating is now the main limitation in raising the voltage per stage in the capacitor bank. It should be noted that as capacitor voltages continue to rise, a two capacitor circuit is envisioned.

The invention is not to be taken as limited to all of the details thereof as modifications and variations thereof may be made without departing from the spirit or scope of the invention.

Claims

What Is Claimed Is:

1. A circuit for selectively charging at least one capacitor bank in a defibrillator, the circuit comprising: a pulse generator for generating a train of pulses; a pulse transformer having a primary winding connected to the pulse generator and having a secondary winding magnetically coupled to the primary winding; a low pass filter having an input and an output wherein the input of the filter is connected to the secondary winding of the pulse transformer; at least one charge switch having an input and an output wherein the input of the at least one charge switch is connected to the output of the low pass filter; and at least one capacitor bank connected to the output of the at least one charge switch.

2. The circuit as in claim 1 wherein the low pass filter comprises a: a high speed diode connected in series with a first end of the secondary winding of the pulse transformer; and a filter capacitor connected to the high speed diode and a second end of the secondary winding and having sufficient capacitance to act as a low-pass filter for the train of pulses delivered from the pulse generator means by the pulse transformer.

3. The circuit as in claim 2 further comprising at least one charge control circuit connected to the output of the low pass filter and the input of the at least one charge switch.

4. The circuit as in claim 3 further comprising at least one monitoring circuit connected to the at least one capacitor bank and the at least one charge control circuit.

5. An apparatus for delivering biphasic high voltage defibrillation pulses in an external defibrillator circuit comprising: a pulse generator; a pulse transformer having a primary winding connected to the pulse generator and having a secondary winding magnetically coupled to the primary winding; a first capacitor bank comprised of at least one capacitor; a second capacitor bank comprised of at least one capacitor; a first switch having an input connected to the secondary winding of the pulse transformer and an output connected to the first capacitor bank; a second switch having an input connected to the secondary winding of the pulse transformer and an output connected to the second capacitor bank; electrode terminals for delivering the high voltage defibrillation pulse to a patient; a third switch connected between the first capacitor bank and the electrode terminals for selectively providing and interrupting a path therebetween; and a fourth switch connected between the second capacitor bank and the electrode terminals for selectively providing and interrupting a path therebetween.

6. The apparatus as in claim 5 further comprising a first phase selector driver connected to the third switch and a second phase selector driver connected to the fourth switch.

7. The apparatus as in claim 6 further comprising a first select phase control circuit connected to the first phase selector driver and a second select phase control circuit connected to the second phase selector driver.

8. An improved external defibrillator, the improvement comprising a pair of separate capacitor banks for delivering biphasic high voltage defibrillation pulses to electrodes and a biphasic selector switch having a pair of solid state switching means wherein one of the pair of switching means is connected between one of the capacitor banks and the electrodes for selectively providing and interrupting a path therebetween and the other of the pair of switching means is connected between the other capacitor bank and the electrodes.

9. An external defibrillator high voltage patient isolation circuit for selectively delivering and isolating high voltage biphasic waveform defibrillation pulses, the patient isolation circuit comprising: a) a diode bridge circuit having four diodes connected between an input terminal and an output terminal and having a pair of intermediate terminals, wherein one of the input and output terminals is connected to a means for providing a source of biphasic high voltage and the other of the input and output terminals is connected to a means for connecting defibrillation pulses to a patient electrode; b) a pair of solid state switching devices connected together in series across the pair of intermediate terminals; and c) a pair of resistors, with each one of the pair of resistors connected across one of the pair of switching devices to balance voltages across the switching devices wherein the isolation circuit will provide a high impedance to block biphasic high voltages at either of the input or 7/49457 PC17US97/11421

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output terminal from appearing at the other of the input or output terminal when the switching devices are OFF, and a low impedance between the input and output terminals to provide a path for biphasic defibrillation pulses between the means for providing a source of biphasic high voltage and the means for connecting defibrillation pulses to a patient when the switching devices are ON.

10. A fast isolation driver system comprising: an input circuit for receiving input signals from a plurality of input lines; an isolation transformer connected to the input circuit wherein the isolation transformer has first and second output terminals; biasing circuitry connected to the first and second output terminals; and an insulated gate bipolar transistor (IGBT) having its gate connected to the biasing circuitry and its emitter connected to the second output terminal wherein the IGBT switches between operational states in response to the biasing circuitry.

11. A fast isolation driver system for use in external defibrillators, the system comprising: a first input circuit for receiving first and second input signals; a first isolation transformer connected to the first input circuit wherein the first isolation transformer has first and second output terminals; a first biasing circuit connected to the first and second output terminals of the first isolation transformer; a first insulated gate bipolar transistor (IGBT) connected to the first biasing circuit; a second input circuit connected in parallel with the first input circuit, wherein the second input circuit receives the first and second input signals; a second isolation transformer connected to the second input circuit wherein the second isolation transformer has first and second output terminals; a second biasing circuit connected to the first and second output terminals of the second isolation transformer; a second insulated gate bipolar transistor (IGBT) connected to the second biasing circuit; and wherein the first and second IGBT are connected in series and wherein the first and second IGBTs switch between operational states in response to the first and second biasing circuits.

12. A high voltage circuit for use in an external defibrillator capable of handling higher voltages to implement a charge and discharge states in a plurality of high voltage capacitors , the circuit comprising: a power source; switching circuit connected to the power source; at least one automatic switch in electrical communication with the switching circuit; and the switching circuit including a charge and discharge circuit having operable electrical connection with the plurality of capacitors via the automatic switch.

13. A high voltage circuit including a capacitor bank comprised of a plurality of capacitor for use in an external defibrillator to store and discharge at least 2000 volts, the circuit comprising: a power source; a string of diodes; 6 a plurality of thyristors; and

7 switching means for charging the capacitor banks;

8 the string of diodes, the thyristors, the switching means and

9 the capacitor bank having operable electrical connection

10 therebetween and further having electrical connections to the

11 power source.