WO1997047040A1

WO1997047040A1 - I.c. device with concealed conductor lines

Info

Publication number: WO1997047040A1
Application number: PCT/EP1996/002342
Authority: WO
Inventors: Pierre Badehi
Original assignee: Shellcase Ltd.
Priority date: 1996-05-30
Filing date: 1996-05-30
Publication date: 1997-12-11
Also published as: AU6003696A

Abstract

This application discloses an integrated circuit device (10) comprising an integrated circuit die having top (16) and bottom (17) surfaces formed of electrically insulative and mechanically protective material and electrically insulative edge surfaces having exposed sections of conductive pads, the protective material being resistant to plastic dissolving solvents, and the integrated circuit die being readily damageable upon physical tampering with the integrated circuit device (10). A method for production of an integrated circuit device (10) which is resistant to techniques employed to remove integrated circuit packaging is also disclosed.

Description

I.C. DEVICE WITH CONCEALED CONDUCTOR LINES

The present invention relates to methods and apparatus for producing integrated circuit devices and to integrated circuit devices produced thereby.

An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.

At present three principal technologies are employed for packaging semiconductors: wire bonding, tape automatic bonding (TAB) and flip chip.

Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.

Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combina¬ tion and includes a pattern of copper traces suited thereto. The individual leads may be connected individu¬ ally or as a group to the various bond pads on the chip.

Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.

The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.

The flip-chip does not provide packaging but rather only interconnection. The interconnection encoun¬ ters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.

Published PCT application PCT/EP92/02134 of the present applicant/assignee, the disclosure of which is hereby incorporated by reference, describes a novel integrated circuit package which has significant advan¬ tages over the prior art described heremabove.

Various techniques have been proposed for preventing unauthorized extraction of information there¬ from. Scanning electron microscopes have been employed to following the logic within the die. Encryption techniques have been applied to all or part of firmware embodied in a chip. Physical and chemical techniques have been em¬ ployed to open integrated circuit packages and to dis¬ solve packages, for example using concentrated nitric acid.

The present invention seeks to provide appara¬ tus and techniques for production of integrated circuit devices which are resistant to physical and chemical techniques employed to remove integrated circuit packag¬ ing, and for production of integrated circuit devices in which unauthorized tampering causes damage to the inte¬ grated circuits thereof.

There is thus provided in accordance with a preferred embodiment of the present invention an inte¬ grated circuit device including an integrated circuit die having top and bottom surfaces formed of electrically insulative and mechanically protective material and electrically insulative edge surfaces having exposed sections of conductive pads, the protective material being resistant to plastic dissolving solvents, and the integrated circuit die being readily damageable upon physical tampering with the integrated circuit device.

In accordance with a preferred embodiment of the present invention, the integrated circuit device has a thickness of 0.5 mm or below.

Alternatively in accordance with a preferred embodiment of the present invention, at least one of the top and bottom surfaces is formed with at least one notch so as to render the integrated circuit device readily breakable.

Further in accordance with a preferred embodi¬ ment of the present invention, the at least one notch is filled with an elastomeric filler, such as silicone, thereby to prevent its being filled with a hard, suppor¬ tive material.

Additionally or alternatively, at least one of the top and bottom surfaces may be formed with at least one notch which is filled with a machining resistant material, such as adhesive filled with a powdered hard material, such as diamond, carborundum, silicon carbide or an appropriate ceramic material.

Further in accordance with a preferred embodi¬ ment of the present invention, an adhesive in contact with an active surface of a die may be filled with an abrasive material, which will damage the active surface if subjected to mechanical grinding.

Additionally in accordance with a preferred embodiment of the present invention, the adhesive may be filled with a material including a substance which reacts with nitric acid and releases agents which either attack or break the die. Further in accordance with a preferred embodi¬ ment of the present invention, at least one of the top and bottom surfaces includes an inclined surface, such that grinding of the integrated circuit device is sub¬ stantially prevented from being parallel to the active surface of the die.

Still further in accordance with a preferred embodiment of the present invention, at least one of the top and bottom surfaces includes at least two levels, such that grinding of the integrated circuit device creates a localized pressure on the die, thereby causing damage thereto, and grinding is substantially prevented from being parallel to an active surface of the die.

Additionally in accordance with a preferred embodiment of the present invention, the die includes a modified bonding pad which includes a plurality of rela¬ tively thin, generally parallel lines which are damage¬ able upon tampering with the integrated circuit device, and which substantially prevent contacting an electrical line of the die with probe technology, wire bonding or any other conductor line bonding technique.

Further in accordance with a preferred embodi¬ ment of the present invention, the integrated circuit device further includes a metal layer which masks the die, the metal layer having a plurality of randomly placed vias which expose internal conductor lines of the

There is also provided in accordance with a preferred embodiment of the present invention a method for production of integrated circuit devices which are resistant to techniques employed to remove integrated circuit packaging comprising providing an integrated circuit device including an integrated circuit die having top and bottom surfaces formed of electrically insulative and mechanically protective material and electrically insulative edge surfaces having exposed sections of conductive pads, the protective material being resistant to plastic dissolving agents, and the integrated circuit die being readily damageable upon physical tampering with the integrated circuit device.

In accordance with a preferred embodiment of the present invention, the method includes forming the integrated circuit device with a thickness of 0.5 mm or below.

Alternatively in accordance with a preferred embodiment of the present invention, the method includes forming at least one notch on at least one of the top and bottom surfaces so as to render the integrated circuit device readily breakable.

Further in accordance with a preferred embodi¬ ment of the present invention, the method further in¬ cludes filling the at least one notch with an elastomeric filler, such as silicone, thereby to prevent its being filled with a hard, supportive material.

Additionally or alternatively, the method includes forming at least one notch on at least one of the top and bottom surfaces and filling the at least one notch with a machining resistant material, such as adhe¬ sive filled with a powdered hard material, such as dia¬ mond, carborundum, silicon carbide or an appropriate ceramic material.

Further in accordance with a preferred embodi¬ ment of the present invention, the method further in¬ cludes providing an adhesive in contact with an active surface of a die, and filling the adhesive with an abra¬ sive material which will damage the active surface if subjected to mechanical grinding.

Still further in accordance with a preferred embodiment of the present invention, the method further includes filling the adhesive with a material including a substance which reacts with nitric acid and releases agents which either attack or break the die. Further in accordance with a preferred embodi¬ ment of the present invention, the method further in¬ cludes forming at least one of the top and bottom sur¬ faces with an inclined surface, such that grinding of the integrated circuit device is substantially prevented from being parallel to the active surface of the die.

Still further in accordance with a preferred embodiment of the present invention, the method further includes forming at least one of the top and bottom surfaces with at least two levels, such that grinding of the integrated circuit device creates a localized pres¬ sure on the die, thereby causing damage thereto, and grinding is substantially prevented from being parallel to an active surface of the die.

Additionally in accordance with a preferred embodiment of the present invention, the method further includes providing the die with a modified bonding pad which includes a plurality of relatively thin, generally parallel lines which are damageable upon tampering with the integrated circuit device, and which substantially prevent contacting an electrical line of the die with probe technology, wire bonding or any other conductor line bonding technique.

Further in accordance with a preferred embodi¬ ment of the present invention, the method further in¬ cludes providing the integrated circuit device with a metal layer which masks the die, the metal layer having a plurality of randomly placed vias which expose internal conductor lines of the die. The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:

Fig. 1 is a simplified pictorial illustration of an integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention; Fig. 2A is a simplified pictorial illustration of an integrated circuit device constructed and operative in accordance with another preferred embodiment of the present invention;

Fig. 2B is a simplified pictorial illustration of the integrated circuit device of Fig. 2A, having filled notches;

Fig. 3 is a simplified pictorial illustration of an integrated circuit device constructed and operative in accordance with yet another preferred embodiment of the present invention;

Fig. 4 is a simplified pictorial illustration of an integrated circuit device constructed and operative in accordance with still another preferred embodiment of the present invention;

Fig. 5 is an illustration of an integrated circuit device having an inclined surface in accordance with a preferred embodiment of the present invention;

Fig. 6 is an illustration of an integrated circuit device with a surface including at least two levels in accordance with a preferred embodiment of the present invention;

Figs. 7A and 7B are simplified illustrations respectively of prior art and novel pads constructed and operative in accordance with a preferred embodiment of the present invention; and

Fig. 8 is a partial, simplified illustration of an integrated circuit package having randomly located vias in accordance with a preferred embodiment of the present invention.

Reference is now made to Fig. 1, which illus¬ trates a preferred embodiment of integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention and in¬ cludes a relatively thin and compact, environmentally protected and mechanically strengthened integrated cir- cuit package 10 having a multiplicity of electrical contacts 12 plated along the edge surfaces 14 thereof. In accordance with a preferred embodiment of the invention, contacts 12 extend over edge surfaces onto a top planar surface 16 and optionally to a bottom planar surface 17 of the package. This contact arrangement permits both flat surface mounting and edge mounting of package 10 onto a circuit board. It is noted that the integrated circuit package 10 may include an integrally formed ground plane (not shown) as well as ground plane contacts 18.

In accordance with a preferred embodiment of the present invention, the integrated circuit package 10 may also include one or more thermal bonding pads 19 formed on one or both of the planar surfaces 16 and 17 thereof. The provision of such thermal bonding pads 19 is optional.

In accordance with a preferred embodiment of the present invention, the integrated circuit package 10 is manufactured from a material, such as glass, which is resistant to dissolving agents, such as nitric acid, which are capable of removing conventional plastic pro¬ tective layers or encapsulants.

In accordance with a preferred embodiment of the present invention, the integrated circuit package 10 has a thickness of 0.5 mm or below. The relatively thin package 10 is relatively fragile and difficult to handle mechanically, thereby enhancing resistance to physical techniques for removing integrated circuit packaging.

Reference is now made to Fig. 2A which is a simplified pictorial illustration of an integrated cir¬ cuit device 20 constructed and operative in accordance with another preferred embodiment of the present inven¬ tion. The integrated circuit device 20 is substantially identical to an integrated circuit device constructed and operative in accordance with published PCT application PCT/EP92/02134 of the present applicant/assignee, or in accordance with unpublished PCT application PCT/EP95/00097 of the present applicant/assignee, the disclosure of which is hereby incorporated by reference, with the exception that at least one of the top 16 and bottom 17 surfaces is formed with at least one notch 22 so as to render the integrated circuit device 20 readily breakable.

In accordance with a preferred embodiment of the present invention, as shown in Fig. 2B, the notches 22 may be filled with an elastomeπc filler 24, such as silicone, thereby to prevent their being filled with a hard, supportive material which could tend to diminish the fragility of the device 20 in an attempt to uncover the die therein.

Additionally or alternatively, as shown in Fig. 3, at least one of the top 16 and bottom 17 surfaces may be formed with at least one notch 26 which is filled with a machining resistant material 28, such as adhesive filled with a powdered hard material, such as diamond, carborundum, silicon carbide or an appropriate ceramic material. If the surface with the notches 26 is lapped or machined in an attempt to uncover the die, the lapping or machining of the machining resistant material 28 exerts a localized pressure on the die, thereby causing damage thereto.

Reference is now made to Fig. 4 which is a simplified partial illustration of an integrated circuit device 30 constructed and operative in accordance with another preferred embodiment of the present invention. The integrated circuit device 30 is substantially identi¬ cal to an integrated circuit device constructed and operative in accordance with published PCT application PCT/EP92/02134 of the present applicant/assignee, or in accordance with unpublished PCT application PCT/EP95/00097 of the present applicant/assignee, and as such, comprises a die 32 which has an active surface 34. An insulating cover plate 36 is attached to the active surface 34 with an adhesive 38, such as an epoxy. The underside of the die 32, as viewed in Fig. 4, may addi¬ tionally be bonded with an adhesive 39, which typically, although not necessarily, is identical with adhesive 38.

In accordance with a preferred embodiment of the present invention, the adhesives 38 and 39 may be filled with an abrasive material, such as a powdered ceramic, which will damage the active surface 34 if subjected to mechanical grinding.

Additionally in accordance with a preferred embodiment of the present invention, the adhesives 38 and 39 may be filled with a material including a substance which reacts with nitric acid and releases agents which either attack or break the die 32.

An example of such a substance is calcium fluoride which upon contact with nitric acid produces hydrofluoric acid which attacks the active surface 34 of the die 32.

Another example of such a substance is calcium chloride which upon contact with nitric acid produces aqua regia which attacks all metalized portions of the integrated circuit device 30, as well as damaging the die 32.

Yet another example of such a substance is any alkali metal hydroxide, such as lithium hydroxide, sodium hydroxide, or potassium hydroxide, which upon contact with nitric acid produces an exothermic reaction which damages the active surface 34 of the die 32.

Still another example of such a substance is an acetylacetonate, such as aluminum acetylacetonate, which upon contact with nitric acid releases acetone which in contact with the concentrated nitric acid locally burns violently, or may even cause a small explosion, thereby damaging the die 32. Reference is now made to Fig. 5 which is a simplified pictorial illustration of an integrated cir¬ cuit device 40 constructed and operative in accordance with another preferred embodiment of the present inven¬ tion. The integrated circuit device 40 is substantially identical to an integrated circuit device constructed and operative in accordance with published PCT application PCT/EP92/02134 of the present applicant/assignee, or in accordance with unpublished PCT application PCT/EP95/00097 of the present applicant/assignee, with the exception that at least one of the top 16 and bottom 17 surfaces includes an inclined surface 42, such that grinding of the integrated circuit device 40 is substan¬ tially prevented from being parallel to the active sur¬ face of the die. Thus attempted grinding may cause damage to the die.

Alternatively in accordance with another pre¬ ferred embodiment of the present invention, as shown in Fig. 6, at least one of the top 16 and bottom 17 surfaces includes at least two levels 44, such that grinding of the integrated circuit device 40 creates a localized pressure on the die, thereby causing damage thereto. This configuration also substantially prevents grinding from being parallel to the active surface of the die.

Reference is now made to Fig. 7A which illus¬ trates a bonding pad 50 of the prior art which is typi¬ cally used to electrically connect a die to input/output contacts of an integrated circuit device. The bonding pad 50 typically has a length of about 80 - 100 microns and a width of about 80 - 100 microns.

In accordance with a preferred embodiment of the present invention, as shown in Fig. 7B, an integrated circuit device (not shown) includes a modified bonding pad 52 for electrical connection with a die. The modified bonding pad 52 includes a plurality of relatively thin, generally parallel lines 54 which are damageable upon tampering with the integrated circuit device. The lines 54 are preferably about 25 microns wide and about 50 microns long.

Reliable electrical contact with the modified bonding pad 52 in the integrated circuit device itself may be difficult if most conventional integrated circuit device manufacturing techniques are employed. However, if the integrated circuit device is constructed in accord¬ ance with published PCT application PCT/EP92/02134 of the present applicant/assignee, or in accordance with unpub¬ lished PCT application PCT/EP95/00097 of the present applicant/assignee, the modified bonding pad 52 is con¬ tacted at edges thereof. Thus, reliable contact is achieved provided that the sum of cross sections 56 of the individual lines 54, shown in Fig. 7B, substantially equals the cross section of the original pad 50, the original cross section being designated by reference numeral 58 in Fig. 7A.

Reference is now made to Fig. 8 which illus¬ trates an integrated circuit device 60 which is con¬ structed in accordance with any conventional technique of the art for manufacturing microelectronic components, and as such, comprises a die 62 which has an active surface 64, and bonding pads 66. An insulating layer 68 is depos¬ ited onto the active surface 64 by chemical vapor deposi¬ tion or liquid spinning and further baking techniques, such as for polyimide, spin glass or sol gel.

In accordance with a preferred embodiment of the present invention, the integrated circuit device 60 further includes a metal layer 70 which masks the die 62. The metal layer 70 has a plurality of randomly placed vias 72 which expose internal conductor lines 74 of the die 62 underneath the mask layer 70 and the insulating layer 68.

If an attempt is made to etch or dissolve the mask layer 70, the etching solution passes through the vias 72, thereby damaging the conductor lines 74 of the die 62. Since the vias 72 are randomly placed, it is difficult to create a mask which would prevent the etch¬ ing solution from reaching the die 62 and causing damage thereto.

It will be apparent to persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims which follow:

Claims

C L A I M S

1. An integrated circuit device comprising an integrated circuit die having top and bottom surfaces formed of electrically insulative and mechanically pro¬ tective material and electrically insulative edge sur¬ faces having exposed sections of conductive pads, said protective material being resistant to plastic dissolving solvents, and said integrated circuit die being readily damageable upon physical tampering with said integrated circuit device.

2. Apparatus according to claim 1 and wherein said integrated circuit device has a thickness of 0.5 mm or below.

3. Apparatus according to claim 1 and wherein at least one of said top and bottom surfaces is formed with at least one notch so as to render said integrated cir¬ cuit device readily breakable.

4. Apparatus according to claim 1 and wherein said at least one notch is filled with an elastomeric filler, thereby to prevent its being filled with a hard, suppor¬ tive material.

5. Apparatus according to claim 1 and wherein at least one of said top and bottom surfaces is formed with at least one notch which is filled with a machining resistant material.

6. Apparatus according to claim 1 and further comprising an adhesive in contact with an active surface of a die, said adhesive being filled with an abrasive material which is operative to damage said active surface if subjected to mechanical grinding.

7. Apparatus according to claim 1 and wherein said adhesive is filled with a material comprising a substance which reacts with nitric acid and releases agents which either attack or break said die.

8. Apparatus according to claim 1 and wherein at least one of said top and bottom surfaces comprises an inclined surface, such that grinding of said integrated circuit device is substantially prevented from being parallel to said active surface of said die.

9. Apparatus according to claim 1 and wherein at least one of said top and bottom surfaces comprises at least two levels, such that grinding of said integrated circuit device creates a localized pressure on said die, thereby causing damage thereto, and grinding is substan¬ tially prevented from being parallel to an active surface of said die.

10. Apparatus according to claim 1 and wherein said die comprises a modified bonding pad which comprises a plurality of relatively thin, generally parallel lines which are damageable upon tampering with said integrated circuit device, and which substantially prevent contact¬ ing an electrical line of said die with probe technology, wire bonding or any other conductor line bonding tech¬ nique.

11. Apparatus according to claim 1 and further comprising a metal layer which masks said die, said metal layer having a plurality of randomly placed vias under which internal conductor lines of said die are exposed.

12. A method for production of an integrated circuit device which is resistant to techniques employed to remove integrated circuit packaging comprising provid¬ ing an integrated circuit die having top and bottom surfaces formed of electrically insulative and mechani¬ cally protective material and electrically insulative edge surfaces having exposed sections of conductive pads, said protective material being resistant to plastic dissolving solvents, and said integrated circuit die being readily damageable upon physical tampering with said integrated circuit device.

13. A method according to claim 12 and also com¬ prising forming said integrated circuit device with a thickness of 0.5 mm or below.

14. A method according to claim 12 and also com¬ prising providing at least one of said top and bottom surfaces with at least one notch so as to render said integrated circuit device readily breakable.

15. A method according to claim 12 and also com¬ prising filling said at least one notch with an elasto- meric filler, thereby to prevent its being filled with a hard, supportive material.

16. A method according to claim 12 and also com¬ prising forming at least one notch on at least one of said top and bottom surfaces and filling said at least one notch with a machining resistant material.

17. A method according to claim 12 and further comprising providing an adhesive in contact with an active surface of a die, said adhesive being filled with an abrasive material which is operative to damage said active surface if subjected to mechanical grinding.

18. A method according to claim 12 and further comprising filling said adhesive with a material compris¬ ing a substance which reacts with nitric acid and re¬ leases agents which either attack or break said die.

19. A method according to claim 12 and also com¬ prising forming at least one of said top and bottom surfaces with an inclined surface, such that grinding of said integrated circuit device is substantially prevented from being parallel to said active surface of said die.

20. A method according to claim 12 and also com¬ prising forming at least one of said top and bottom surfaces with at least two levels, such that grinding of said integrated circuit device creates a localized pres¬ sure on said die, thereby causing damage thereto and whereby grinding is substantially prevented from being parallel to an active surface of said die.

21. A method according to claim 12 and further comprising providing said die with a bonding pad which comprises a plurality of relatively thin, generally parallel lines which are damageable upon tampering with said integrated circuit device, and which substantially prevent contacting an electrical line of said die with probe technology, wire bonding or any other conductor line bonding technique.

22. A method according to claim 12 and further comprising providing a metal layer which masks said die, said metal layer having a plurality of randomly placed vias under which internal conductor lines of said die are exposed.