WO1997023071A1 - Error correcting timing reference distribution - Google Patents
Error correcting timing reference distribution Download PDFInfo
- Publication number
- WO1997023071A1 WO1997023071A1 PCT/US1996/019653 US9619653W WO9723071A1 WO 1997023071 A1 WO1997023071 A1 WO 1997023071A1 US 9619653 W US9619653 W US 9619653W WO 9723071 A1 WO9723071 A1 WO 9723071A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- symbols
- reference signal
- signal
- timing
- phase
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
Definitions
- the present invention relates generally to global time reference signals for use in telecommunications systems and more specifically for airframe synchronization.
- Synchronization is an important part of many telecommunications systems.
- a communications system needs to distribute accurate frequency and time reference signals.
- TDMA time division multiple access
- a base station transmits bursts of data known as airframes (or simply frames), to mobile units traveling in an area serviced by the base station.
- ADC American Digital Cellular
- a frame is defined as a digital packet containing six time slots transmitted at a 25 Hertz frame rate.
- This exemplary frame format, illustrated as FIG. 1 is used in the D-AMPS system specified in EIA/TIA IS-54B.
- GSM Global System for Mobile Communication
- GSM Global System for Mobile Communication
- An original base station BSl is handling a connection between mobile station MS and the network as represented by the transmission link TL1 between base station BSl and the mobile switching center MSC.
- the mobile station then moves to a position MS' wherein it is determined that this connection is best handled by base station BS2, e.g. , to improve the signal quality of the connection.
- the system initiates a handoff procedure by sending appropriate commands to base stations BSl and BS2 over transmission links TL1 and TL2.
- the mobile station MS may or may not be informed of the impending handoff.
- transmissions will begin from the base station BS2 and terminate from base station BSl.
- a mobile station may be desirable to allow transmission to continue from both base stations for some time period.
- the mobile station cleanly receive a last frame from original base station BSl followed by a first frame from base station BS2.
- a highly accurate and quickly discernible reference signal must be provided such that the base stations are time synchronized within, for example, 2 microseconds to ensure that the frame decoder in the mobile will not be disturbed by lost, or duplicated data.
- a second application for the synchronization of airframes in a telecommunications system occurs when a single base station contains multiple transceivers that are each transmitting the same, or substantially the same, information to a mobile unit.
- the transceivers can be separated within the same base station or base station site, or transceivers from neighboring sites can cooperate for a call handled by a common switching center, wherein the neighboring sites are globally synchronized.
- Each transceiver can transmit at slightly different frequencies in order to avoid interference.
- the base station transmits the airframes to a mobile unit, the mobile unit receives each of the signals and combines them such that the signals appear much stronger. This is often referred to as simulcasting.
- One way to achieve a working simulcasting is to synchronize the airframe timing of two transceivers and then have the transceivers transmit airframes with a known offset relative to each other.
- the transmission of signals must be synchronized by the base stations.
- synchronization between transmitters should be determined within, for example, ten microseconds.
- airframe data clocks and synchronization signals are phase locked using a reference distribution signal.
- a phase-locked loop can be used to lock to a reference frequency.
- a typical analog PLL may include a phase comparator, a low-pass filter and a voltage controlled oscillator (VCO).
- VCO voltage controlled oscillator
- the output of the VCO is fed back as one of the inputs to the phase comparator and, typically, a low frequency reference signal consisting of individual synchronization pulses is fed into another input of the phase comparator.
- VCO voltage controlled oscillator
- Another object is to enable the transceiver to obtain a phase-locked state with respect to the reference signal significantly faster than is presently possible with conventional systems and that will maintain a lock even if spurious errors or interference are introduced in the reference signal. It is a further object to make fault identification of the distributed reference signal easier, so that the reference receiver will obtain accurate alarms concerning cable shorts, cable open circuit, and spurious signalling. In addition, it is an object of the invention to provide a reference signal distribution while minimizing manufacturing costs of the communications system.
- a reference signal that includes an encoded digital symbol pulse train having a rate much higher than the actual frequency or occurrence rate of a reference event represented (For example a frame time zero that occurs once every 40ms frame for a 25Hz signal).
- a first group or sequence of symbols is used to identify a low frequency signal event or reference event.
- a second group or sequence of symbols is used to indicate continuous phase information.
- the symbols used to identify the reference event are made significantly different from the phase information, making identification of the reference event easier.
- By encoding a known sequence of symbols to represent the phase information in the reference signal an increased amount of frequency information can be propagated as compared with a conventional single pulse. This also facilitates the detection and correction of signalling errors as the errors will break the expected symbol sequence. The system can then identify and correct, or choose to ignore, the errors based on the effect the errors will have on system performance.
- FIG. 1 illustrates a frame with time slots
- FIG. 2 shows an example of base station communication with a mobile
- FIG. 3 A illustrates phase relations of the timing reference signal
- FIG. 3B shows the timing reference signal in relation to an indicated frame time zero
- FIG. 4 is a block diagram of a digital phase locked loop
- FIG. 5 is a block diagram of an exemplary symbol correlation detector
- FIG. 6 depicts sampling and bit error correction according to an exemplary embodiment of the present invention
- FIG. 7 is a block diagram illustrating an exemplary embodiment of a symbol detection unit
- FIG. 8 is a block diagram of transceiver cabinets to which reference signals according to the present invention can be distributed.
- Reference signal distribution is a source of continuous errors that are difficult to detect and locate. Errors can also lead to severe degradation of system performance.
- the technique and medium used to distribute a reference signal e.g. , as microwave, radio, or cable, introduce spurious pulses or errors in the signal which, if undetected, can slow or inhibit system operation.
- PLL phase locked loop
- the error in the reference signal is added to the feedback loop, causing the system to take much longer to acquire a locked frequency.
- the PLL could be forced outside the maximum specified error from the ideal reference frequency for the system.
- the problem with conventional reference signals is that it is extremely difficult to determine if errors or unwanted interference have been added to the reference signal. It is equally difficult to remove any errors that have been introduced in the reference signal.
- a time domain discrete reference signal is distributed and encoded with information to enable the system to determine if the reference signal has enough accuracy.
- the reference signal includes predetermined groups or sequences of symbols. By monitoring the reference signal the system can determine if each received sequence of symbols is correct for the actual frequency measurement. If the sequence is not correct, the system can then determine if the signal should be disregarded. The system can thus exclude a very small part of the reference signal that contains an error. Therefore, a much higher level of disturbance or noise is needed to break a lock condition.
- the symbols are chosen so that, for example, spikes, cable breakage, hum, click, and static will not appear as a good signal.
- the system is then able to pick system errors out of the reference system errors and make corrections on single samples to make the reference signal immune to small spikes and jitter that equals out on a single symbol or in an alternative embodiment simply ignore the error. For example, errors smaller than plus or minus 1.5 master clock (MCK) intervals will be filtered by sampling and symbol detection units (shown in detail below) under the condition that the error will be equaled by an error of the same amount in the other direction at the next transition on the reference signal.
- MCK master clock
- the rate of symbol transmission is also important to the ability to disregard spurious errors.
- a symbol error with a period of 1/1000 of a measurement interval will render in the reference signal an error of one per mille or 1/1000. Therefore, the smaller the symbol period, the higher the symbol transmission rate and correspondingly the greater the ability to disregard errors.
- a conventional PLL system with one pulse per reference event will respond to a single spike as anything between zero error up to the whole pulse interval. When using such a conventional reference signal only a single spike per (theoretically) eleven hours is tolerated; however, when implemented with a PLL including a lowpass filter present in the feedback chain, about a single spike per hour can be tolerated.
- the initial time needed to produce a locked condition will be much smaller than with a conventional reference signal.
- Another advantage of using a known sequence of symbols is the ability to count errors and determine the reliability of the reference signal. For the same reasons the system can also recognize errors much more quickly and disregard or hold the signal locked within the required specification by keeping errors from being fed back into the PLL. As a result, fewer demands are placed on the circuitry.
- phase information is sent with the reference signal than is actually needed to indicate a reference event.
- the phase information In order to diversify the information, the phase information must behave in a way that is sufficiently different from the reference event such that the reference event is easily identified.
- the information is comprised of symbols each having a unique bit pattern. There are basically two kinds of symbols, "phase” symbols and “sync" symbols.
- the sync symbols carry both the reference event and phase information.
- the phase symbols only carry phase information. Symbols are indicated by a continuous flow of a unique high frequency pattern.
- the symbol pattern is one million times more unique than the singular pulse used in a conventional system. This will satisfy one parts per million (PPM) of information consistency simplifying the detection of any error condition and if an error condition can be corrected.
- PPM parts per million
- the AFS signal is a composite signal comprising two binary signals, AFSl 10 and AFS2 11.
- the AFS signal can be generated out of a 4860 kHz clock signal, CLK 12. Therefore, for a 25 Hz reference pulse, with every 48,600th tick of CLK, a violation sequence 14 is indicated.
- the violation sequence is a sequence of sync symbols recurring in the stream of symbols at the time of the reference event. According to one preferred embodiment of the invention the violation sequence occurs at a 25 Hertz rate.
- the violation sequence lasts for two cycles of the CLK 12, starting at the negative CLK transition. After completion of the violation sequence, the normal sequence composed of phase symbols 15 is resumed and will continue until the next violation sequence, completing a 25 Hertz cycle.
- FIG. 3 A illustrates that the order of the toggle between AFSl 10 and AFS2 11 is reversed during the violation sequence.
- AFSl 10 would normally remain low and AFS2 11 would toggle low.
- AFS2 11 is held high and AFSl 10 toggles high.
- AFS2 11 will toggle when AFSl 10 normally would have toggled, and vice versa.
- the AFS signal will propagate an airframe time reference (airframe timing) with high tolerance to disturbances and connection errors for several reasons.
- the frequency of symbols is very high. This makes singular errors very insignificant.
- Frame time zero, FTZ 16 is indicated by the violation sequence as shown in FIG. 3 A.
- the Detected AFS and FTZ can be determined in many ways. According to a preferred embodiment, FTZ and the Detected AFS are determined when all of the sync symbols have been received with no errors and in the right sequence. If any of the sync symbols are faulty, the whole 40 ms interval is disregarded. Using this embodiment it has been discovered that phase information is not necessary for the determination. It is enough to just count the phase information errors in order to determine the signal jitter, and other errors. It will be appreciated by one skilled in the art that the signals in FIG.
- AFSl and AFS2 are included only for illustrative purposes of determining a reference event and are not part of the AFS distribution concept per se.
- Other signaling schemes for creation of a reference signal would suggest themselves to one skilled in the art without departing from the scope and spirit of the invention.
- the airframe timing reference signal, AFS can be a 1215 kHz, 50/50% duty-cycle 90° two phase square-wave signal carried by the signals AFSl and AFS2.
- the 25 Hz interval airframe timing is encoded into the AFS signal by means of a phase violation as defmed above.
- the coding scheme used is similar to a two-phase Miller variant or delay modulation encoding. Of course other coding schemes may be used in -9- accordance with the present invention.
- jitter on the AFS signal must not exceed ⁇ 25 nanoseconds at the receiver end.
- the maximum allowed frequency error on the AFS signal is 1 PPM measured over an integration time of 25 milliseconds, or longer.
- a path delay introduced by distributing the AFS signal from the timing master and to any airframe time reference recipient is allowed to be between 0 - 450 nanoseconds.
- a Master Clock of 19.44 MHz is used.
- AFS as a train of symbols, see, e.g., FIGS. 3A and 3B. Each symbol represents a specific time in the airframe.
- the time reference signal is diversified into AFSl and AFS2.
- Each of the two signals carries a part of the composite AFS signal.
- the two signals, AFSl and AFS2 will be commonly referred to as AFS, and where they differ, this will be noted.
- the airframe timing signals 52 In order to generate the airframe timing signals 52, see, e.g., FRAMESYNC, SAMPLERATE, FRAME_TX, and FRAME_RX in FIG. 4, they may be synchronized to a timing reference signal.
- the receiving unit see, e.g. , FIG. 8
- the receiving unit identifies and correlates the phase information and the reference event information or SYNC information. According to another aspect of the present invention this can be accomplished through the use of a symbol correlation detector (SCD).
- SCD symbol correlation detector
- the SCD detects airframe timing on the AFS signal by measuring the time between the current transition on the incoming reference and the last transition on AFSl and AFS2, respectively. It also measures the current signal level and detects transitions on the AFSl and AFS2.
- FIG. 5 is an example of an SCD 30 according to an exemplary embodiment of the invention.
- the AFS signal 20 and master clock (MCK) 25 are fed into a sampling and bit error correction unit 34. After the AFS signal is sampled and corrected, it is output as a detected AFS
- DET_AFS (DET_AFS) signal 37.
- the DET_AFS 37 is then input into a symbol detection unit 36 to identify the symbols in the AFS signal to determine the encoded reference event information and phase information which is outputted as signals AFS_TRANS 39 and SYMBOL ID 33. These signals are then input into the Frametime Detection Unit 38 along with the detected AFS signal 37 in order to identify any symbol error, overrun, and the detected frame time 31, 32 and 35, respectively.
- sampling and bit error correction unit 34 is depicted.
- the AFS signal is input into a low pass filter 41 and then transmitted to a Schmitt trigger 42.
- the signal is then sampled in a series of D-type latches 43. Single bit errors are then corrected using a two out of three majority gate 44.
- the sampled and corrected signal, DET_AFS 37 is then distributed to the symbol detector. It should be noted that this function is doubled, one for AFSl and one for AFS2.
- FIG. 7 shows an example of a symbol detection unit 36 according to an embodiment of the invention.
- the symbol detection unit 36 detects transitions on the detected AFS signal 37. Time between the transitions is measured with a 5-bit counter 55 that counts from three after it is reset by the AFS TRANS asserted condition 39.
- the detected AFS signal 37 is "mid bit sampled" as the AFS signal is nonstationary to the sampling MCK signal. Since the count by the counter 55 is truncated, and counts the duration of a level sampled at mid bit, the counter should start at three to compensate for the truncated bit. The counter counts up to 16 and then holds until reset again.
- the detected SYMBOL ID 33 equals the binary output of the counter 55 divided by 4.
- OverRun error is detected every master clock interval that the situation remains. OverRun error is flagged when there are no transition on one of the two or both of the signals AFSl and AFS2 for a timeout period.
- the timeout is sampled with an up/down counter (not shown) that counts overruns per MCK interval. The counter will count down to zero and stay there if there are no overruns.
- the counter will count for each overrun up to 8191.
- An overrun error can occur when connection is broken, e.g. , cable breakage, when no signal is detected.
- An overrun error is flagged when this counter is greater than or equal to 4096.
- the OverRun error thus is filtered for glitches and reported as a SymOverRun when it averages more than 50% over an integration time of 211 microseconds.
- SYNC(O) frame time zero (FTZ) is detected. Continuous indication of momentary phase is given by the phase (n) symbols.
- the detector keeps track of the sequence by validating the detected condition according to the previous condition.
- Table II indicates an example of a series of valid condition sequences. Note this table is exemplary and other encoding schemes could be used without departing from the scope and spirit of the invention.
- Phase (1) Phase (2)
- Phase (3) Phase (3)
- a detected condition that is out of sequence is considered as a symbol error. For instance, if the previous symbol was Phase(l) the expected current symbol should be Phase(2). If not then an error is detected. When any error condition occurs, the detected frame timing is not considered valid and a symbol error is reported at every transition on either DET AFS1 or DET AFS2. Conditions of symbol error, and implicitly overrun errors, too, will not affect the generated frame timing. Therefore, the detected frame timing can be updated frequently. The system can also count the number of errors to determine if the signal has become unlocked. The system can then decide if it should adjust the loop back time in the phase locked loop or if the system can go temporarily unsynced if the error is spurious.
- Timing reference signal One application of the timing reference signal is to provide airframe synchronization between base stations and between local transceivers at the same base station as illustrated in FIG. 8. According to this embodiment a time reference signal
- EXT_AFS 72 is generated by a timing master TIM (not shown).
- the EXT AFS is then distributed between the transceiver cabinets 70.
- the EXT_AFS is then distributed internally to each transceiver 80 as signal AFS 82.
- Each transceiver 80 then locks its airframe timing to this time reference signal. The synchronization can be accomplished through use of a Frequency
- FGC Generator and Correlator
- Each transceiver 80 is provided with an FGC.
- FGC timing reference signal
- the FGC In order to synchronize the transmissions of the airframes from each of the base stations and from multiple transceivers within a base station, a timing reference signal (AFS) 20 is provided.
- the FGC generate airframe timing signals using the MCK 25.
- the FGC adds or removes a small time quantum at regular intervals to the airframe timing signals 52.
- the FGC In an ideal situation of no time skew between the generated timing and the AFS reference signal, the FGC generates its output signals directly out of the MCK. When a time skew between the generated timing and the reference AFS signal is present, the FGC will adjust timing by adding or removing a quantum of time to or from the generated airframe timing signals. This time quantum is determined by the
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU12851/97A AU716935B2 (en) | 1995-12-15 | 1996-12-13 | Error correcting timing reference distribution |
KR1019980704506A KR20000064413A (en) | 1995-12-15 | 1996-12-13 | Timing Reference Signal Distribution System and Method for Error Correction |
BR9612019A BR9612019A (en) | 1995-12-15 | 1996-12-13 | System and process for distributing a timing reference signal in a telecommunications system and a discrete timing reference signal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US872995P | 1995-12-15 | 1995-12-15 | |
US60/008,729 | 1995-12-15 |
Publications (1)
Publication Number | Publication Date |
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WO1997023071A1 true WO1997023071A1 (en) | 1997-06-26 |
Family
ID=21733324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US1996/019653 WO1997023071A1 (en) | 1995-12-15 | 1996-12-13 | Error correcting timing reference distribution |
Country Status (5)
Country | Link |
---|---|
KR (1) | KR20000064413A (en) |
AU (1) | AU716935B2 (en) |
BR (1) | BR9612019A (en) |
CA (1) | CA2240633A1 (en) |
WO (1) | WO1997023071A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999039532A1 (en) * | 1998-02-02 | 1999-08-05 | Ericsson, Inc. | Coverage area sectorization in time division multiple access/frequency-time division duplex communications systems |
US6587444B1 (en) | 1997-11-14 | 2003-07-01 | Ericsson Inc. | Fixed frequency-time division duplex in radio communications systems |
US6778603B1 (en) | 2000-11-08 | 2004-08-17 | Time Domain Corporation | Method and apparatus for generating a pulse train with specifiable spectral response characteristics |
US6959031B2 (en) | 2000-07-06 | 2005-10-25 | Time Domain Corporation | Method and system for fast acquisition of pulsed signals |
EP2051422A1 (en) | 2007-10-16 | 2009-04-22 | Emma Mixed Signal C.V. | Digital data encoding and decoding method and system |
EP2211581A1 (en) * | 2009-01-27 | 2010-07-28 | Alcatel Lucent | Local network timing reference signal |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10108110A1 (en) * | 2001-02-21 | 2002-08-29 | Philips Corp Intellectual Pty | Receiver and method for initially synchronizing a receiver to the carrier frequency of a desired channel |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US4218770A (en) * | 1978-09-08 | 1980-08-19 | Bell Telephone Laboratories, Incorporated | Delay modulation data transmission system |
US4683567A (en) * | 1985-07-30 | 1987-07-28 | British Columbia Telephone Company | Asynchronous signaling system for digital communication channel |
EP0553610A1 (en) * | 1992-01-29 | 1993-08-04 | Siemens Aktiengesellschaft | Synchronisation method for circuits elements in a telecommunication exchange |
EP0671825A1 (en) * | 1994-03-09 | 1995-09-13 | Alcatel SEL Aktiengesellschaft | Method for framesynchronisation |
-
1996
- 1996-12-13 CA CA002240633A patent/CA2240633A1/en not_active Abandoned
- 1996-12-13 BR BR9612019A patent/BR9612019A/en unknown
- 1996-12-13 WO PCT/US1996/019653 patent/WO1997023071A1/en not_active Application Discontinuation
- 1996-12-13 AU AU12851/97A patent/AU716935B2/en not_active Ceased
- 1996-12-13 KR KR1019980704506A patent/KR20000064413A/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4218770A (en) * | 1978-09-08 | 1980-08-19 | Bell Telephone Laboratories, Incorporated | Delay modulation data transmission system |
US4683567A (en) * | 1985-07-30 | 1987-07-28 | British Columbia Telephone Company | Asynchronous signaling system for digital communication channel |
EP0553610A1 (en) * | 1992-01-29 | 1993-08-04 | Siemens Aktiengesellschaft | Synchronisation method for circuits elements in a telecommunication exchange |
EP0671825A1 (en) * | 1994-03-09 | 1995-09-13 | Alcatel SEL Aktiengesellschaft | Method for framesynchronisation |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6587444B1 (en) | 1997-11-14 | 2003-07-01 | Ericsson Inc. | Fixed frequency-time division duplex in radio communications systems |
WO1999039532A1 (en) * | 1998-02-02 | 1999-08-05 | Ericsson, Inc. | Coverage area sectorization in time division multiple access/frequency-time division duplex communications systems |
US6556830B1 (en) | 1998-02-02 | 2003-04-29 | Ericsson Inc. | Coverage area sectorization in time division multiple access/frequency-time division duplex communications systems |
US6959031B2 (en) | 2000-07-06 | 2005-10-25 | Time Domain Corporation | Method and system for fast acquisition of pulsed signals |
US6778603B1 (en) | 2000-11-08 | 2004-08-17 | Time Domain Corporation | Method and apparatus for generating a pulse train with specifiable spectral response characteristics |
EP2051422A1 (en) | 2007-10-16 | 2009-04-22 | Emma Mixed Signal C.V. | Digital data encoding and decoding method and system |
US8144802B2 (en) | 2007-10-16 | 2012-03-27 | Semiconductor Components Industries, Llc | Digital data encoding and decoding method and system |
EP2211581A1 (en) * | 2009-01-27 | 2010-07-28 | Alcatel Lucent | Local network timing reference signal |
Also Published As
Publication number | Publication date |
---|---|
AU716935B2 (en) | 2000-03-09 |
BR9612019A (en) | 1999-06-29 |
KR20000064413A (en) | 2000-11-06 |
AU1285197A (en) | 1997-07-14 |
CA2240633A1 (en) | 1997-06-26 |
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