WO1997020316A2 - Automated process for generating boards from defective chips - Google Patents

Abstract

An automated apparatus for generating a plurality of memory systems from a population of memory elements (90) including non-perfect memory elements each including at least one defective memory cell, the apparatus comprising: a region tester (80) operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element; a memory element grouper (100) operative to group the population of memory elements into a plurality of sets based on the regional testing results; and a controlling program generator (140) operative to automatically generate a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.

Description

AUTOMATED PROCESS FOR GENERATING BOARDS FROM DEFECTIVE CHIPS

This application is based on application no. 116220 filed in the Israel Patent OfBce on November 30, 1995, the content of which is incorporated herein by reference.

Background Of The Invention

Faults are known to occur in the manufacture of memory elements the most common of which today are DRAMs (dynamic random access memories). Typically, the DRAMs produced include a certain percentage of perfect DRAMs, and a certain percentage of "mostly good" DRAMs, for example ARAMs (audio RAMs, typically including only thousands of defective cells in a 4 megabit DRAM chip), and a certain percentage of rejected DRAMs which are discarded or downsized to remove defective portions. ARAMs are used in audio applications, since the audio data is not sensitive to a small number of faults. There also exists a portion of the wafer used in the manufacture of the DRAM which, due to an abundance of defective cells, is not even packaged as DRAM chips.

The following art describes use of "mostly good" memories in non- audio applications: U.S. 4,376,300 to Tsang and PCT Published Application WO92/20068 (PCT/US91/03183) to Sophos Technologic. U.S. Patent 4,376,300 to Tsang describes a memory system which employs a plurality of mostly good memory chips. A redundant memory chip is used to store the data to designated defective locations in the mostly good memories. In one embodiment a FROM is programmed to recognize the addresses of defective elements and cause the redundant memory to be selected. PCT Published Application WO92/20068 (PCT/US91/03183) to

Sophos Technologic states that the system described in U.S. Patent 4,376,300 to Tsang is slow in that the access time of the memory system is generally longer than that of a conventional memory system. Obviously this presents significant limitations on the system with respect to timing considerations vis-a-vis the host system.. PCT Published Application W092/20068 suggests that the programmable memory is connected to the processor memory bus for storing the addresses of the defects in the mostly good memories. U.S. Patent 5,278,793 to Yeh describes a memory defect masking device to be used in combination with defective memory devices such as SIMMs. The memory masking device first stores the addresses of the defective memory spaces of the defective memory devices therein and then compares the memory addresses present at the addresses lines of the defective memory devices with the address stored therein The defective memory devices are disabled when the memory address present at the address lines tallies with one of the addresses stored in the memory defect masking device. The memory defect masking device is also connected to the data lines of the defective memory devices to permit the former to act as a replacement for the defective space of the defective memory devices. The defective memory devices are therefore operated as if they have no defective memory space The utilization of this technique will result in non-standard memory systems which would require special modifications to any standard host system

Operations research methods applicable to working with memory systems having faults are discussed in the following references' A. Kandel, Fuzzy techniques in pattern recognition, John Wiley & Sons, 1982, chapter 5, J. Hertz, A. Krogh, and R. G. Palmer, Introduction to the theory of neural computation, Addison- Wesley, 1991, chapters 4, 9, and 10, B Kosko, Neural networks and fuzzy systems, Prentice Hall, 1992, chapter 10, and M Taha, Operations research, Macmillan Publishing, 1982, Chapter 8.

Conventional methods for inspecting chips are described in B Dekker, F. Beenker and L. Thijssen, "A realistic fault model and test algorithm for static random access memories", IEEE Transactions, CAD, Vol. 9(6), pp. 567-572, June 1990, "Testing semiconductor memories. Theory and Practice" by A. J. Van de Goor, John Wiley & Sons Ltd., 1991, and in the "Records of the 1993 IEEE International Workshop on Memory Testing", San Jose California, edited by R. Rajsuman, IEEE Computer Society Press.

Identifying defective chips is also discussed in S. Kim and W. Wijaranakula, "The Effect of the Crystal Growth in Defects on the Pause Tail Characteristics of Megabit Dynamic Random Access Memory Devices", Journal of the Electrochemical Society, Volume 141, Number 7, July 1994

A typical bus used to access chips is described in the ISA Bus Specification and Application Notes, Intel Corporation, 1990 The disclosures of all of the above publications and of publications cited thereby, and the disclosures of all publications referred to in the specification and of all publications cited by any of these publications, are hereby incorporated herein by reference. Summary Of The Invention

The present invention seeks to provide an improved method and apparatus for utilizing defective memory elements such as an automated process for generating boards from defective chips.

The disclosure of Applicant's co-pending PCT Patent Application (PCT/US96/03443) is hereby incorporated by reference.

There is thus provided, in accordance with a preferred embodiment of the present invention, apparatus for generating a plurality of memory systems from a population of memory elements including non-perfect memory elements each including at least one defective memory cell, the apparatus including a region tester operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element, a memory element grouper operative to group the population of memory elements into a plurality of sets based on the regional testing results, and a controlling program generator operative to automatically generate a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.

Further in accordance with a preferred embodiment of the present invention, the apparatus also includes robotic apparatus operative to generate a memory system using the memory elements in an individual one of the plurality of sets and the controller.

Still further in accordance with a preferred embodiment of the present invention, at least one of the memory systems includes an ISP controller and the controlling program generator is operative to automatically generate a controlling program for the ISP controller. Further in accordance with a preferred embodiment of the present invention, the controlling program generator generates a controlling program for a particular memory system from among the plurality of memory systems according to the regional testing results of all non-perfect memory elements in the particular memory system. Also provided, in accordance with another preferred embodiment of the present invention, is an automated method for generating a plurality of memory systems from a population of memory elements including non-perfect memory elements each including at least one defective memory cell, the method including testing regions within each non-perfect memory element for defective cells and generating a regional testing result for each non-perfect memory element, grouping the population of memory elements into a plurality of sets based on the regional testing results, and automatically generating a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.

Further provided, in accordance with another preferred embodiment of the present invention, is apparatus for generating a plurality of memory systems from a population of memory elements including non-perfect memory elements each including at least one defective memory cell, each of the plurality of memory systems including at least one memory system component, the apparatus including a region tester operative to test regions within each non-perfect memory clement for defective cells and to generate a regional testing result for each non-perfect memory element, and a memory element grouper operative to group the population of memory elements into sets based on the regional testing results, at least one constraint on each of the plurality of memory systems, and at least one constraint on each of the memory system components. Brief Description Of The Drawings

The present invention will be better understood and appreciated from the following detailed description, taken in conjunction with the drawings in which: Fig. 1 is a simplified flowchart illustration of a preferred method for generating memory systems from defective memory elements, which method is operative in accordance with a preferred embodiment of the present invention;

Fig. 2 is a simplified block diagram of automated apparatus for performing steps 30 - 70 of the method of Fig. 1, Fig. 3 is a schematic illustration of a testing board constructed and operative in accordance with a preferred embodiment of the present invention; Figs. 4 A and 4B (taken together) are a schematic illustration of a 72 -pin programmable memory mapping board constructed and operative in accordance with a preferred embodiment of the present invention; and

Figs. 5A and 5B are top and bottom views, respectively, of a PCB (printed circuit board) on which defective memory elements are mounted, which is constructed and operative in accordance with a preferred embodiment of the present invention.

Attached herewith are the following appendices which aid in the understanding and appreciation of one preferred embodiment of the invention described herein:

Appendix A is a listing of a preferred software implementation of a memory element grouper constructed in accordance with a preferred embodiment of the present invention and operative on a PC compatible computer; and

Appendix B is a listing of a preferred software implementation of a controller program generator constructed in accordance with a preferred embodiment of the present invention and operative on a PC compatible computer. Detailed Description Of Preferred Embodiments

A portion of this patent disclosure contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of this patent disclosure as it appears in the file or records of the Patent Office, but otherwise reserves all rights.

Reference is now made to Fig. 1 which is a simplified flowchart illustration of a preferred method for generating memory systems from defective memory elements, which method is operative in accordance with a preferred embodiment of the present invention.

The method of Fig. 1 includes the following processes:

Process 10: The defective cell distribution of memory elements originating from the same production line tend to be correlated. Therefore, definition of good and bad regions, as explained in the description of process 20, may typically be obtained by analyzing the distribution of the defective cells in only a sample of memory elements from a production line. A plurality of memory elements, such as chips, are inspected, to map the defective cells therein. Conventional methods may be employed to inspect each chip, such as the 13N test algorithm from B. Dekker, F. Beenker and L Thijssen, "A realistic fault model and test algorithm for static random access memories", IEEE Transactions, CAD, Vol 9(6), pp 567-572, June 1990, used m our example

Alternatively, other conventional methods may be employed to inspect each chip, as descπbed in "Testing semiconductor memoπes Theory and Practice" by A J Van de Goor, John Wiley & Sons Ltd , 1991, and in the "Records of the 1993 IEEE International Workshop on Memory Testing", San Jose California, edited by R Rajsuman, IEEE Computer Society Press

All of these methods identify the defective cells only after repeated cycles of testing As is known, this identification process can be done more quickly for DRAM chips by modifying the chips' data preservation system For example, it is based on the fact that "the refresh time failure of the memory devices could be attπbuted to several types of crystal defects ", S Kim and W Wijaranakula, "The Effect of the Crystal Growth in Defects on the Pause Tail Characteristics of Megabit Dynamic Random Access Memory Devices", Journal of the Electrochemical Society, Volume 141, Number 7, July 1994

As a further example, delaying the refresh time allows the test system to identify the defective cells in fewer cycles It is appreciated that testing must typically also be done with the regular refresh cycle since there are sometimes defects that can be identified only with regular refresh

The output of the inspection process is a file containing a map of the memory address of each defective cell in the memory elements sampled

Process 20 Typically, unless there are very few defective cells, the file generated in process 10 is too large to be cost-effective relative to a situation where only non-defective memory elements are used Also, identifying defective cells using the said file would take an unacceptably long time

Therefore, the memory is subdivided, typically partitioned, mto regions which are then categorized into at least two categoπes such as good regions or bad regions, such that the following cπteπa are met, as much as possible a The total area of the good regions is as large as possible, and b As little information as possible is required in order to control access to the good regions and to prevent access to the bad regions The relative importance of the two criteria depends on the application which determines the "price" of storage and timing. For example, in voice modules, timing is not important because sampling of voice is typically relatively slow, such as 8 KHz and the more important consideration is that space should be conserved. Conversely, in SIMM modules, the access time is short, such as 70 nanoseconds, whereas extra space is available because the presence of even a small amount of defective cells typically requires that an additional, or redundant, chip be provided. Therefore, space considerations are less important so long as the sum of the sizes of all of the bad regions account for no more than the size of the good regions on the redundant chip.

For example, in a standard 4 megabyte / 32 megabit SIMM module the bad regions may account for up to about 10% on each memory element because the 10% bad regions of the 32 megabits may be stored on the redundant memory element which requires at most 3.2 megabits of good memory. The definition of good and bad regions are application specific. For example, in applications of solid state drives and SIMM modules, any region containing even one defective cell is considered bad. Conversely, in voice modules a region is defined as good even if a limited number of defective cells are present within that region and if these defective cells are somewhat spread within the region, i.e., not clustered. More than two categories of region may also be used in certain applications to improve the performance of the application.

Process 30' With the definition of good and bad regions established for this collection of memory elements and specific system application, mapping of defective regions for the full set of memory elements may be accomplished. Identifying bad regions for each memory element is typically faster than identifying all defective cells of a memory element because.

1) once more than a predetermined acceptable number of defective cells in a region are identified, the region may be defined as bad without further testing;

2) region testing typically requires less permanent memory storage since information need not be stored on the cell level but only at the region level.

These two advantages allow for a simplified testing procedure which can be implemented in hardware, thereby speeding up the testing process. For each memory element, an identification of the good and bad regions, called a memory element region mask is stored in a memory element region mask database. This database contains, for each memory element, a string of bits equal in length to the number of regions. The bit in j-th place contains value 0 if the j-th region is good or 1 if the j-th region is bad.

Process 40: Process 40 is only useful for applications in which, for each memory device, an array including more than one memory element is provided and there is some interaction between those memory elements which impose certain constraints on the plurality of memory elements as a whole. For example, in SSD (solid state drive) applications, the data transfer is done by "words" containing 16 bits of data. Thus, during each read or write process, 16 cells with the same address on 16 chips belonging to a pair of SIMM modules, are involved. For this application, a word- region comprises the set of regions at each of the 16 memory elements with the same region number. A word-region is termed "problematic" if one or more of these 16 regions is bad.

The access time of the SSD will depend on the number of problematic word-regions. Thus the memory elements must be chosen in such a way as to minimize the number of the problematic word-regions in a SSD.

Another example of the application of process 40 is in one type of 4 megabyte SLMM modules. In this SIMM module there are two 4Mx4 chips and a 4Mxl redundant chip. Typically, a bad region in one of the 4Mx4 chips is stored in the corresponding region in the redundant chip. Therefore, no region can be bad in more than one of the four data entries of each of the 4Mx4 chips and the redundant chip of each SIMM module. Process 40 is an optimization process whereby a multiplicity of memory elements is divided into as many sets as possible of memory elements, each including a predetermined number of elements or range of number of elements and each satisfying the constraints which the application imposes on each set of memory elements. Process 40 may be based on conventional operations research methods such as the above- referenced publications by Kandel, Hertz et al, Kandel et al, Kosko and Taha. Alternatively, particularly if the numbers of memory elements are relatively small, the multiplicity of memory elements may be divided into sets manually. Process 50 Generate a replacement table by assigning a replacement location to defective memory locations. For example, typically in SIMM applications with a controller, each bad region in any of the "non-redundant" memory elements is typically assigned that replacement region in the redundant memory element which has the same region number

Typically in SSD applications each problematic word-region is linked to a replacement word-region such that bad regions in the problematic word-region have corresponding good regions in the replacement word-region. A replacement word region may be linked to more than one problematic word-region Typically, in voice module applications, a table is generated which associates each bad region with an alternative region typically of the same size. Alternatively, the association between bad and replacement region may be implemented logically rather than in a table.

Process 60: The information generated in process 50 is stored in a memory management subsystem in association with that set of memory elements for that application

In some applications, a controller may be assigned to each set of memory elements and the information generated in process 50 may be transferred to the controller. In some applications, such as voice modules the memory management subsystem is contained in part in a DSP (digital signal processor) and a DRAM controller and the information generated in process 50 may be transferred to either of these. In some applications, such as SSD's, the information generated in process 50 is stored in a software called disk drive program In some applications, such as SIMM modules with a controller, the information generated in process 50 is stored in the controller Means other than those mentioned in the above example may also be used; for example, field programmable gate arrays, EPROMs, PROMs and others.

Process 70 A memory system is generated which includes a plurality of defective memory elements including at least one memory element having at least one defective memory cell, the memory management subsystem, and application-specific components.

In some applications, such as SIMM modules without a controller, there is no memory management subsystem That is, the defective regions are bypassed through the utilization of a specially designed integrated circuit board Yet another example of the application of process 40 is a lM x 32 4 megabyte SIMM module. This module comprises 4 independent memory sets each of which can store 1 megabyte of information. If the memory elements used are perfect, such sets can be generated by a pair of IM x 4 DRAMs. If the memory elements contain errors, an additional memory element is added to each defective pair, i.e. to each pair of memory elements including at least one defective memory cell. The additional memory element is also termed herein a "redundant" memory element. The redundant memory element provides storage to which information intended for defective memory cells can be directed. A typical SIMM made from defective memory elements, therefore, may include 4 sets of 3 IM x 4 chips. Typically, a bad region in one of the 1MX4 chips is stored in a corresponding region in the redundant chip. Therefore, no region can be bad in more than four data entries of each set of the 3 1MX4 chips.

It is appreciated that constraints of the application determining how memory elements are to be grouped into sets preferably include not only the memory access needs of the application and, more generally, the needs of the host system in which the memory system resides, but also the capabilities of the memory system resources such as the capabilities of the memory system's controlling device which is used to direct information intended for defective cells elsewhere. For example, if the total number of I/O's in the controlling device is a limiting factor, the grouping step 40 preferably takes into consideration that there exists a limitation on the number of bits that can be processed simultaneously by the controller, i.e. the width of the data.

An additional example is that if the amount of redundant memory is a limiting factor, e.g. if the redundant memory space is provided by the controlling device, whose amount of memory space is limited, the grouping step 40 preferably limits the total number of defective cells in all memory elements in each set.

This can be done simply, for example, by only utilizing defective memory elements having less than N/n defective memory cells, where N is the number of memory cells in the redundant memory space and n is the number of memory elements in each set. Here the defective memory elements are considered only in isolation and not as a set. Another solution is to group the memory elements such that memory elements having more than N/n defective memory cells are grouped with memory elements having less than N/n defective memory cells in such a way that the total number of defective cells in each set is less than N. Here a set of defective memory elements is considered as a unit rather than considering each defective memory element in isolation. The advantage of this solution is at least some of the memory elements having more than N/n defective memory cells are utilized rather than being discarded.

According to a preferred embodiment of the present invention, the method of Fig. 1 is performed in an automated fashion. Fig. 2 is a simplified block diagram of automated apparatus for performing the method of Fig. 1.

The apparatus of Fig. 2 includes a region tester 80 operative to test regions, as described above with reference to step 30, for each chip or memory element 90 in a population of memory elements of which some are defective. A suitable testing board into which the chips 90 may be mounted for region testing is illustrated in Fig. 3, and a suitable (72-pin) programmable memory mapping board on which a plurality of testing boards may be mounted is illustrated in Figs. 4A and 4B (taken together).

The apparatus of Fig. 2 also includes a memory element grouper 100 which is operative, based upon the results of the region testing, to group memory elements 90 into sets fulfilling constraints of the application (Process 40). Each set of memory elements 90 is subsequently mounted onto an individual PCB (printed circuit board) 110.

For example, Figs. 5A and 5B are top and bottom views, respectively, of a board 1 10 constructed and operative in accordance with a preferred embodiment of the present invention. Each side of the board is arranged to receive an array of memory elements, at least one of which is defective, such as six chips 90, and also a controller 114. Optionally, each side of board 110 may have one or more zero-resistors 92 which can be configured so as to optimize the use of the board for a given application. The memory element grouper is preferably operative to group memory elements into sets so as to minimize or reduce the retail value of defective memory elements in the population which are discarded. Alternatively, the memory element grouper is operative to group memory elements into sets so as to minimize or reduce the number of defective memory elements in the population which are discarded.

The memory element grouper typically generates a memory element table 120 including a multiplicity of entries (1600 in the illustrated embodiment) corresponding to the multiplicity of memory elements 90 in the population of memory elements. For each memory element, the following items of information are preferably stored: a. an identifying number; b. a result of testing each of the memory element's regions (a regional testing result); c. a set of memory elements, corresponding to a single PCB 1 10, to which the particular memory element has been assigned, based on its regional testing result; and d. an indication of the position within the set of memory elements to which the memory element has been assigned. Typically, a set of memory elements only or best fills the constraints of a particular application if they are mounted on a board 1 10 in a specific configuration and therefore, each memory element is not only assigned to a board but also to a specific position upon each side of the board, such as positions 1 to 6 in the illustrated embodiment. The memory element grouper 100 preferably provides operating instructions to a robotic arm 130 which mounts each memory element 90 within the population directly in the appropriate position on the board 1 10 to which it has been assigned, all as indicated in the memory element table 120 generated by the memory element grouper. In this embodiment, no intermediate sorting of the memory elements is provided.

Alternatively, however, memory element grouper 100 may provide operating instructions for an intermediate sorting step in which the memory elements 90 are arranged in trays in a configuration which corresponds to the memory element table. Subsequently, a "pick and place" SMT device transfers the ordered memory elements from the trays to the boards 110

Yet another alternative is that the memory element grouper 100 may provide a printout of the memory element table 120 and the mounting of memory elements 90 onto boards 110 may be performed manually by a human operator consulting the printout of table 120

The robotic arm 130 or human operator preferably also mounts a controller 1 14 onto each board 110, either directly or following an intermediate sorting step. The controller 1 14 may comprise any suitable controller such as but not limited to an ISP (in-system programmable) controller. A suitable ISP controller is the 2032- 135LT controller, marketed by Lattice Semiconductor Corporation, Hillsboro, Oregon. The controller 114 operates in accordance with a controlling program which is specific to the board 110 on which it is mounted in that it is constructed and operative to take into account the locations of the defect or defects in one or more of the chips 90 which are mounted on the board

An advantage of using ISP controllers is that each controller can be programmed after it is soldered to its board and therefore, it is not necessary to differentiate between programmed, not-yet-soldered controllers to ensure that each uniquely programmed controller is soldered to the right board.

Therefore, a plurality of boards, having memory elements 90 selected from among a population of memory elements at least some of which are defective, will each typically have a different program in its controller 114, because the pattern of defects within the memory elements 90 differs between boards 110 A controlling program generator 140 is operative to receive per-board defect information, preferably automatically and without operator intervention from the memory element grouper 100. The per-board defect information includes, for each board 1 10, information regarding the defects of the memory elements 90 assigned to each position of that board. The per-board defect information may include the entire contents of the memory element table 120. Using this information, the program generator generates a typically unique program for each board 110 which program is loaded onto the controller 114 of that board. In the illustrated embodiment, the program may be downloaded onto controller 114 of Figs. 5 A and 5B via the CIO connector 150 which may be connected to the printer port of a computer (for example, a PC) which incorporates the program generator.

A preferred implementation of the method of Fig. 1, using the apparatus of Fig. 2 to group a population of, say, 1600 chips, is now described. (The size of the memory element population is preferably chosen to be large enough to allow good grouping but not so large as to be cumbersome A population of 1600 memory elements has been found to be a good population size in the described application, however, for other applications, the optimal memory size may be quite different.)

1 A plurality of testing boards, such as 200 boards, is built based on Fig. 3 The boards are each assigned an identification number

2 The testing boards are filled, with 8 chips each in the illustrated embodiment.

3 The programs listed in Appendices A - B (as well as other programs as needed, such as those disclosed in Applicant's co-pending application PCT US96/03443 and Israel Patent Application No 116220) are entered into files using a standard ASCII editor on an IBM-compatible PC

4 Using any standard compiler (such as Borland's Version 3 1 "C"), an executable file is generated to perform regional testing, as is more fully described in PCT/US96/03443

5 A 72-pin programmable memory mapping board based on Figs 4A and 4B is built and appropriate programs are downloaded into the gate arrays of the board

6 Each of the 200 testing boards is inserted in turn into the programmable memory mapping board and a regional database is generated containing region masks for each chip on the testing board The regional database for each testing board is stored in a file

7. Using any standard compiler (such as Borland's Version 3 1 "C"), an executable file is generated utilizing, e g the files of Appendix A, to perform grouping

8 Grouping is then executed and the output of this step is a report file, which generates sets of six chips for each side of a SIMM Also generated is a binary file which is used by the controlling program generating software

9. A SIMM board is produced according to Figs 5A and 5B

10. Using SMT (surface mounting technology), all the components of the boards of step 9 according to the file generated in step 8 (and according to the appropriate board partslist) are mounted on the boards A standard controller, such as that commercially available from Lattice Corporation, is also mounted on each board This step can be performed either manually or by robotic arm 130 11. Using any standard compiler (such as Borland's Version 3.1 "C"), a program generating executable file is created using the files of Appendix B.

12. An ".LDF" program is created for each controller. (To do this, type "PRLATT M K A", where M is the number of the first controller for which a program is to be generated, K is the number of the last controller for which a program is to be generated and A indicates the A side of the SIMM board. If it is desired to use the B side, type "PRLATT M K B" )

13. The program associated with the controller, such as the Lattice Starter Kit V. 2.71, is installed in an IBM compatible PC. 14. A downloading file is created for each ".LDF" generated in step 12 which is then downloaded using the download cable in the starter kit through the connector 150 shown in Figs. 5A and 5B.

It is appreciated that the particular embodiment described is intended only to provide an extremely detailed disclosure of the present invention and is not intended to be limiting.

It is appreciated that the invention shown and described herein has a broad variety of applications. It is believed that the invention shown and described herein allows defective memory elements to be used in constructing substantially any memory system for any type of data supplying device including SIMM modules with and without controllers, SSDs, switching systems, high definition television, voice memory modules, memory systems for vision applications, and buffers for printers, graphic users interfaces (GUIs) and other applications.

It is appreciated that the software components of the present invention may, if desired, be implemented in ROM (read-only memory) form. The software components may, generally, be implemented in hardware, if desired, using conventional techniques.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention is defined only by the claims that follow: Appendix A

* Name Groupsim c

* Programmer .... M Shnaider

* Copyright (c) Memsys.Ltd

* Date 1995

* Version 1.0

^* Description . . Based on the binary file RDL ASK bin containing the regional masks of the chips tested, generates file report SETSIMM rpt of assignment of the chips to an apropπate place in a SIMM satisfying the restrictions from the file Groupsim mi */

#ιnclude <stdιo.h> #ιnclude <dιr.h> #ιnclude <dos h> #ιnclude <stdlib > #ιnclude <alloc h> #ιnclude <conιo.h> #ιnclude <tιme h> #ιnclude <stπng h> #ιnclude <sys\stat h> #ιnclude <ιo.h> #ιnclude <fcntl.h> #ιnclude <mem h> #ιnclude <groupsιm.h> #ιπclude <setflag h> //

//Simm wicth controller

// AB/BC AB/AC CD/AD CD/BD

// ABC ACD ABD BCD

// aBCD AbCD ABcD ABCd

II w n n n

Λprotoype of function*/ int read_ιnι_file (char *szFileName), int CreatAdrBitMaskRDL (void); void WriteErrStnng (int iNum ,char* IBufNumber.FILE *pstFιle ), int sort_f(ιnt far *a,ιnt far *b), int ChoseChιp1(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed), int ChoseChιp2(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed) , int ChoseChιp3(ιπt iMaskData.mt iNumSetToSimm.int iDataNotUsed) , int ChoseChιp3a(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed), int ChoseChιp3b(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed), int ChoseChιp2b(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed), int ChoseSet(ιnt iNumSetToSimm), void NumDataChιp(voιd), int ChosePassl (int iNumSetToSimm ), int ChosePass2 (int iNumSetToSimm.int iFlagPass), int ChosePass3 (int iNumSetToSimm ), void ClearFlag (void), void ClearFlagl (void), void ClearFlag2 (void), int CheckFlag(ιnt iFlag, int iNumSetToSimm), void SetFlag(ιnt* pFiag, int iNumSetToSimm), void AddChιpMask( char cMaskA. t iNum), void AddChιp(voιd), int CreatOutFιle(char* szFileName), void TextMask(char *BufferData,char cIMaskD), char szAddressBit [INI_VAR_MAX_LENGTH], char szNumberDate [INI_VAR_MAX_LENGTH], char szTypeChip [INI_VAR_MAX_LENGTH], char szBitAddressRDL [INI_VAR_MAX_LENGTH], char szFileNameRDLMask [INI_VAR_MAXJ_ENGTH], char szFileNameFlag [INI_VAR_MAX_LENGTH], char szFileNameReport [INI_VAR_MAX_LENGTH], char szMaxErrRDLtoChose (INI_VAR_MAX_LENGTH], char szMaskDataChipl [INI_VAR_MAX_LENGTH] char szMaskDataChιp2[INI_VAR_MAX_LENGTH], char szMaskDataChιp3[INI_VAR_MAX_LENGTH], char szMaskDataChιp4[INI_VAR_MAX_LENGTH], char szMaskDataChιp5[INI VAR_MAX_LENGTH], char szMaskDataChιp6[INI_VAR_MAX_LENGTH] char szMaskDataChιp7[INI_VAR_MAX_LENGTH], char szMaskDataChιp8[INI_VAR_MAX_LENGTH], char szMaskDataChιp9[INI_VAR_MAX_LENGTH], char szMaskDataChιp10[INI_VAR_MAX_LENGTH], char szMaskDataChipl 1 [INI_VAR_MAX_LENGTH], char szMaskDataChιp12[INI_VAR_MAX_LENGTH], char szNotUseData_Chιp3[INI_VAR_MAX_LENGTH], char szNotUseData_Chιp6[INI_VAR_MAX_LENGTH], char szNotUseData_Chιp9[INI_VAR_MAX_LENGTH], char szNotUseData_Chιp12[IN!_VAR_MAX_LENGTH], char szMaskDataChangeChipl [IN!_VAR_MAX_LENGTH], char szMaskDataChangeChιp4[INI_VAR_MAX_LENGTH], char szMaskDataChangeChιp7[INI_VAR_MAX_LENGTH], char szMaskDataChangeChipl 0[INI_VAR_MAX_LENGTH], char szFιleNameFlagChιp[INI_VAR_MAX_LENGTH], char szFιleNameSetSιmm[INI_VAR_MAX_LENGTH], char szBegιnNumberChιp[8], char ^*szlnιLabels [INI_VARS_NUM] = {

"Number_of_date_to_chιp",

"Type_group_chιp",

"BιtAddress_RDL",

"FιleName_RDLMask",

"FιleName_Report",

"FιleName_FlagChιp",

"FιleName_SetSιmm",

^HMaxErrRDL_to_Chose",

"BeginNumberChip",

"MaskData_Chιρ1",

"MaskData_Chιρ2",

"MaskData_Chιp3",

"MaskData_Chιρ4"

"MaskData_Chιp5",

"MaskData_Chιp6",

"MaskData_Chιρ7",

"MaskData_Chιp8",

"MaskData_Chιp9",

"MaskData_Chιρ10",

"MaskData_Chιp11",

"MaskData_Chιp12",

"NotUseData_Chιp3",

"NotUseData_Chιp6",

"NotUseData_Chιp9",

"NotUseData_Chιp12",

"MaskDataChange_Chιp1 ",

"MaskDataChange_Chιp4",

"MaskDataChange_Chιp7",

"MaskDataChange_Chιp10" }, char *szlnιVars[INI_VARS_NUM] = { szNumberDate, szTypeChip szBitAddressRDL, szFileNameRDLMask, szFileNameReport, szFileNameSetSimm, szMaxErrRDLtoChose, szBeginNumberChip, szMaskDataChipl , szMaskDataChιp2, szMaskDataChιp3, szMaskDataChιp4, szMaskDataChipδ, szMaskDataChipθ, szMaskDataChip7, szMaskDataChipδ, szMaskDataChipθ, szMaskDataChipl 0, szMaskDataChipl 1 , szMaskDataChipl 2, szNotUseData_Chip3, szNotUseData_Chip6, szNotUseData_Chip9, szNotUseData_Chip12, szMaskDataChangeChipl , szMaskDataChangeChip4, szMaskDataChangeChιp7, szMaskDataChangeChipl 0 }; char StrιngErrBuffer[1024]; char szPathNameAdr[4] [INI_VAR_MAX_LENGTH], unsigned long IBitAdrRDLfMAXBITRDL]; int iMaskDataChip[12]; int iFlagChangeChip[12]={1 , 0,0, 1 ,0,0, 1 ,0,0, 1 ,0,0}; //— 1 int iMaskDataChange[12]={6,0,0, 6,0,0, 5,0,0, 12,0,0}, // number group number chip number data //1-12 A B e d int ιNumberNotUsedData[4]={9,10,11 ,12}; // 1 2 3 4 5 6 7 8 9 10 11 12

// A B AB C AC BC - D AD BD - CD int ιAddChip[12]={ 2, 2, 1 ,2 , 1 , 0, 0, 2, 0, 1 , 0, 1 }, int ιNumDataToChιp3[4]={3,3,3,3}, int ιNumRDLJnι,ιNumData,ιNumChιp,ιNumChιpC,ιMaxErrRDLtoChose,ιNumSet, ιNumRDL2.iBegιnNumberChιp,ιFlagAdd, int iNumErrRDLtoChιp[6300][2], char cFlagChose[6300], int iNumChipSet[1600][3], char cSetChipl [32]; char cSetChιp2 [32]; char cSetChip3 [32], long far* IpBufferMaskl ; long far^* IpHomeBufferMaskl , char far* IpBufferMask; char far^* IpHomeBufferMask, char far* IpBufferNum; char far^* IpHomeBufferNum; char far* IpBufferMaskData; char far* IpHomeBufferMaskData; int iNumMask[16], int iFlagChosel , iFlagChose2,iFlagChose3, #pragma argsused int mam (int argc.char *argv Q) I*. */

{ char cMask,Buffer[16],cNumRdl[32],clMask,clMaskdata,c int ιRes,ι,j,k,handle_mask,handle_flag,handle_chιp,handle_sιm, ιNumBιtRDL,ιNumSιm, long ILenfileMask.lLenfileFlag.lLenNum, if ((read_ιnι_fιle(argv[0])) •= 0) exιt(1), NumDataChipO, ιBegιnNumberChιp=atoι(szBegιπNumberChιp), ιNumBιtRDL=CreatAdrBιtMaskRDLO, if ( iNumBitRDL ) { ιNumRDL_lnι=1 , ιNumRDL_lnι «= iNumBitRDL ,} ιf(ιNumBιtRDL > MAXBITRDL) { pnntf ("\n Error number if RDL"), exιt(1),

} ιNumRDL2= ιNumRDL_lnι/2, iMaxErrRDLtoChose =atoι(szMaxErrRDLtoChose ), if ((handle_mask=open(szFιleNameRDLMask,0_BINARYIO_RDONLY))==-1 ) { perror("Error " ), pnntf (" %s",szFιleNameRDLMask) , getchO, return(1),} ILenfileMask =fιlelength(handle_mask), ILenfileFlag =sιzeof(cFlagChose), ILenNum=ILenfιleMask,///sιzeof(long), lpBufferNum=(char far*)farmalloc(ILenNum), lpBufferMask=(char far*)farmalloc(ILenNum), lpBufferMaskData=(char far*)farcalloc(ILenNum,sιzeof(char)), if (lpBufferMask==NULL||lpBufferNum==NULL||lpBufferMaskData== NULL) { pπntf("Not enough memory to allocate buffeΛn"), getchO, /^* terminate program if out of memory */ return (1),} IpHomeBufferMask = IpBufferMask, IpHomeBufferNum = IpBufferNum, IpHomeBufferMaskData = IpBufferMaskData, if ((read(handle_mask,(voιd* )lpBufferMask,ILenfιleMask))==-1){ pnntf ("Error read file %s\n",szFιleNameRDLMask), getchO, retum(1),

} close(handle_mask), iNumChip =ILenfιleMask /(4*sιzeof(char)), for (ι=0, ι< iNumChip, ι++) { memset (cNumRdl.O.iNumRDLJni), cMask=1 ,

cMask«=1 , }/*end for*/ ιNumErrRDLtoChιp[ι][1 J=ι,

_fmemcpy (lpHomeBufferNum+(ι^*ιNumRDL_inι),cNumRdl,ιNumRDL_lnι), }/*end for*/ qsort((voιd*)&ιNumErrRDLtoChιp,(sιze_t)ιNumChιp,4,

(ιnt(*)(const void*, const voιd*))sort_f), ι=ιNumChιp-1 , ιNumSιm=0, for (ι=0, ι<1 ,ι++){ ιNumSιm=0, ιNumSet=0 if (ι'=0) { for (k=0, k< ιNumChιp,k++) { j=ιNumErrRDLtoChιp[ι][1] , ιf(cFlagChose[j]==FLAG_SET_DATA){ cFlagChose[j]=0, break,

} }/*end for*/ } end if^*/ while (1) { ιf(ιNumSιm==8) k=0, ιRes= ChoseSet(1), ιf(ιRes==-1 ) break, ιRes= ChoseSet(2), ιf(ιRes==-1 ) break, ιRes= ChoseSet(3), ιf(ιRes==-1 ) break, ιRes= ChoseSet(4), ιf(ιRes==-1 ) break, ιNumSιm++, }/*end while*/ ιf(cFlagChose[46]'=0) ιRes=0, pπntf("\n Pass=%d Chose Simm to controller =%d\n",ι+1 iNumSim), }/* end for^*/ CreatOutFιle(szFιleNameReport), pnntf ("\n End choseVn"), for (ι=0,ι < ιNumSet,ι++ ) { for (k=0,k < 3, k++){ j=ιNumChιpSet[ι][k], ιRes=(ιnt)^*(lpHomeBufferMaskData+j), if (ιRes==6) pnntf("%4d-%5d",ι,j+1), ιNumMask[ιRes]++,

} }/*end for*/ pπntf("\n AB=%d, AC=%d BC= %d AD=%d BD=%d CD=%d", ιNumMask[3), ιNumMask[5],ιNumMask[6], ιNumMask[9], ιNumMask[10], ιNumMask[12]), pnntf("\n ABC=%d, ABD=%d ACD= %d BCD=%d", ιNumMask[7], ιNumMask[11], ιNumMask[13], ιNumMask[14]), pπntf("\n ABCD=%d",ιNumMask[15]), terminate ClearFlagO, ClearFlagl O, _fmode=0_BINARY, if ((handle_chιp=creat(szFιleNameFlagChιp,S_IREAD|S_IWRITE))==-1) { perror("Error " ), pnntf (" %s",szFιleNameFlagChιp) , getchO, return(1),} if ((handle_sim=creat(szFileNameSetSimm,SJREAD|SJWRITE))==-1) { perror("Error " ), pnntf (" %s",szFιleNameSetSιmm) , getchO, return(1), } if ((wπte(handle_chιp,(voιd* )cFlagChose,ILenfιleFlag))==-1){ pnntf ("Error write file %s\n",szFιleNameFlagChιp), getchO, return(1),

} ι=ιNumSet*3,

ILenNum=ι*sιzeof(ιnt), if ((wrιte(handle_sιm,(voιd* )ιNumChιpSet,ILenNum))==-1){ pnntf ("Error write file %s\n",szFιleNameSetSιmm), getchO, return(1) close(handle_chιp), close(handle_sιm) /^* free the memory */ farfree(lpBufferMask), farfree(lpBufferNum), farfree(lpBufferMaskData), getchO. return (0),} /* */ int ChoseSet(ιnt INumSetToSimm)

/* */

{ int ι,j,k,ιRes,ιNum,ιChose, iDataNotUsed, char cByte, ιNum=(ιNumSetToSιmm-1)^*3, ιRes=CheckFlag(ιFlagChose1 , iNumSetToSimm), ιf(ιRes==-1) goto chose_2, //_ CHOSE- 1 while (1) { ιDataNotUsed=0, ιf(ιNumberNotUsedData [ιNumSetToSιmm-1] < 5) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1], ιRes= ChoseChιp1(ιMaskDataChιp[ιNum],ιNumSetToSιmm, iDataNotUsed), ιf(iRes==-1) { break,} ιNumChιpSet[ιNumSet][0]=ιRes, ιChose=0, ιRes=ChosePass1 (iNumSetToSimm ), if (iRes==1) goto end_c, ιf(ιRes==0) { continue,} }/*end while*/ SetFlag (&ιFlagChose1.iNumSetToSimm), chose_2 ClearFlagl O, // CHOSE-2 // — chose chιp3 3date bad ιRes=CheckFlag(ιFlagChose2, iNumSetToSimm), ιf(ιRes==-1) goto chose_3, whιle(1) { ιRes= ChoseChιp1 (ιMaskDataChιp[ιNum], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) { break, } ιNumChιpSet[ιNumSet][0]=ιRes, ιRes=ChosePass2 (iNumSetToSimm.O), if (ιRes==1) goto end_c, ιf(ιRes==0) { ClearFlaglO,

SetFlag (&ιFlagChose2,ιNumSetToSιmm), goto chose_4, } }//end while

//_ CHOSE-3

// — chose chιp3 2,3,4 date bad

SetFlag (&ιFlagChose2,ιNumSetToSιmm), chose_3

ClearFlagl O, ιRes=CheckFlag(ιFiagChose3, iNumSetToSimm), ιf(ιRes==-1) goto chose_4, while (1){ ιRes= ChoseChιp1(ιMaskDataChιp[ιNum], iNumSetToSimm, iDataNotUsed), ιf(iRes==-1) { break, } ιNumChιpSet[ιNumSet][0]=ιRes, ιRes=ChosePass2 (ιNumSetToSιmm,1), ιf (ιRes==1) goto end_c,

}

SetFlag (&ιFlagChose3,ιNumSetToSιmm), // CHOSE-4 chose_4 while (1) {

ClearFlagl O, ιRes= ChoseChιp1 (ιMaskDataChιp[ιNum], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) { pnntf ("numset =%d chιp= %d",ιNumSetToSιmm,1) return(ιRes),

} ιNumChιpSet[ιNumSet][0]=ιRes, ιRes=ChosePass3 (iNumSetToSimm ), if (ιRes==1) goto end_c, else { pnntf ("numset =%d chιp= %d",ιNumSetToSιmm,2), retum(-1), } } end_c

ClearFlagO,

ClearFlagl O, pnntf ("\n Set%d - m%d m%d m%d ",ιNumSet+1 , ιNumChιpSet[ιNumSet][0]+ιBegιnNumberChιp, ιNumChιpSet[ιNumSet][1]+ιBegιnNumberChιp, ιNumChιpSet[ιNumSet][2]+ιBegιnNumberChιp), ι= ιNumChιpSet[ιNumSet][0], cFlagChose[ι]=FLAG_SET, ι= ιNumChιpSet[ιNumSet][1], cFlagChose[ι]=FLAG_SET, ι= ιNumChιpSet[ιNumSet][2], cFlagChose[ι]=FLAG_SET, cByte=~FLAG_CHOSE, for (ι=0,ι < ιNumChιp,ι++) { cFlagChose[ι] = cFlagChosefi] & cByte,

} ιNumSet++, return(ιNumSet), } /* */ int ChoseChιp1 (ιnt iMaskData.mt ιNumSetToSιmm,ιnt iDataNotUsed)

{ ιnt j,ι,k,ιChose1 , char cTemp,cTemp1 ,cTempa,cTemp1 a,c, char far *lpBuffer, cTemp=(char)ιMaskData, cTemp1=0, if (ιFlagChangeChιp[(ιNumSetToSιmm-1 )*3]) cTempl = ιMaskDataChange[(ιNumSetToSιmm-1 )*3], cTempa=~cTemp, cTempl a=~cTemp1 , for (ι=ιNumChιp-1 ,ι>0, ι--) { j=ιNumErrRDLtoChιp[ι][1] , c= *(lpHomeBufferMaskData +j), if ( cFlagChose[j] ==0 && ((c&cTempa)==0 ||( c&cTemp1a)==0)) { lpBuffer= IpHomeBufferNum +(j*ιNumRDL_lnι) , _fmemcpy (cSetChipl ,lpBuffer,ιNumRDL_lnι), ιf(iDataNotUsed ) { for (k=0,k<ιNumRDL_lnι,k++) cSetChιp1[k]++, }/^*end if*/ cFlagChoseH] =FLAG_CHOSE1 , return (]), }/*end if*/ }/*end for*/ return (-1), } int ChoseChιp2(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed) /* */

( char far ^*lpBuffer, char cIMaskdata, char cTemp, cTempl ,c, int ι,j,k,ιChose2, cTemp=(char)ιMaskData, cTempl =255, if (ιFlagChangeChιp[(iNumSetToSιmm-1)*3 +1]) cTempl = ιMaskDataChange[(ιNumSetToSιmm-1)^*3 +1], for (ι=ιNumChιp-1 ,ι>0, ι-) {

ιChose2=0, //del for chosmg chip Mask 1111 to data for (k=0, k<4, k++) { clMaskdata=*lpBufferMask++, if ( clMaskdata==15) { ιChose2=1 break,

} }/* end for*/ if (ιChose2==1 ) continue, ιf(ιDataNotUsed ) ( for (k=0,k<ιNumRDL_lnι,k++) cSetChιp2[k]++, }/^*end if*/ ιChose2 =0, for (k=0,k<ιNumRDL_lnι ,k++) { ιf((cSetChιp1 [k]+cSetChtp2[k])>ιNumDataToChιp3[ιNumSetToSιmm-1]) { ιChose2=1 , break, }/*end if*/ } /*end for*/ ιf(ιChose2==0) { cFlagChoseh] =FLAG_CHOSE, return (j), }/^*end if^*/ }/*end if^*/ }/*end for*/ return(-1), } /* */ int ChoseChιp2b(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed)

// chose

{ char far ^*lpBuffer, char ccTemp, cTempl .cTempa, cTempl a, int ι,j,k,t,t1 ,ιChose2, char cIMaskdata.clMask, cTemp=(char)ιMaskData, cTempl =255, if (ιFlagChangeChιp[(ιNumSetToSιmrn-1)*3 +1 ]) cTemp1= ιMaskDataChange[(ιNumSetToSιmm-1)*3 +1], cTempa=~cTemp, cTempl a=~cTemp1 , for (ι=0,κιNumChιp, ι++) { j=ιNumErrRDLtoChιp[ι][1], c=*(lpHomeBufferMaskData +j), if ( cFlagChoseh] '=0 ) continue, ιf( ((c&cTempa)==0)||((c&cTemp1a)==0)) { lpBuffer= IpHomeBufferNum +0^*ιNumRDL_lnι) , _fmemcpy (cSetChιp2,lpBuffer,ιNumRDL_lnι), ιf(ιDataNotUsed) { for (k=0,k <ιNumRDL_lnι ,k++) cSetChιp2[k]++, }/*end if*/ ιChose2 =0, for (k=0,k<ιNumRDL_lnι ,k++) { if((cSetChιp1 [k]+cSetChιp2[k])> ιNumDataToChιp3[ιNumSetToSιmm-1]){ ιChose2=1 , break, }/*end if*/ } /*end for*/ ιf(ιChose2==0) { cFlagChose[j] = FLAG_CHOSE, return (j), }/*end if*/ }/^*end if*/ }/*end for*/ retum(-1), } r */ int ChoseChιp3(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed)

{ char far *lpBuffer, int ι,j,k,t,ιChose3, char cIMaskdata.clMask, char cTemp cTempl ,c, cTemp=(char)ιMaskData, cTempl =255, if (ιFlagChangeChιp[(ιNumSetToSιmm-1)^*3 +2]) cTempl = ιMaskDataChange[(ιNumSetToSιmm-1)^*3 +2], for (ι=ιNumChιp-1 ,ι>0, ι~) { j=ιNumErrRDLtoChιp[ι][1], c=*(lpHomeBufferMaskData +j) , if ( cFlagChosefj] ==0 &&( ( c == cTemp) ||(c==cTemp1) ) ) { lpBufferMask= IpHomeBufferMask +(j^*ιNumRDL_lnι), memset (cSetChιp3,0,ιNumRDL_lnι), for(t=0,t < 4 t++) { clMaskdata=^*lpBufferMask++, if (t==ιDataNotUsed-1) continue, clMask=1 , for (k=0,k <ιNumRDL_lnι ;k++) { if (cIMaskdata&clMask) { cSetChιp3[k]++, }/*end for*/ clMask«=1 , } /*end for^*/ }/^*end for^*/ ιChose3 =0, for (k=0,k<ιNumRDL_lnι ,k++) { ιf((cSetChιp1 [k]+cSetChιp2[k]+cSetChιp3[k]) > ιNumDataToChιp3[ιNumSetToSιmm-1]) { ιChose3=1 , break, }/^*end if^*/ } end for*/ ιf(ιChose3==0) { return 0), }/*end if*/ }/*end if*/ }/*end for*/ return(-1), } int ChoseChιp3a(ιnt iMaskData.mt iNumSetToSimm.int iDataNotUsed) /*_ */

{ char far ^*lpBuffer, int ι,j,k,t,ιChose3, char cIMaskdata.clMask, char cTemp, cTempl .cTempa, cTempl a, cFlagC.c, cTemp=(char)ιMaskData, cTempa=~cTemp, cTempl a=0, if (ιFlagChangeChιp[(ιNumSetToSιmm-1)*3 +2]) cTemp1= ιMaskDataChange[(ιNumSetToSιmm-1)^*3 +2], cTempl a=~cTemp1 , for (ι=ιNumChιp-1 ;ι>0, ι-) { j=ιNumErrRDLtoChιp[ι][1], ιf(j==964) c=0, c=*(lpHomeBufferMaskData +j) , cFlagC=cFlagChose[j], if «cFlagChose[j]==FLAG_CHOSE) && 0'= ιNumChιpSet[ιNumSet][1])) cFlagC=0, if ( cFlagC ==0 && ( ((c & cTempa)==0) || ((c & cTempl a)==0) )) { lpBufferMask= IpHomeBufferMask +(j*ιNumRDLJnι), memset (cSetChιp3,0,ιNumRDL_lnι), for(t=0,t <4, t++) { clMaskdata=^*lpBufferMask++, if (t==ιDataNotUsed-1) continue, clMask=1 for (k=0,k <ιNumRDL_lnι ,k++) { if (cIMaskdata&clMask) { cSetChιp3[k]++ }/*end if*/ clMask«=1 , }/*end for*/ }/^*end for^*/ ιChose3 =0, for (k=0,k<ιNumRDL_lnι ,k++) { ιf((cSetChιp1 [k]+cSetChιp2[k]+cSetChιp3[k]) > ιNumDataToChιp3[ιNumSetToSιmm-1 ]) { ιChose3=1 , break, }/*end if*/ } /*end for*/ ιf(ιChose3==0) { return 0), }/*end if*/ }/*end if^*/ }/^*end for*/ return(-1), } /* */ int ChoseChιp3b(ιnt iMaskData.mt ιNumSetToSιmm,mt iDataNotUsed) /*_ */

{ char far *lpBuffer, int ι,j,k.t,ιChose3, char cIMaskdata.clMask, char cTemp,cTemp1 ,c,c1.cFlagC, for (ι=ιNumChιp-1 ,ι>0, ι-) { j=ιNumErrRDLtoChιp[ι][1], c=*(lpHomeBufferMaskData +j) , cFlagC=cFlagChose[j], if ((cFlagChose[j]==FLAG_CHOSE) && 0'= ιNumChιpSet[ιNumSet][1])) cFlagC=0, If (( CFlagC ==0) && ( C==7 || c== 11 || c== 13 || c==14) ) { lpBufferMask= IpHomeBufferMask + *ιNumRDL_lnι), memset (cSetChιp3,0,ιNumRDL_lnι), for(t=0,t < 4 t++) { clMaskdata=*lpBufferMask++, if (t==ιDataNotUsed-1) continue, clMask=1 , for (k=0,k <ιNumRDL_lnι ;k++) { if (cIMaskdata&clMask) { cSetChιp3[k]++, }/*end for*/ clMask«=1 , } /*end for*/ }/*end for^*/ ιChose3 =0, for (k=0,k<ιNumRDL_lnι ,k++) { ιf((cSetChιp1 [k]+cSetChιp2[k]+cSetChιp3[k]) > ιNumDataToChιp3[ιNumSetToSιmm-1 ]) { ιChose3=1 , break, }/^*end if*/ } /^*end for^*/ ιf(ιChose3==0) { return 0), }/^*end if*/ }/*end if*/ }/*end for*/ return(-1), } I* */ int ChosePassl (int iNumSetToSimm )

/* */

{ int i .iRes.iNum, iDataNotUsed, ιChose=0, ιNum=(ιNumSetToSιmm-1)^*3, for (ι=0,κιNumChιp-(ιNumSet*3),ι++) { ιDataNotUsed=0, if (iNumberNotUsedData[ιNumSetToSιmm-1 ]>4 && iNumberNotUsedData [ιNumSetToSιmm-1]<9) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 4, ιRes= ChoseChιp2(ιMaskDataChιp[ιNum+1 ],ιNumSetToSιmm,ιDataNotUsed), ιf(ιRes==-1) break, ιChose=2, ιNumChιpSet[ιNumSet][1 ]=ιRes, ιDataNotUsed=0, ιf(ιNumberNotUsedData [ιNumSetToSιmm-1]>8 && iNumberNotUsedData [ιNumSetToSιmm-1]<12) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 8, ιRes= ChoseChιp3(ιMaskDataChιp[ιNum+2],ιNumSetToSιmm,ιDataNotUsed), ιf(ιRes==-1) continue, ιChose=l , ιNumChιpSet[ιNumSet][2]=ιRes, break, }/*end for*/ ClearFlagO, return (iChose), } /*. */ int ChosePass2 (int iNumSetToSimm.int iFlagPass ) /*. */

{ int i,j,ιRes,ιNum, iDataNotUsed, ιChose=0, ιNum=(ιNumSetToSιmm-1 )*3, for (ι=0,κιNumChιp-(ιNumSet^*3),ι++) { ιDataNotUsed=0, ιf(ιNumberNotUsedData [ιNumSetToSιmm-1]>4 && iNumberNotUsedData [ιNumSetToSιmm-1 ]<9) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 4, ιRes= ChoseChιp2(ιMaskDataChιp[ιNum+1], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) break, ιChose=2, ιNumChιpSet[ιNumSet][1]=ιRes, ιDataNotUsed=0, ιf(ιNumberNotUsedData [ιNumSetToSιmm-1 ]>8 && iNumberNotUsedData [ιNumSetToSιmm-1]<12) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 8, if (ιF!agPass==0) ιRes= ChoseChιp3b(ιMaskDataChιp[ιNum+2],ιNumSetToSιmm,ιDataNotUsed), else ιRes= ChoseChιp3a(ιMaskDataChιp[ιNum+2], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) continue, ιChose=1 , ιNumChιpSet[ιNumSet][2]=ιRes, break, }/*end for*/ ClearFlagO, return (iChose), } int ChosePass3 (int iNumSetToSimm )

/* */

{ int ι,j,ιRes,ιNum, iDataNotUsed, ιChose=0, ιNum=(ιNumSetToSιmm-1)*3, for (ι=0,κιNumChιp-(ιNumSet*3),ι++) { ιDataNotUsed=0, ιf(ιNumberNotUsedData [ιNumSetToSιmm-1]>4 && iNumberNotUsedData [ιNumSetToSιmm-1]<9) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 4, ιRes= ChoseChιp2b(ιMaskDataChιp[ιNum+1], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) break, ιChose=2, ιNumChιpSet[ιNumSet][1]=ιRes, ιDataNotUsed=0. if (iNumberNotUsedData [ιNumSetToSιmm-1]>8 && iNumberNotUsedData [ιNumSetToSιmm-1]<12) ιDataNotUsed= iNumberNotUsedData [ιNumSetToSιmm-1] - 8, ιRes= ChoseChιp3a(ιMaskDataChιp[ιNum+2], iNumSetToSimm, iDataNotUsed), ιf(ιRes==-1) continue, ιChose=1 , ιNumChιpSet[ιNumSet][2]=ιRes, break }/*end for*/ ClearFlagO, return (iChose), } I- */ void ClearFlag (void)

I* */

{ char cByte, cByte=~FLAG_CHOSE, for (ι=0,ι < ιNumChιp,ι++) { cFlagChose[ι] = cFlagChose[ι] & cByte, }

} r -/ void ClearFlagl (void)

{ char cByte, cByte=~FLAG_CHOSE1 , for (ι=0,ι < ιNumChιp,ι++) { cFlagChose[ι] = cFlagChose[ι] & cByte, }

}

/*. */ void ClearFlag2 (void)

{ char cByte, cByte=Fl_AG_SET_DATA|FLAG_ERR , for (ι=0,ι < ιNumChιp,ι++) { cFlagChose[ι] = cFlagChosefi] & cByte, } } int CheckFlag(ιnt iFlag, int iNumSetToSimm)

{ int ιMaskF=1 , if (iNumSetToSιmm^,=1) ιMaskF«=(ιNumSetToSιmm-1 ) , if (iFlag&iMaskF) retum(-1 ), else return(O),

} void SetFlag(mt* pFlag, int iNumSetToSimm)

{ if (ιNumSetToSιmm==1)

^*pFlag|=1 , if (ιNumSetToSιmm==2)

^*pFlag|=2, if (ιNumSetToSιmm==3)

*pFlag|=4, if (iNumSetToSιmm==4)

*pFlag|=8; } void AddChip (void)

char c, for (ι=0,ι < 12,ι ++) { ιf(ιAddChιp[ι]==0) continue, c=ι+1 ,

AddChιpMask(c, lAddChipfi]) , } } void AddChιpMask( char cMaskA.int iNum)

char c, for (ι=0,k=0,ι< iNumChip, ι++) ( j=ιNumErrRDLtoChιp[ι][1], c=^*(lpHomeBufferMaskData +j) , if ((c==cMaskA) && (cFlagChose[|]==FLAG_SET_DATA)){ cFlagChosefj] =0, k++, if (ιNum==k) return,

} }/*end for*/

K void WπteErrStnng (int iNum ,char^* IBufNumber.FILE *pstFιle ) /*

char szBuffer[16], StπngE Buffer[0]=0, for (ι=0, i < iNum, ι++) { sprιntf(szBuffer,"%lu ",*IBufNumber ), strcat(StrιngErrBuffer,szBuffer),

IBufNumber++, }/*end for*/ strcat(StrιngErrBuffer,"\n"), fputs(StπngErrBuffer,pstFιle), } int read_ιnι_fιle (char *szFιleName)

/* */

/* Read config file ^*/

{

FILE ^*pstStream, int i .iFound, char szBuffer [INI_VAR_MAX_LENGTH], char szlniFileName [INI_VAR_MAX_LENGTH], char *PoιntBuf, /* Creting name ιnι_fιle's */ strcpy( szlniFileName.szFileName),

PoιntBuf=strchr( szlniFileName,' '),

PoιntBuf++, strcpy(PoιntBuf,"ιnι"), if ((pstStream = fopen (szlniFileName.V)) == (FILE *)0) { pπntf("Cannot open mi file %s \n",szlnιFιleName), getchO, return (1),

} for (i = 0,ι < INI_VARS_NUM,ι ++) ( if (fseek (pstStream,0L,SEEK_SET)) { f close (pstStream), fpπntf(stderr, "Cannot seek_set into mi file \n"), getch 0, return 1 , }/* end if */ iFound = 0, while (fgets (szBuffer,INI_VAR_MAX_LENGTH, pstStream)) { szBuffer [strlen (szBuffer) - 1] = '\0', if ('strncmp (szBuffer,szlnιLabels[ι], strlen (szlnιLabels[ι] ))) { iFound = 1 , break, } }/* end while */ if (iiFound) ( terminate fclose (pstStream), pnntf (" Error in structure of mi file \n"), getch 0, return(1), } /* end if */ ιf(( PoιntBuf=strchr (szBuffer,'=')) == NULL) goto terminate, PoιntBuf++ iFound = 0

iFound = 1 break, } }

PointBuf- if ('iFound) goto terminate, strcpy (szlnιVars[ι],PoιntBu , }/^*end for ^*/ return (0), } /* */ mt CreatAdrBιtMaskRDL(voιd) r */

char szBufBιtAddressRDL[64], ι=0, strupr( szBitAddressRDL), strcpy(szBufBιtAddressRDL, szBitAddressRDL ), if (szBufBitAddressRDL[0] "='A') return(ι), p= strtok(szBufBιtAddressRDL,"X"), if OP) return (i), do { j=atoι(p+1), IBιtAdrRDL[ι]=1 ,

'f O)

IBιtAdrRDL[ι] «=j, ι⁺⁺, p = strtok(NULL,"X"), } while (p), return (i), } /*. */ int CreatOutFιle(char* szFileName)

/* */

{ void Strset (char^* OutBuffer,FILE^* pstStream, int iNum), char OutBuffer[256],Buffer[16],BufferData[32], char cIMaskR, int ι,j,k,n,ιNum,ιRowSet,ιNumSιmm,ιNumSetSιm FILE *pstStream char ChιpName[100]= "| Set | Chip | DataO Datal Data2 Data3 1 RDL

|\n", if (ιNumRDL_lnι==4) strcpy( ChipName, "| Set | Chip | DataO Datal Data2 Data3 | RDL |\n"), if ((pstStream = fopen (szFιleName,"wt")) == (FILE *)0) { pπntf("Cannot open file %s \n",szFιleName), getchO, return (1),

} spnntf(OutBuffer,

" Set from sample %d chιps1x4 for Simm \n",ιNumChιp), fputs(OutBuffer,pstStream ), spπntf(OutBuffer," Fιle_report %s\n", szFileName), fputs(OutBuffer,pstStream ), spπntf(OutBuffer," RDL = %s\n",szBιtAddressRDL) fputs(OutBuffer, pstStream ), ιNum=78, ιNumSιmm=1 if (ιNumRDL_lnι==4) ιNum=66 ιRowSet=0, ιNumSetSιm=0, for (ι=0,κιNumSet,ι++) { ιf( iNumSetSim ==0) { spπntf (OutBuffer," Simm -%d\n",ιNumSιmm), fputs(OutBuffer, pstStream ), Strset(OutBuffer,pstStream,ιNum), fputs(ChιpName,pstStream ),

Strset(OutBuffer,pstStream,ιNum), }/^*end if*/ for (n=0,n<3, n++) { if (n==0) spnntf (OutBuffer,"|%3d | M%04d | ",ι+1 ,ιNumChιpSet[ι][n]+ιBegιnNumberChιp), else spnntf (OutBuffer,"|%3s | M%04d | \ιNumChιpSet[ι][n]+ιBegιnNumberChιp), k=ιNumChιpSet[ι][n],

IpBufferMask =lpHomeBufferMask +k*ιNumRDL_lnι for (|=0,j < 4,j++){ clMaskR=*lpBufferMask,

TextMask(BufferData.clMaskR), strcat(OutBuffer.BufferData), lpBufferMask++,

} strcat(OutBuffer,"|"),

IpBufferNum =lpHomeBufferNum +k*ιNumRDL_lnι,

lpBufferNum++, strcat(OutBuffer,BufferData), } /*eπd for*/ strcat(OutBuffer," |\n"), fputs(OutBuffer, pstStream ), }/* end for*/

Strset(OutBuffer,pstStream,ιNum), iNumSetSim ++, ιf( ιNumSetSιm==4) { ιNumSetSιm=0. ιNumSιmm++, ιRowSet++ ιf(ιRowSet==3) { ιRowSet=0, fputs("\An",pstStream),

Strset(OutBuffer,pstStream iNum), }/*end if*/ }/*end if*/ }/* end for*/ fputs(" Bad chips \n", pstStream ) for (ι=0, ι< ιNumChιp,ι++) { ιf( cFlagChose[ι] ==(char)FLAG_ERR) { spnntf(OutBuffer " M%04d\n",ι+1), fputs(OutBuffer,pstStream ), }/*end if*/ }/^*end for^*/ fρuts(" Not chosed chips \n", pstStream ), for (ι=0, ι< ιNumChιp,ι++) {

fclose (pstStream), return (0), } /* */ void Strset (char* OutBuffer.FILE* pstStream, int iNum)

{ memset(OutBuffer,'-',ιNum),

OutBuffer[0]=' ',

OutBufferfιNum]=^,\n',

OutBuffer[ιNum+1]=0, fputs(OutBuffer,pstStream ), } /* */ void TextMask(char *BufferData char cIMaskD)

{ char clMask=1 , for (ι=0,ι< ιNumRDL_lnι,ι++) { if (cIMaskD & cIMask ) ^*BufferData++='1', else

^*BufferData++='0', clMask«=1 , }/*end for*/

*BufferData++=' ', if (ιNumRDL_lnι==4) { for (ι=0,ι<4,ι++) ^*BufferData++=' ',

} ^*BufferData++=0.

} void NumDataChιp(voιd)

{ ιMaskDataChιp[0]= atoι(szMaskDataChιpl), ιMaskDataChιp[1]= atoι(szMaskDataChιp2), ιMaskDataChιp[2]= atoι(szMaskDataChιp3), ιMaskDataChιp[3]= atoι(szMaskDataChιp4), ιMaskDataChιp[4]= atoι(szMaskDataChιpS), ιMaskDataChιp[5]= atoι(szMaskDataChιp6), ιMaskDataChιp[6]= atoι(szMaskDataChιp7), ιMaskDataChιp[7]= atoι(szMaskDataChιp8), ιMaskDataChιp[8]= atoι(szMaskDataChιp9), ιMaskDataChιp[9]= atoι(szMaskDataChιplO), ιMaskDataChιp[10] = atoι(szMaskDataChιpH), ιMaskDataChιp[11] = atoι(szMaskDataChιp12), ιMaskDataChange[0] =atoι(szMaskDataChangeChιp1), ιMaskDataChange[3] =atoι(szMaskDataChangeChιp4), ιMaskDataChange[6] =atoι(szMaskDataChangeChιp7), ιMaskDataChange[9] =atoι(szMaskDataChangeChιp10), } /* */ int sort_f(ιnt far *a,ιnt far *b)

/* */

num1=*(ιnt far*)a, num2=*(ιnt far*)b return (num1-num2), }

// file groupsim h

#defιne LENFILE 0x8000

#defιne LENBUFFER 0x4000

#defιne NUMBUFTOFILE 16

#defme INI_VAR_MAX_LENGTH 64 #defιne INI_VARS_NUM 29

#defιne NumAddressBit 20

#defιne MAXBITRDL 7

// file setdlag h

#defιne FLAG_ERR 0x80 #define FLAG_CHOSE 0x1 #defιne FLAG_SET 0x2 #defιne FLAG_SET_DATA 0x4 #defιne FLAG_CHOSE1 0x10

/^* file Groupsim i ^*/

Number_of_date_to_chιp = 4 , — symbol of group chips Type_group_chιp =M BιtAddress_RDL = A0XA8

,-- fiename —

FιleName_RDLMask = rdlmask bin FιleName_Report = setsim rpt FιleName_SetSιmm = setsim bin FιleName_FlagChιp = flagchp bin

BeginNumberChip = 1

,- MaskData = binary code of the data entry quality of the chip 1 if bad cells are allowed in the data entry and 0 if the data entry must be perfect For example 15 meens any chip is allowed

, Groupl MaskData_Chip1 = 3 MaskData_Chip2 = 7 MaskData_Chip3 = 15 NotUseData_Chip3 =0 MaskDataChange_Chip1 = 6

_; Group2

MaskData_Chip4 = 3 MaskData_Chip5 = 13 MaskData_Chip6 = 15 NotUseData_Chip6 =0 MaskDataChange_Chip4 = 5

; Group3

MaskData_Chip7 = 12 MaskData_Chip8 = 11 MaskData_Chip9 = 15 NotUseData_Chip9 =0 MaskDataChange_Chiρ7= 9

, Group4

MaskData_Chip10 = 12 MaskData_Chip11 = 14 MaskData_Chip12 = 15 NotUseData_Chιp12 =0 MaskDataChange_Chip10= 10

;1-Yes 0=No

FlagChipAdd = 0

;from 3 adrress_bit RDL =31 from 2 =15

MaxErrRDL_to_Chose = 15

// file groupsim. mak

.AUTODEPEND

# 'Translator Definitions^* CC = bcc +GROUPSIM.CFG

TASM = TASM

TUB = tlib

TLINK = tlink

LIBPATH = D:\BORLANDC\LIB

INCLUDEPATH = DΛBORLANDCMNCLUDE;.;

# "Implicit Rules* .c.obj:

$(CC) -c {$< }

.cpp.obj: $(CC) -c {$< }

# ^*List Macros* EXE_dependencιes = \ groupsim. obj

# "Explicit Rules* groupsim.exe: groupsim. cfg $(EXE_dependencιes)

$(TLINK) /v/x/c/P-/L$(LIBPATH) @&&| c0l.obj+ groupsim.obj groupsim

# no map file fp87.lib+ mathl.lib+ cl.lib

# 'Individual File Dependencies* groupsim. obj: groupsim. cfg groupsim. c

# "Compiler Configuration File^* groupsim. cfg: groupsim. mak copy &&| -ml -f287 -v

-VI-

-wpro

-weas

-wpre

-l$(INCLUDEPATH)

-L$(LIBPATH)

I groupsim. cfg

// file groupsim.cfg

-ml

-f287

-v

-VI-

-wpro

-weas

-wpre

-ID:\BORLANDC\INCLUDE;.;

-LD:\BORLANDC\LIB rt wq

Appendix B

/* /

* Name Prlatt.c

* Programmer M. Shnaider

* Copyright (c) Memsys.Ltd

* Date 1995

* Version 1.0

* Syntax Prlatt < number of the first Simm number of the last Simm >

* Description Based on the binary file Setsimm.bin, generates a program in .Idf format for the Lattice ispStarter Kit. */

#include <stdio.h>

#include <dir.h>

#include <dos.h>

#include <stdlib.h>

#include <alloc.h>

#include <conio.h>

#include <time.h>

#include <string.h>

#include <sys\stat.h>

#include <io.h>

#include <fcntl.h>

#include <mem.h>

#include <prlatt.h>

//.

//Simm wicth controller // AB/BC AB/AC CD/AD CD/BD // ABC ACD ABD BCD // aBCD AbCD ABcD ABCd II n n n n protoype of function*/ int read_ini_file (char *szFileName); int CreatOutFile(char* szFileName); void ChoseMaskChip(int iSetLat.int iSetToLat); void CreatTypeMask (int iNumType); void CreatEquSet(int iChipSet); int SearchReplace(int iChipSet.char cMaskErr); void WriteDataEquOnt iDataNumD.int iDataNumR.int iNumbit); void WriteReplaceEqu(int iDatNumD,int iDataNumR.int iNumbit); void CreatTextLdfFile(void); void DelBadReplace (void); char far* SearchString (char cSampie.int iNum); char szTypeChip [INI_VAR_MAX_LENGTH]; char szFileNameRDLMask [INI_VAR_MAX_LENGTH]; char szFileNameLdfFile [INI_VAR_MAX_LENGTH]; char szFileNameTempLdfFile [INI_VAR_MAX_LENGTH]; char szFileNameResSetSimm[INI_VAR_MAX_LENGTH]; char szTypeSetSim[INI_VAR_MAX_LENGTH]; char szEquation[16][INI_VAR_MAX_LENGTH]; char szEquData[10][80]; char szEquReplaceData[6][80], char cFlagOneReplace[6]; char cUseReplaceData[6]; char *szlniLabels [INI_VARS_NUM] = {

"Ty pe_grou p_chi p" ,

"FileName_RDLMask",

"FileName_ResSetSimm",

"FileNameTempLdfFile",

"Type_SetSim", "EquationO", "Equationl", "Equatιon2", "Equatιon3", "Equatιon4", "Equations", "Equationβ", "Equatιon7", "Equationβ", "Equatιon9", "Equationl 0", "Equationl 1", "Equationl 2", "Equationl 3", "Equationl 4", "Equationl 5" }, char *szlnιVars[INI_VARS_NUM] = { szTypeChip, szFileNameRDLMask, szFileNameResSetSimm, szFileNameTempLdfFile, szTypeSetSim, (char^*)&szEquatιon(0], (char*)&szEquatιon[1 j, (char^*)&szEquatιon[2], (char*)&szEquatιon[3], (char*)&szEquatιon[4], (char*)&szEquatιon[5], (char^*)&szEquatιon[6], (char*)&szEquatιon[7], (char*)&szEquatιon[8], (char^*)&szEquatιon[9], (char*)&szEquatιon[10], (char*)&szEquatιon[11], (char*)&szEquatιon[12], (char*)&szEquatιon[13], (char*)&szEquatιon[14], (char*)&szEquatιon[15] }, char *F pFlop[4] ={"QA","QB","QC","QD"}, int ιNumRDL_lnι,ιNumChιp,ιNumChιpC,ιNumSet,

// 1 2 4 8 int ιNumShιft[9] ={0,0,1 ,0,2,0,0,0,3}, int ιNumChιpSet[1000][3], char far^* IpBuffer ask, char far^* IpHomeBufferMask, char cMaskChipData [10]; char cMaskReplaceChip [6], char cBufChιp[16], char cBufReplaceChιp[8], char far^* IpBufTempLdf, char far^* IpHomeBufTempLdf, char far "IpBufOutLdf, char far "IpHomeBufOutLdf,

#pragma argsused

/*. */ int main (int argc.char *argv D) r */

{ char cMask,Buffer[16],cNumRdl[32],clMask,clMaskdata,c, int iRes,i,j,k,handte_mask,handle_sim,handle_lat,handle_out,iNumLatSet,

Jlndex.ilndexEnd.iNumSetToSim.iTypeSetSim; long ILeπfileMask.lLenfileSet.lLenTemp; char* Point; char* TempLdf; if (argc<4 || argc>5 ){ printf ("parametrs error <number of first simm> <end simm> <Set-A/B>"); exit (1);

} if ((read_ini_file(argv[0])) != 0) exit(1); iNumRDL_lni=4;

// iNumLatSet=atoi(argv[1]); ilndex=atoi(argv[1]); ilndexEnd=atoi(argv[2]); strupr(argv[3]); iNumSetToSim=1 ; if(^*argv[3]=='A') iNumSetToSim=0; iTypeSetSim=atoi(szTypeSetSim); // strcpy(szFileNameLdfFile,argv[2]); if ((handle_mask=open(szFileNameRDLMask,0_BINARY|0_RDONLY))==-1) { perror("Error:" ); printf (" %s",szFileNameRDLMask) ; getchO; return(1);

} if ((handle_sim=open(szFileNameResSetSimm,0_BINARY|0_RDONLY))==-1) { perrorC'Erron" ); printf (" %s",szFileNameResSetSimm) ; getchO; return(1);

} if ((handle_lat=open( szFileNameTempLdfFile,0_BINARY|0_RDONLY))==-1) { perror("Error:" ); printf (" %s", szFileNameTempLdfFile); getchO; return(1);

}

ILenfileMask =filelength(handle_mask);

ILenfileSet = filelength(handle_sim);

ILenTemp = filelength(handlejat); /^*!!!!!!!!!!! ϋϋϋϋϋϋϋϋdebug */ // ILenfileMask =filelength(handle_mask)/4; lpBufferMask=(char far*)farmalloc(ILenfileMask );

IpBufTempLdf = (char far*)farmalloc(ILenTemp);

IpBufOutLdf =(char far*)farmalloc(ILenTemp+1); if ((lpBufferMask==NULL)j|( lpBufTempLdf==NULL)||(lpBufOutLdf==NULL)){ printfC'Not enough memory to allocate buffertn"); getchO; /* terminate program if out of memory */ return (1);

}

IpHomeBufferMask = IpBufferMask; lpHomeBufTempLdf=lpBufTempLdf; lpHomeBufOutLdf=lpBufOutLdf; if ((read(handle_mask,(void^* )lpBufferMask,ILenfιleMask))==-1){ printf ("Error read file %s\n",szFileNameRDLMask); getchO; return(1);

} if ((read(handle_sim,(void* )iNumChipSet,ILenfileSet))==-1){ printf ("Error read file %s\n",szFileNameResSetSimm); getchO; return(1);

} if ((read(handle_lat,(void* )lpBufTempLdf,ILenTemp))==-1){ printf ("Error read file %s\n",szFiieNameTempLdfFile) ; getchO; return(1);

} lpHomeBufTempLdf=lpBufTempLdf; close(handle_mask); close(handle_sim); close (handlejat); for (i=0;i<ILenTemp;i++) { c=*(lpHomeBufTempLdf +i); if (c==' ) ^*(lpHomeBufTempLdf +i)=' '; }/*end for*/ for (; ilndex < ilndexEnd+1 ; ilndex++){ memset( szEquData,0,sizeof(szEquData)); memset( szEquReplacβData,0,sizeof(szEquReplaceData)); memset( cFlagOneReplace,0,sizeof( cFlagOneReplace)); memset( cUseReρlaceData.O,sizeof( cUseReplaceData)); iNumLatSet=(ilndex-1)*2 +iNumSetToSim; memcpy(lpHomeBufOutLdf,lpHomeBufTempLdf,ILenTemp);

*(lpHomeBufOutLdf+ILenTemp)=0;

//for unsecsefull route if (argc==5) { sprintf(szFileNameLdfFile,"Sim%d%s.jed",ilndex,argv[3]); if ((handle_out=open(szFileNameLdfFile,0_BINARY|0_RDONLY))!=-1){ close(handle_out); continue; } } // create mask to laticce

ChoseMaskChip(iNumLatSet,0); ChoseMaskChip(iNumLatSet,1); CreatTypeMask (iTypeSetSim); if (argc==5 ) { if( *argv[4]==T) j=5; if( *argv[4]=='2') j=0; for (i=j; i<j+5 ;i++){ cMaskChipData[i]=0; } } //create base_Equation for (i=0;t<10; i++) { j= cMaskChipDatafi]; strcpy ((char^*)&szEquData[i],(char^*)&szEquation[j]); while(1) { Point= strchr(szEquData[i],'n'); if(Point==NULL) break; c=i+48; *Point=c; }/*end while*/ }/*end for^*/

CreatEquSet(l); CreatEquSet(2); CreatTextLdfFileO; sprintf(szFileNameLdfFile,"Sim%d%s.ldf',ilndex,argv[3]); if (argc==5) sprintf(szFileNameLdfFile,"Sim%d%s%s.ldr',ilndex,argv[3],argv[4]);

_fmode=0_BINARY; if ((handle_out=creat( szFileNameLdfFile,S_IREAD|S_IWRITE))==-1) { perrorfError:" ); printf (" %s", szFileNameLdfFile); getchO; return(1);

} if ((write(handle_out,(void^* )lpHomeBufOutLdf,ILenTemp))==-1){ printf ("Error write file %s\n",szFileNameLdfFile); getchO; retum(1);

} printf ("%-16s",szFileNameLdfFile); close(handle_out); }/*end for*/ farfree(lpBufferMask); farfree (IpHomeBufTempLdf); farfree(lpHomeBufOutLdf); priπtf("\nEnd of creating ldf-file\n"); getchO; return (0);

}

/* */ void ChoseMaskChip(int iSetLat,int iSetToLat)

/* */

{ int i,j,k,iNum; char c; iNum= iSetLat*2 + iSetToLat; 116- number chip for (k=0;k<2;k++) { j= iNumChipSet[iNum][k]; for (i=0;i <4; i++) { c= "(IpHomeBufferMask +j^*4 +i); cBufChip[iSetToLat*8+i+k*41= c; }/^* end for*/ }/*end for*/ j= iNumChipSet[iNum][2]; for (i=0;i <4; i++) { c= '(IpHomeBufferMask +j*4 +i); cBufReplaceChip[iSetToLat^*4+i]= c; }/^* end for*/

}

/*. */ void CreatTypeMask (int iNumType)

{ switch (iNumType) { case 1 : //AB AB //setl cMaskChipDatafO] = cBufChip[4]; cMaskChipData[1] = cBufChip[5]; cMaskChipData[2] = cBufChip[6]; cMaskChipData[3] = cBufChip[θj; cMaskChipData[4] = cBufChip[1]; //set2 cMaskChipData[5] = cBufChip[12]; cMaskChipData[6] = cBufChip[8]; cMaskChipData[7] = cBufChip[14]; cMaskChipData[8] = cBufChip[15]; cMaskChipData[9] = cBufChip[9]; //setl cMaskReplaceChip[0] = cBufReplaceChip[1] cMaskReplaceChip[1] = cBufReplaceChip[2] cMaskReplaceChip[2] = cBufReplaceChip[3] //set2 cMaskReplaceChip[3] = cBufReplaceChip[4] cMaskReplaceChip[4] = cBufReplaceChip[6] cMaskReplaceChip[5] = cBufReplaceChip[7] break; case 2: //CD CD //setl cMaskChipDatafO] = cBufReplaceChip[0] cMaskChipData[1] = cBufReplaceChip[1] cMaskChipData[2] = cBufReplaceChip[3] cMaskChipData[3] = cBufChip[4]; cMaskChipData[4] = cBufChip[5]; cMaskChipData[5] = cBufReplaceChip [4] cMaskChipData[6] = cBufReplaceChip [5] cMaskChipData[7] = cBufReplaceChip [6] cMaskChipData[8] = cBufChip[13]; cMaskChipData[9] = cBufChip[14]; cMaskReplaceChip[0] = cBufChipf⁷]; cMaskReplaceChip[1] = cBufChip[2]; cMaskReplaceChip[2] = cBufChip[3]; cMaskReplaceChip[3] = cBufChip[15] cMaskReplaceChip[4] = cBufChip[10] cMaskReplaceChip[5] = cBufChip[11] break; case 3: //BC AC

CMaskChipDatafO] = cBufChip[4] cMaskChipData[1] = cBufChip[5] cMaskChipData[2] = cBufChip[6] cMaskChipData[3] = cBufChip[1] cMaskChipData[4] = cBufChip[2] //set2 cMaskChipData[5] = cBufChip[12] cMaskChipData[6] = cBufChip[14] cMaskChipData[7] = cBufChip[15] cMaskChipData[8] = cBufChip[8]; cMaskChipData[9] = cBufChip[10];

//setl cMaskReplaceChip[0] = cBufReplaceChip[1]; cMaskRepiaceChip[1] = cBufReplaceChip[2]; cMaskReplaceChip[2] = cBufReplaceChip[3];

//set2 cMaskReplaceChip[3] = cBufReplaceChip[4]; cMaskReplaceChip[4] = cBufReplaceChip[6]; cMaskReplaceChip[5] = cBufReplaceChip[7]; break; case 4: // AD BD cMaskChipDatafO] = cBufChip[4]; cMaskChipDatafl] = cBufChipfδj; cMaskChipData[2] = cBufChip[7]; cMaskChipData[3] = cBufChipfOJ; cMaskChipData[4] = cBu.Chip[3]; //set2 cMaskChipData[5] = cBufReplaceChip[4]; cMaskChipDatafθ] = cBufReplaceChip[5J; cMaskChipData[7] = cBufReplaceChip[6]; cMaskChipDatafβ] = cBufChip[9]; cMaskChipData[9] = cBufChip[11]; //setl cMaskReplaceChip[0] = cBufReplaceChipfO] cMaskReplaceChipfl] = cBufReplaceChip[1] cMaskReplaceChip[2] = cBufReplaceChip[3] //set2 cMaskReplaceChip[3] =cBufChip[13]; cMaskReplaceChip[4] = cBufChip[14]; cMaskReplaceChip[5] = cBufChip[15]; break; case 11 : //AB AB //setl

CMaskChipDatafO] = cBufChipfO]; cMaskChipData[1] = cBufChip[1]; cMaskChipData[2] = cBufChip[4]; cMaskChipData[3] = cBufChip[5]; cMaskChipDataf4] = cBufChip[6]; //set2 cMaskChipData{5] = cBufChipfβ]; cMaskChipData[6] = cBufChip[9]; cMaskChipData[7] = cBufChip[12]; cMaskChipData[8] = cBufChip[14]; cMaskChipData[9] = cBufChip[15]; //setl cMaskReplaceChip[0] = cBufReplaceChip[1] cMaskReplaceChip[1] = cBufReplaceChip[2] cMaskReplaceChip[2] = cBufReplaceChip[3] //set2 cMaskReplaceChip[3] = cBufReplaceChip[4] cMaskReplaceChip[4] = cBufReplaceChip[6] cMaskReplaceChip[5] = cBufReplaceChip[7] break; case 12: //CD CD

//setl cMaskChipDatafO] = cBufChip[2]; cMaskChipData[1] = cBufChip[3]; cMaskChipData[2] = cBufChip[4]; cMaskChipData[3] = cBufChip[5]; cMaskChipData[4] = cBufChip[7];

//set2 cMaskChipData[5] = cBufChip[10]; cMaskChipDatafδ] = cBufChip[11]; cMaskChipData[7] = cBufChip[13]; cMaskChipData[8] = cBufChip[14]; cMaskChipDatafθ] = cBufChip[15];

//setl cMaskReplaceChipfO] = cBufReplaceChipfO]; cMaskReplaceChipfl] = cBufReplaceChipfl ]; cMaskReplaceChip[2] = cBufReplaceChip[3]; //set2 cMaskReplaceChip[3] = cBufReplaceChip[4]; cMaskReplaceChip[4] = cBufReplaceChipfδj; cMaskReplaceChip[5] = cBufReplaceChipfβj; break; case 13: //BC AC //set . cMaskChipData[0] = cBufChip[2]; cMaskChipDatafl] = cBufChipflj; cMaskChipData[2] = cBufChipf4]; cMaskChipData[3] = cBufChipfδ]; cMaskChipData[4] = cBufChipfθj; //set2 cMaskChipData[5] = cBufChip[8]; cMaskChipData[6] = cBufChipflO]; cMaskChipDataf7] = cBufChip[12]; cMaskChipData[8] = cBufChip[14]; cMaskChipData[9] = cBufChip[15]; //setl cMaskReplaceChipfO] = cBufReplaceChipfl]; cMaskReplaceChipfl] = cBufReplaceChipf2]; cMaskReplaceChip[2] = cBufReplaceChip[3]; //set2 cMaskReplaceChipf3] = cBufReplaceChip[4]; cMaskReplaceChip[4] = cBufReplaceChip[6]; cMaskReplaceChip[5] = cBufReplaceChip[7]; break; case 14: //AD BD //setl cMaskChipDatafO] = cBufChipfOJ; cMaskChipData[1] = cBufChip[3]; cMaskChipData[2] = cBufChip{4]; cMaskChipData[3] = cBufChip[5]; cMaskChipData[4] = cBufChip[7]; //set2 cMaskChipData[5] = cBufChip[9]; cMaskChipData[6] = cBufChipfH]; cMaskChipDatafV] = cBufChip[13]; cMaskChipData[8] = cBufChip[14]; cMaskChipData[9] = cBufChip[15]; //setl cMaskReplaceChip[0] = cBufReplaceChipfO]; cMaskReplaceChipfl] = cBufReplaceChipfl]; cMaskRepiaceChip[2] = cBufReplaceChip[3]; //set2 cMaskReplaceChip[3] = cBufReplaceChip{4]; cMaskReplaceChip[4] = cBufReplaceChipfδ]; cMaskReplaceChip[5] = cBufReplaceChip[6]; break; default: break;

}/* end switch*/

}

/* */ void CreatEquSet(int iChipSet) /* */

{ int ij.k; char cMask.cErr.iDataNumR; for (i=(iChipSet-1)*5; i < (iChipSet-1)^*5+5; i++ ){ for 0=O,cMask=1 ;j<iNumRDL_lni;j++) { cErr=cMaskChipData[i] & cMask; if(cErr) { iDataNumR=SearchReplace(iChipSet,cErr); if(iDataNumR==-1) { priπtf(Εrror of chose"); getchO; exit(1);

} k=iNumShiftfcMask]; WriteDataEqu(i.iDataNumR.k); cUseReplaceData[iDataNumR]=1 ; WriteReplaceEqu(i.iDataNumR.k); } /"end if*/ cMask«=1 ; }/*end for*/ }/*end for*/

}

/* */ int SearchReplace(int iChipSet.char cMaskErr)

/* */

{ int ij; for (i=(iChipSet-1)^*3;i<(iChipSet-1)^*3+3;i++){ if( (cMaskReplaceChipfi] & cMaskErr)==0) { cMaskReplaceChip[i]|=cMaskErr; retum(i); }/*end if^*/ }/*end for*/ retum(-1);

}

/*. */ void WriteDataEqu(int iDataNumD.int iDataNumR.int iNumbit) /* */

{ int i,j; char szBuffer[32]; sprintf(szBuffer," # ( %s%d & %s );",RNAME,iDataNumR,FlipFlopfiNumbit]); j=strleπ (szEquDatafiDataNumD]); if (szEquData[iDataNumD][j-1 ]==';') szEquDatafiDataNumD][j-1 ]=0; strcat (szEquDatafiDataNumD],szBuffer);

}

/* */ void WriteReplaceEquOnt iDataNumD.int iDataNumR.int iNumbit) I* */

{ int i,j; char szBuffer[32]; if (IcFlagOneReplacefiDataNumR]) { cFlagOneReplacefiDataNumR] = 1 ; sprintf (szBuffer, "( %s%d & %s );",DNAME,iDataNumD,FlipFlop[iNumbit]); strcpy ( szEquReplaceData[iDataNumR],szBuffer); }else ( j=strien (szEquReplaceDatafiDataNumR]); szEquReplaceDatafiDataNumR][j-1]=0; spnntf (szBuffer," # ( %s%d & %s ),",DNAME,ιDataNumD,FlιpFlopfιNumbιt]), strcat ( SzEquReplaceDatafiDataNumR], szBuffer), } } I* */ void DelBadReplace (void)

char far^* IpPoint, char c.cTemp, fo

continue, lpPoιnt=SearchStπng(ϊ,ι), while (1) { c=*lpPoιnt~, if (c=='A') { lpPoιnt++, ^*lpPoιnt++=7', *lpPomt++=V, break, }/*end if*/ }/*end while*/ }/^*end for*/ for (ι=0, i < 6, ι++ ){ for 0=0, j < 4 ,j++) { lpPoιnt=SearchStπng('p',ι), cTemp='/',

cTemp=' ', IpPoint-, *lpPoιnt++ = ' ', *lpPoιnt++ = cTemp, ^*lpPoιnt++ = cTemp, }/*end for*/ }/*end for*/

}

/*. */ void CreatTextLdfFile (void)

/*. */

char far * IpPoint, for (ι=0, ι< 10,ι++) { lpPoιnt=SearchStπng(^,d',ι), j=_fstrten(szEquData[ι]), if (szEquDatafι][1 ]=="#') szEquDatafι][1]=",

_fstmcpy (lpPoιnt,szEquData[ι] ), }/*end for*/ for (ι=0,ι< 6,ι++) { lpPoιπt=SearchStπng(V,ι), j=_fstrlen(szEquReplaceDatafι]),

_fstmcpy (lpPoιnt,szEquReplaceData[ι],j), }/*end for*/ DelBadReplaceO, } r *ι char far* SearchStnng (char cSample.iπt iNum) /^• { int ij; char far *lpPoint,*lpBuf; char c; lpBuf=lpHomeBufOutLdf; while(1) { IpPoint = _fstrchr(lpBuf,'='); if (lpPoint==NULL) retum(lpPoint); lpBuf=lpPoint+1 ; c=*(lpPoint+1); if (c==cSample) { c=*(lpPoint+2); if (c==iNum+48) //40 code 0 return(lpPoint+1); }/^*end if^*/ } /*end while*/ lpPoint=NULL; return (IpPoint);

I int read_ini_file (char ^*szFileName) r */

// Read config file.

{ FILE *pstStream; int ij, iFound; char szBuffer [INI_VAR_MAX_LENGTH]; char szlniFileName [INI_VAR_MAX_LENGTH]; char *PointBuf;

/^* Creting name ini_file's 7 strcpy( szlniFileName, szFileName); PointBuf=st rch r( szlniFileName,¹.'); PointBuf++; strcpy(PointBuf,"ini"); if ((pstStream = fopen (szlniFileName,"r")) == (FILE *)0) { printffCannot open ini file. %s \n", szlniFileName); getchO; return (1);

} for (i = 0;i < INI_VARS_NUM;i ++) { if (fseek (pstStream,OL,SEEK_SET)) { fclose (pstStream); fprintf(stderr, "Cannot seek_set into ini file.\n"); getch 0; return 1 ; }/* end if 7 iFound = 0; while (fgets (szBuffer,INI_VAR_MAX_LENGTH, pstStream)) { szBuffer [strlen (szBuffer) - 1] = '\0'; if (Istmcmp (szBuffer.szlniLabelsfi], strlen (szlniLabels[i]))){ iFound = 1 ; break;

} }/* end while 7 if (MFound) { terminate: fclose (pstStream), pnntf (" Error in structure of ini file \n"); getch 0, return(1), } /* end if 7 ιf(( PointBuf=strchr (szBuffer, '=')) == NULL) goto terminate, PoιntBuf++; iFound = 0; for 0=O;j<INI_VARS_NUM;j++) { if (*PointBuf++ ι= "){ iFound = 1 ; break,

} }

PointBuf--; if (MFound) goto terminate, strcpy (szlnιVars[ι], PointBuf), }/*end for 7 return (0),

}

// file prlatt.h

#defιne INI_VAR_MAX_LENGTH 64

#defιne INI_VARS_NUM 21

#defιne DNAME "ZD"

#defιne RNAME "ZDQR"

/*_ */

/* Prlatt.ini 7

/* */

; — symbol of group chips Type_group_chιp =M

, filename

FileName_RDLMask = rdlmask.bin

FιleName_ResSetSimm = setsim.bin

FileNameTempLdfFile =Temp.ldf

;~1= AB AB CD CD 2=

Type_SetSιm = 2

Equatιon0 = ZDQn;

Equationl = ( ZDQn & IQA )

Equation2 = ( ZDQn & IQB )

Equatιon3 = ( ZDQn & QC ) # ( ZDQn & QD )

Equatιon4 = ( ZDQn & !QC )

Equationδ = ( ZDQn & QB ) # ( ZDQn & QD )

Equationβ = ( ZDQn & QA ) # ( ZDQn & QD )

Equatιon7 = ( ZDQn & QD )

Equationδ = ( ZDQn & IQD )

Equatιon9 = ( ZDQn & QB ) # ( ZDQn & QC )

Equationl 0 = ( ZDQn & QA ) # ( ZDQn & QC )

Equationl 1 = ( ZDQn & QC )

Equationl 2 = ( ZDQn & QA ) # ( ZDQn & QB )

Equationl 3 = ( ZDQn & QB )

Equationl 4 = ( ZDQn & QA )

Equationl 5 =

// file prlatt.mak

.AUTODEPEND

# "Translator Definitions*

CC = bcc+PRLATTCFG

TASM =TASM TLINK = tlmk

LIBPATH = D \BORLANDC\LIB

INCLUDEPATH = D \BORLANDC\INCLUDE, ,

# "Implicit Rules* c.obj

# ^*Lιst Macros^*

EXE_dependencιes = \ priatt obj

# *Explιcιt Rules^* priatt exe priatt cfg $(EXE_dependencιes)

$(T INK) /v/x c/P-/L$(LIBPATH) @&&| cOI obj+ priatt obj priatt emu

mathl lιb+ cl lib

# individual File Dependencies* priatt obj priatt cfg priatt c

# "Compiler Configuration File* priatt cfg priatt mak copy &&| -ml -v

-VI-

-wpro -weas -wpre

-l$(INCLUDEPATH) -L$(LIBPATH) I priatt cfg

// file priatt cfg

-ml

-v

-VI-

-wpro

-weas

-wpre

-ID \BORLANDC\INCLUDE, ,

-LD.\BORLANDC\LIB

//*^* design witch 10 date 6 replace ABO AB1 -input 10,11 // CLK =RAS

LDF 1 00 00 DESIGNLDF, DESIGN dsιm32lat, PROJECTNAME psιm32lat, PART ispLSI2032-135LJ44;

DECLARE

END; //DECLARE

//""DO out clb - 4 SYM GLB AO 1 ; SIGTYPE QAREG SIGTYPE QBREG SIGTYPE QCREG SIGTYPE QD EG EQUATIONS QA.PTCLK= RAS; QA= IAB0&IAB1; QB.PTCLK = RAS QB = AB0&!AB1; QC.PTCLK = RAS QC= IAB0&AB1; QD.PTCLK = RAS QD = AB0&AB1; END; END;

II****** j 3 delay.OE by read ******* out clb - 4

SYM GLB A1 1 ;

SIGTYPE OETMPOUT;

SIGTYPE OEDQOE;

SIGTYPE RPREG;

EQUATIONS

RP.PTCLK= RAS;

RP=!CAS1 # ICAS2;

OEDQ = RAS & !WE;

OETMP = (RAS & WE & ICAS1 & !RP) # (RAS & WE & ICAS2 & IRP);

ADQRO

it******** Γ- Λ *************** _. | _ A

SYM GLB A2 1 ; EQUATIONS ADQO = ZDO; ADO

/I_{**** D2} 3 _*** out clb - 4

SYM GLB A3

EQUATIONS

ADQ2 = ZD2 ;

AD2

=d3

END; END,

II_******* _D ««"> out clb - 4

SYM GLB A4 1 , EQUATIONS ADQ4 = ZD4, AD4

=d4

ADQ5 = ZD5, AD5

=d5

END, END,

II**** _D5 *** out clb - 4

SYM GLB A5 1 ,

EQUATIONS

ADQ6 = ZD6,

AD6

=d6

ADQ7 = ZD7, AD7

//" "D8 DQRO DQR1 out clb - 4

SYM GLB A6 1 ,

EQUATIONS

ADQ8 = ZD8,

AD8

=d8

ADQ9=ZD9, AD9

// * *DQR2 DQR3 DQR4 DQR5 out clb - 4

SYM GLB A7 1 ,

EQUATIONS

ADQR2

=r4

ADQR5

ij***** DI *************

SYM IOC IO 1 , XPIN I XABO LOCK 14, IB11(AB0,XAB0), END,

SYM IOC 11 1 ,

XPIN I XAB1 LOCK 24,

IB11(AB1 ,XAB1), END;

SYM IOC IO01 ; XPINIOXCAS1 LOCK 30; IB11(CAS1,XCAS1); END;

SYM IOC I01 1; XPINIOXCAS2 LOCK 17; IB11(CAS2,XCAS2); END;

SYM IOC I02 1 ;

XPIN IOXRAS LOCK 18;

IB11(!RAS,XRAS);

END;

SYM IOC I03 1 ; XPIN IOXWE LOCK 19; IB11(WE,XWE); END;

SYM IOC I04 1 ; XPIN IO XOETMP LOCK 4; OB11 (XOETMP.OETMP); END;

SYM IOCGOE01;

XPIN GOE XENOUT LOCK 2;

IB11 (ENOUT.XENOUT);

END;

SYM IOC I051 ;

XPIN IO XDQO PULLUP LOCK 20 ;

BI11 (ZDQ0,XDQ0,ADQ0,OEDQ);

END;

SYM IOC I061 ;

XPIN IO XDO LOCK 29;

Bill (ZD0,XD0,AD0,ENOUT);

END;

SYM IOC I071 ;

XPIN IO XDQ1 PULLUP LOCK 22;

BI11 (ZDQ1,XDQ1,ADQ1,OEDQ);

END;

SYM IOC I081; XPINIOXD1 LOCK 21; BI11 (ZD1,XD1,AD1,ENOUT); END;

SYM IOC I091 ;

XPIN IO XDQ2 PULLUP LOCK 42;

BI11 (ZDQ2,XDQ2,ADQ2,OEDQ);

END;

SYM IOC IO101;

XPIN IO XD2 LOCK 9;

BI11 (ZD2,XD2,AD2,ENOUT);

END; SYM IOC I011 1

XPIN IO XDQ3 PULLUP LOCK 6,

BI11 (ZDQ3,XDQ3,ADQ3,OEDQ),

END,

SYM IOC 1012 1 ,

XPIN IO XD3 LOCK 7,

BI11 (ZD3,XD3,AD3,ENOUT),

END,

SYM IOC 1013 1 ,

XPIN IO XDQ4 PULLUP LOCK 8,

BI11 (ZDQ4,XDQ4,ADQ4,OEDQ),

END,

SYM IOC I014 1 ,

XPIN IO XD4 LOCK 37,

BI1 1 (ZD4,XD4,AD4,ENOUT),

END,

SYM IOC 1015 1 ,

XPIN IO XDQ5 PULLUP LOCK 44

BI11 (ZDQ5,XDQ5,ADQ5,0EDQ),

END,

SYM IOC 1016 1 ,

XPIN IO XD5 LOCK 5,

BI11 (ZD5,XD5,AD5,ENOUT),

END,

SYM IOC 1017 1 ,

XPIN IO XDQ6 PULLUP LOCK 38,

BI11 (ZDQ6,XDQ6,ADQ6,OEDQ),

END,

SYM IOC 1018 1 ,

XPIN IO XD6 LOCK 41 ,

BI11 (ZD6,XD6,AD6,ENOUT),

END,

SYM IOC 1019 1 ,

XPIN IO XDQ7 PULLUP LOCK 10 ,

BI11 (ZDQ7,XDQ7,ADQ7,OEDQ),

END,

SYM IOC IO20 1 ,

XPIN IO XD7 LOCK 43,

BI11 (ZD7,XD7,AD7,ENOUT),

END,

SYM IOC 1021 1 ,

XPIN IO XDQ8 PULLUP LOCK 16 ,

BI11 (ZDQ8,XDQ8,ADQ8,OEDQ),

END,

SYM IOC 1022 1 , XPIN IO XD8 LOCK 25, BI11 (ZD8,XD8,AD8,ENOUT), END, SYM IOC I023 1 ;

XPIN IO XDQ9 PULLUP LOCK 32 ;

BI11 (ZDQ9.XDQ9.ADQ9.OEDQ);

END;

SYM IOC I024 1 ;

XPIN IO XD9 LOCK 27 ;

BI11 (ZD9.XD9.AD9.ENOUT);

END;

=pOSYM IOC I025 1 ;

=pOXPIN IO XDQRO PULLUP LOCK 40 ;

=p0BI11 (ZDQR0.XDQR0.ADQR0.OEDQ);

=p0END;

=p1SYM IOC I026 1 ;

=p1XPIN IO XDQR1 PULLUP LOCK 39;

=p1 BI11 (ZDQR1.XDQR1.ADQR1 ,OEDQ);

=p1END;

=p2SYM IOC I027 1 ;

=p2XPIN IO XDQR2 PULLUP LOCK 15;

=p2BI11 (ZDQR2,XDQR2,ADQR2,OEDQ);

=p2END;

=p3SYM IOC I028 1 ;

=p3XPIN IO XDQR3 PULLUP LOCK 26;

=p3BI11 (ZDQR3,XDQR3,ADQR3,OEDQ);

=p3END;

=p4SYM IOC I029 1 ;

=p4XPIN IO XDQR4 PULLUP LOCK 31 ;

=p4BI11 (ZDQR4,XDQR4,ADQR4,OEDQ);

=p4END;

=p5SYM IOC IO30 1 ;

=p5XPIN IO XDQR5 PULLUP LOCK 28;

=p5BI11 (ZDQR5,XDQR5,ADQR5,OEDQ);

=p5END;

END; //LDF DESIGNLDF

Claims

Claims 1. Apparatus for generating a plurality of memory systems from a population of memory elements (90) including non-perfect memory elements each including at least one defective memory cell, the apparatus comprising: a region tester (80) operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element; a memory element grouper (100) operative to group said population of memory elements into a plurality of sets based on said regional testing results; and a controlling program generator (140) operative to automatically generate a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets

2 Apparatus according to claim 1 and also comprising robotic apparatus (130) operative to generate a memory system using the memory elements in an individual one of the plurality of sets and the controller.

3. Apparatus according to claim 1 or claim 2 wherein at least one of the memory systems includes an ISP controller and wherein the controlling program generator is operative to automatically generate a controlling program for the ISP controller

4 Apparatus according to any of the preceding claims wherein the controlling program generator generates a controlling program for a particular memory system from among said plurality of memory systems according to the regional testing results of all non-perfect memory elements in said particular memory system.

5. An automated method for generating a plurality of memory systems from a population of memory elements including non-perfect memory elements each including at least one defective memory cell, the method comprising. testing regions within each non-perfect memory element for defective cells and generating a regional testing result for each non-perfect memory element; grouping said population of memory elements into a plurality of sets based on said regional testing results; and automatically generating a controlling program for a programmable controller within a memory system, the memory system also including the memory elements in an individual one of the plurality of sets.

6. Apparatus for generating a plurality of memory systems from a population of memory elements including non-perfect memory elements each including at least one defective memory cell, each of the plurality of memory systems including at least one memory system component, the apparatus comprising: a region tester operative to test regions within each non-perfect memory element for defective cells and to generate a regional testing result for each non-perfect memory element; and a memory element grouper operative to group said population of memory elements into sets based on: said regional testing results, at least one constraint on each of said plurality of memory systems, and at least one constraint on each of said memory system components.