WO1996029656A1

WO1996029656A1 - Interprocessor communications system

Info

Publication number: WO1996029656A1
Application number: PCT/CA1996/000172
Authority: WO
Inventors: Brian Wirth; Tom Duxbury; Dave Coomber; Jerome Gobuyan
Original assignee: Newbridge Networks Corporation
Priority date: 1995-03-21
Filing date: 1996-03-20
Publication date: 1996-09-26
Also published as: GB9505724D0; AU4935696A

Abstract

A multiprocessor system comprises a plurality of processors attached to a common bus. A communication logic unit independent from said bus provides interprocessor cummunication. Interrupts triggered by the occurence of events signal the events via the logic unit. The source and priority of the events are identified.

Description

INTERPROCESSOR COMMUNICATIONS SYSTEM

This invention relates to an interprocessor communications system.

Multiprocessors require a method of communication with each other. This is essentially the ability to signal the occurrence of events between processors. Furthermore, a method of signaling several types of events must be provided.

Traditionally, this interprocessor communication has been done using flags located in memory shared by all processors in the system. A processor must then poll the flags in order to determine if there is a message or event from another processor. This leads to a bottleneck in the shared memory as well as latencies associated with the length of the polling interval, especially if several flags must be checked each time.

An object of the invention is to alleviate this problem.

According to the present invention, there is provided a multiprocessor system comprising a communications logic unit for connecting a group of processors, which provides a mechanism for signaling the occurrence of events between processors. Means are provided for generating interrupts triggered by the occurrence of events, and for identifying the source and priority of the events.

This communications logic unit may directly accessible by each processor on its local bus, thereby eliminating the shared memory bottleneck.

Once a processor has been signaled that an event has occurred, that processor will then retrieve the full event description from shared memory. Accesses to shared memory for the purposes of interprocessor communication are therefore limited to storage and retrieval of event descriptions. Polling for events in shared memory is eliminated.

The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:-

Figure 1 is a block diagram of a multiprocessor system; and

Figure 2 shows the channel connections between the different processors in the multiprocessor system.

Referring to Figure 1, the multiprocessor system accordance to the invention is arranged on a card comprising three processors 1, 2, and 3. The processors 1, 2, 3 are connected to a main bus 5 through buffers . The main bus 5 is connected to shared memory 11. The processors 1, 2, 3 are also connected directly to the interprocessor communication logic 6, which is implemented in a field programmable gate array (FPGA) .

Referring now to Figure 2, the interprocessor communication logic 6 comprises attention control registers 7, attention status registers 8, and attention mask registers 9. The latter are output to OR gates 10, which generate the attention interrupts for the respective processors 1, 2, 3. Figure 2 shows the arrangement of channels A, B, C, D between the registers of the different processors 1, 2, 3.

The attention status register 8 of one processor, for example processor 2, is used to set the 'Attention' bit in the Attention Status Register 8 of another (target) processor, for example processor 3. There are four bits A, B, C, D between any two processors in subregisters 7a, 7b. These are cross connected to associated subregisters 8a,8b identified with originating processor.

Each one of the bits in the subregisters is used to indicate that one of four possible events has occurred. The initiating processor records the details of the event in shared memory and then sets the appropriate attention request bit for the target processor. Reading this register yields the current state of the attention bits that is seen by the target processors. Typically, if an initiating processor reads this as a '1' , it means that the target processor has yet to complete servicing of the last event; however the bit may be set again if desired. These registers are read/write. Writing a '1' to any bit will set the bit, writing a '0' to any bit has no effect. The bit fields appear differently for each processor, and are shown below:

Attention Request Registers

Processor 1 Proc 2 Proc 2 Proc 2 Proc 2 Proc 3 Proc 3 Proc 3 Proc 3 Attn D Attn C Attn B Attn A Attn D Attn C Attn B Attn A

Processor 2 Proc 1 Proc 1 Proc 1 Proc 1 Proc 3 Proc 3 Proc 3 Proc 3

Attn D Attn C Attn B Attn A Attn D Attn C Attn B Attn A

Processor 2 Proc 1 Proc 1 Proc 1 Proc 1 Proc 2 Proc 2 Proc 2 Proc 2

Attn D Attn C Attn B Attn A Attn D Attn C Attn B Attn A

The attention status register 7 is a read/write register, and reflects the raw (i.e. unmasked) 'Attention' request bits from each other processor. When a bit is set in this register, another processor has requested its associated processor' s attention for an event that has occurred. The details of the event may then be read from shared memory by the target processor. Writing a '1' to any bit in this register will clear the bit in this register as well as the corresponding bit in the initiating processor's Attention Request Register 7. This indicates that the target processor has completed processing the event. The bit fields appear differently for each processor, and are the same as the Attention Request Register above.

The Attention Mask Register 9 provides an Attention interrupt mask, which when set to a ^Λl', will enable interrupts from the corresponding source processor. The interrupt mask registers are read/writeable. When the Attention bit is set in the Status register, and the corresponding interrupt mask bit is set, an interrupt is generated. The mask register is cleared at Reset, disabling all interrupts. The bit fields appear differently for each processor, and are the same as the Attention Request Register above.

Claims

- 5 -Claims :

1. A multiprocessor system comprising a plurality of processors attached to a common bus, characterized in that a communication logic unit independent said bus provides interprocessor communication.

2. A multiprocessor system as claimed in claim 1, characterized in that it further comprises means for signaling the occurrence of events between said processors over said communications network, means for generating interrupts triggered by the occurrence of events, and means for identifying the source and priority of events.

3. A multiprocessor system as claimed in claim 1, characterized in that said processors have direct access to said communication logic unit without the need to compete for access to shared memory.

4. A multiprocessor system as claimed in claim 2, characterized in that said communication logic unit is implemented as a field programmable gate array.

5. A multiprocessor system as claimed in claim 3, characterized in that for each processor there is provided an attention request register and an attention status register, the attention request registers communicating directly with the attention status registers of other processors .

6. A multiprocessor system as claimed in claim 5, characterized in that said status registers each contain subregisters connected to the respective attention request registers of the other processors.

7. A multiprocessor system as claimed in claim 5, characterized in that said attention request registers each contain subregisters connected to corresponding subregisters in the status request registers.

8. A multiprocessor system as claimed in claim 7, characterized in that each attention status register is connected to an attention mask register generating an attention interrupt for the associated processor.

9. A multiprocessor system as claimed in claim 1, characterized in that the communications logic unit is directly connected to each processor via its local bus.

10. A multiprocessor system as claimed in claim 8, characterized in that the attention status registers are connected to the processors through respective OR gates.