WO1996028825A1

WO1996028825A1 - Semiconductor memory

Info

Publication number: WO1996028825A1
Application number: PCT/JP1995/000433
Authority: WO
Inventors: Kan Takeuchi; Yoshinobu Nakagome; Kazuhiko Kajigaya; Hiroshi Kawamoto
Original assignee: Hitachi, Ltd.
Priority date: 1995-03-15
Filing date: 1995-03-15
Publication date: 1996-09-19

Abstract

A low-cost, high-density DRAM in which the current for refreshing is reduced for use in a memory device or a memory card of portable appliances. The DRAM comprises a memory cell array divided into a plurality of blocks, a circuit (e.g. an error correction circuit (ECC) or a use area memory register) for detecting the state of each block, and a control circuit for varying the refresh rate. This control circuit extends the refresh interval until the ECC detects a correctable error, so as to set a most suitable refresh interval for each block and set an infinite refresh interval, i.e., no refreshing, for an unused area. As a result, the refresh rate can be automatically minimized for each block, and thus a stand-by current can be reduced to a minimum.

Description

Rui Akira

Semiconductor memory technology

The present invention relates to a semiconductor memory that consumes a small amount of current during standby, and more particularly to a semiconductor memory that has been subjected to a refresh control capable of minimizing a refresh operation. Background art

In recent years, along with the miniaturization of electronic information devices, there has been an increasing movement to drive the devices by using batteries. Compared to other memories, DRAM has the advantages of lower bit cost and relatively high speed, so if it can hold information for a long time with batteries, it will be widely used in mobile devices and memory cards. it is conceivable that. However, in order to extend the information retention time of the battery to a level that can be substantially regarded as a non-volatile memory, for example, about one year, it is necessary to suppress the current consumption due to the refresh operation.

Now, in a dynamic 'random'access' memory (DRAM), binary information is stored by holding a high-level or low-level potential in a capacitor. The high-level potential gradually drops due to the leakage current if left untouched. To maintain the information in the DRAM, it is necessary to periodically rewrite the information even when not in use (hereinafter, refresh operation). . FIG. 16 shows a method of controlling a refresh operation during standby in a conventional DRAM. During standby, a refresh clock is supplied to the self-refresh control circuit at regular intervals. Clocks can be provided externally or automatically generated internally. You. When the clock is applied, the refresh operation is sequentially performed on all the memory cells. The cycle of the clock is set within a range where the information stored in the memory cell is not lost due to the leak current. When a clock is provided externally, the clock cycle is given by specifications. When a clock is generated internally, a fixed period is generated using, for example, a ring oscillator.

Further, Japanese Patent Application Laid-Open No. S64-32489 discloses a semiconductor memory in which the refresh cycle is controlled by error detection of an error correction circuit to reduce power consumption. Disclosure of the invention

However, the conventional DRAM has a problem that the information retention time of the battery is only a few weeks. In other words, to reduce the current consumption during standby, for example, it is necessary to extend the refresh interval as much as possible, but the interval between refresh operations must be determined according to the memory cell with the largest leak current. Since the leakage current of a memory cell varies widely within a chip, the refresh interval must be set with a large margin for the average leakage current. Reducing the margin here creates another problem: a large number of defective chips and an increase in bit cost. For these reasons, it has been difficult to reduce the refresh interval beyond the current level and further reduce the current consumption during standby. Also, as the integration of DRAM increases, the number of cases where all memory cells in a chip are used decreases. In such a case, it is useless to perform the refresh operation on the unused memory cells. This unnecessary increase in current consumption is particularly important with higher integration of DRAM. Attention was not paid to becoming noticeable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method capable of minimizing a current consumption required for a refresh operation for a semiconductor chip, and to provide a semiconductor memory suitable for a storage device of a portable electronic device 電 a memory card. It is in.

To achieve the above object, in the DRAM of the present invention, a cell array is divided into a plurality of blocks, and a circuit for detecting a state of the cell array for each block and a circuit for variably controlling a refresh cycle are provided. (Fig. 1). The state detection circuit is, for example, an error correction circuit (ECC circuit) that can correct a 1-bit error (Single Error Correction; SEC). The refresh cycle is gradually extended, and when the ECC circuit detects a 1-bit error, the self-refresh circuit is controlled so that the refresh cycle at that point or a shorter cycle is performed. Alternatively, the state detection circuit is a register that stores a use area of the DRAM cell array, while the control circuit sets the refresh cycle of the unused area to infinity based on information from the state detection circuit. (Ie, do not refresh).

According to the above ECC circuit and control circuit, the refresh cycle can be set to the minimum necessary according to the ability of each block of the DRAM array. Alternatively, according to the use area storage register and the control circuit, the current consumption required for one refresh can be minimized. In particular, as the degree of integration of DRAMs increases, the variation in the information retention time of memory cells within a chip increases, and the number of unused areas in a chip increases, the effect of reducing power consumption will increase. Become. That is, according to the present invention, consumption during standby A low-current DRAM can be realized, and a memory suitable for a storage device S ゃ memory card for portable electronic devices that backs up with a battery during standby can be obtained. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a control system of a refresh operation in the semiconductor memory of the present invention.

Figure 2 shows an automatic refresh cycle optimization method using an ECC circuit.

FIG. 3 shows a configuration similar to that of FIG. 2, in which an ECC circuit is shared between blocks.

FIG. 4 is a diagram showing a method of determining a refresh cycle at the time of testing in the semiconductor memories of FIGS. 2 and 3.

FIG. 5 is a more specific circuit configuration example of FIG.

FIG. 6 is a more specific circuit configuration example of FIG.

FIG. 7 is an operation waveform showing a change in the refresh cycle in FIG.

FIG. 8 is an operation waveform showing the fixation of the refresh cycle in FIG.

Fig. 9 is a diagram showing an automatic optimization method of the internal power supply voltage using the ECC circuit.

FIG. 10 is a specific example of the internal power supply compression generation circuit of FIG.

FIG. 11 is a diagram showing a control method of a refresh area by a use area storage register.

FIG. 12 is a more specific circuit configuration example of FIG.

FIG. 13 is another example of the used area storage register of FIG. FIG. 14 is an example of a system configuration for realizing the method of FIG.

FIG. 15 is a diagram showing a control method of a low pressure supply area by a use area storage register.

FIG. 16 shows a control system for refresh operation in a conventional semiconductor memory. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in more detail with reference to examples.

FIG. 1 is an embodiment showing a basic configuration of a refresh control method in a DRAM of the present invention. The DRAM cell array is divided into multiple blocks, and the refresh cycle is set to an optimal value for each block. Each block is provided with a state detection circuit for detecting the state of the DRAM cell array, and a refresh clock generation circuit for variably controlling a refresh cycle based on information from the state detection circuit. This control circuit controls a self-refresh control system in a normal DRAM. In FIG. 1, the ordinary refresh control system comprises a self-refresh circuit for generating an address for performing a refresh, and a multiplexer for selecting one of a refresh address and an external input address and sending the selected address to a row decoder. The self-refresh start signal SRS i (i = 1, 2, 3, 3,...) From the variable-period refresh clock generation circuit of each block is sent to the self-refresh circuit, and corresponds to the block to be refreshed. Set the upper address register and control the oscillator that counts up the lower address. The state detection circuit is, for example, an ECC circuit that corrects a 1-bit error. The refresh clock generation circuit gradually extends the refresh cycle at the time of self-refresh, and The period at which the circuit detects a 1-bit error, or a shorter period, is defined as the subsequent refresh period. Alternatively, the state detection circuit is a use area storage register of the DRAM cell array, and the refresh clock generation circuit refreshes only the use area of the cell array based on the information from the register and uses the unused area. Let the refresh period of be infinite. That is, no refresh is performed. According to the present invention, current consumption required for refresh operation can be suppressed to the minimum necessary for each DRAM chip, and there is an effect that a semiconductor memory that is inexpensive, highly integrated, and has low current consumption during standby can be obtained. .

FIG. 2 is an embodiment of the present invention using an ECC circuit as the cell array state detection circuit in FIG. The refresh clock generation circuit gradually extends the refresh cycle at the time of self-refresh, and sets the cycle at the time when the ECC circuit detects a 1-bit error or a cycle slightly shorter than that as the subsequent refresh cycle. According to the embodiment of the present invention, each block is refreshed at the longest possible cycle in accordance with the ability of the memory cell to retain information. Therefore, the current consumption required for the refresh operation can be suppressed to the minimum necessary, so that there is an effect that a semiconductor memory with small current consumption during standby can be obtained.

FIG. 3 is an embodiment of the present invention in which the ECC circuit in FIG. 2 is shared between blocks. Although FIG. 3 shows a case where the ECC circuit is provided outside the semiconductor chip, it may be provided inside the chip. Data from each block during self-refresh is sent to the ECC circuit, and if a 1-bit error has occurred, a signal indicating the occurrence of the error is returned to the memory chip. Based on the information of the row decoder, it is possible to identify in which block the error has occurred, and to fix the refresh cycle of the block to that value, Alternatively, a period shorter than the value is set. According to the embodiment of the present invention, in addition to the effects described in the embodiment of FIG. 2, the area occupied by the ECC circuit in the chip can be reduced or eliminated, so that a highly integrated memory chip can be obtained. effective.

FIG. 4 is an embodiment of the present invention showing a method of determining a refresh cycle at the time of testing in the configuration of FIG. 2 or FIG. In the figure, CBR indicates a CAS before RAS signal. The pulse width of 81¾ is equivalent to several sets of the self-refresh cycle. In this embodiment, at the time of testing, the self-refresh operation is repeated for all the memory cells until the ECC circuit detects an error in a state where the power supply voltage is lower than that in normal use. As a result, the refresh cycle is determined by the procedure described in FIG. The cycle at this time is the minimum cycle required for the power supply voltage during the test. In other words, the power supply voltage during normal use is a value with a certain margin. In the embodiment of the present invention, the information is not destroyed even if the information holding time is deteriorated by continuing to use the DRAM chip, and the refresh cycle is set to a sufficiently long refresh cycle according to the ability of the chip. Alternatively, a sufficiently long refresh cycle is set within a range that does not cause an error even if the power supply voltage drops during normal use. The register that stores the set refresh cycle is composed of non-volatile memory so that the refresh cycle set at the time of the test is not lost even if the power is turned off. According to the embodiment of the present invention, it is possible to obtain a semiconductor memory having higher reliability and a lower current consumption during standby, taking into account such things as deterioration of a chip during normal use and a reduction in power supply voltage. There is.

Fig. 5 shows the variable-period refresh clock generation circuit in Fig. 2. 1 shows an embodiment of the present invention. Here, only one block (block 1) was extracted. The variable cycle refresh clock generation circuit 1 has a 1-bit error occurrence determination register, a refresh cycle determination shift register, and a refresh cycle generation circuit as its main components. The refresh cycle in the DRAM chip of FIG. 2 is controlled as follows. First, the self-refresh start signal SRS is sent from the refresh cycle generation circuit to the self-refresh circuit. In response to this, the self-refresh circuit sequentially generates refresh addresses by the internal counter, and performs the refresh operation of the DRAM cell array block 1. At this time, the ECC circuit outputs a 1-bit error occurrence flag EF indicating whether or not the stored information is correctly held. If the information write determination flag has changed from 0 to 1 and at least one write operation has been performed on the DRAM cell array, the above 1-bit error generation flag EF is set to the variable period refresh clock generation circuit. Sent to. Here, if the EF is in the 0 state indicating that there is no error in the stored information, the 1-bit error occurrence determination register remains in the 0 state. On the other hand, the pulse of the self-refresh start signal is delayed by a delay circuit for about the time td required for the refresh operation of the entire DRAM cell array block 1 and becomes a count-up pulse of the refresh cycle determination shift register. However, the refresh cycle determination shift register is counted up only when the 1-bit error occurrence determination register is in the 0 state and no error is detected by the ECC circuit during the above-described series of refresh operations. In response to the count-up of the shift register, the refresh cycle generation circuit outputs the next self-refresh start signal SRS at a longer interval. The next start from the self-refresh start signal generation described above _W contract 28825

9

The procedure up to signal generation is repeated until an error is detected during the refresh operation. And the refresh cycle becomes longer and longer. If the refresh cycle becomes longer than the minimum information retention time of the memory cells in block 1, the ECC circuit detects an error and the 1-bit error flag changes from 0 to 1. As a result, the 1-bit error occurrence judgment register changes from 0 to 1, and after that, regardless of the state of the 1-bit error occurrence flag, the 1 state is maintained until the power is turned off. Then, the count-up of the refresh cycle determination shift register stops. Note that as long as the refresh cycle is gradually lengthened, there is little possibility that multiple bits will fail at the same time when the ECC circuit first detects an error. This is because the information retention time of a memory cell varies greatly from cell to cell. Therefore, if the error data is corrected and rewritten by the ECC circuit of SEC that can correct a 1-bit error, no information is lost by the above refresh cycle. However, if the subsequent self-refresh operation is performed in the above-described refresh cycle, it is necessary to correct data by the ECC circuit every time the refresh is performed. Therefore, it may be possible to detect that the 1-bit error occurrence determination register has changed to 1 and count down the refresh cycle determination shift register by one. If the refresh operation is performed one cycle before the error occurs, the refresh is performed at the longest possible cycle in accordance with the ability of the memory cell to retain information. As described above, according to the embodiment of the present invention, since the consumption II current required for the refresh operation can be suppressed to the minimum necessary, there is an effect that a semiconductor memory with low standby current consumption can be obtained.

FIG. 6 shows a twisted configuration of the variable period refresh clock generation circuit of FIG. 1 is an embodiment of the present invention showing a physical circuit configuration example. The 1-bit error occurrence determination register, the refresh cycle generator that generates multiple refresh cycles, and the refresh cycle determination that selects one of the multiple cycles are shown in FIG. A shift register is provided.

The 1-bit error occurrence determination register is composed of an asymmetric flip-flop circuit. That is, one node EJ of the flip-flop circuit is connected to V ss (0 V) via a high resistance. If the 1-bit error occurrence flag EF goes high after a write operation to the DRAM cell array block 1, EJ is short-circuited to Vcc. With this configuration, when power is turned on, EJ is pulled to V ss via a high resistance, so that an imbalance occurs between the two nodes of the flip-flop, and EJ is latched at the mouth level. If the ECC circuit detects an error during the refresh operation after writing to the DRAM cell array, the EF level changes to high level, and EJ changes to high level. Here, the on-resistance of the p-channel transistor that constitutes the flip-flop circuit is designed to be several orders of magnitude smaller than the resistance value of the resistor connected to V ss, so that even if EF returns to the mouth level, EJ Is latched to a high level. In this way, the 1-bit error occurrence determination register holds the low level after the power is turned on, and holds the high level until the power is turned off after the ECC circuit detects at least one error. Can be configured. For example, if it is necessary to retain the state at the end of the test even after the power is turned off as in the embodiment of FIG. 4, the state of the 1-bit error occurrence determination register may be stored in nonvolatile memory. . Note that information writing for detecting whether at least one writing operation has been performed on the DRAM cell array block 1 is performed. For example, the flag may have the same configuration as that of the 1-bit error occurrence determination register, and may have a configuration in which a write enable signal (WE) and a row address are input instead of the EF.

The refresh cycle generation circuit shown in FIG. 6 generates a cycle of 2 n times (n = 1, 2,...) The cycle T O of the oscillation cycle. That is, each time one JK flip-flop is connected in series, its output T l, T 2, etc. has twice the period of the input. By selecting one of these periods T O, T 1, T 2,..., The refresh period can be changed widely.

The refresh cycle determination shift register in FIG. 6 is configured by connecting in series JK flip-flops in which the K input is fixed at the high level. Every time the clock CT rises, the state of F0 at the high level is sequentially propagated to the outputs F1, F2,... Of the JK flip-flop, and changes from the mouth to the high level. .. FO, F 1, F 2... And the refresh cycle generation circuit T 0, T 1, T 2,. The refresh cycle can be determined according to the position of the break between the low level and the high level of. The refresh cycle is doubled every time the clock CT rises. CT rises after a time ΔT required to refresh the DRAM cell array block 1 has elapsed from the rise of the self-refresh start signal SRS. However, if the ECC circuit detects an error during the above refresh operation and the state of the 1-bit error occurrence determination register changes, the SRS will not propagate to the CT and the refresh cycle will be fixed thereafter. In Fig. 5, a signal for generating a CT pulse is generated after a delay of T based on the SRS pulse. The signal for generating a CT pulse may be generated based on a signal from a network circuit. That is, it detects that the refresh power counter in the self-refresh circuit has counted up to the top of the block 1 and generates the above-mentioned signal for generating a CT pulse.

The operation in FIG. 6 will be described in more detail with reference to FIGS. 7 and 8. FIG. 7 shows a case where no error occurs during the refresh operation, and FIG. 8 shows a case where an error occurs.

In Fig. 7, for example, consider the change in the refresh cycle after turning on the source. First, F0, F1, and F2 of the refresh cycle determination register are at high level, low level, and low level, respectively. On the other hand, T 0, T l, and Τ 2 of the refresh cycle generation circuit generate clocks with periods of t, 2 t, and 4 t, respectively, with respect to the oscillation cycle t. Here, the logical type of F 0 and T 0 is A 0, the logical product of F 1 and T 1 is A 1, and the logical product of F 2 and T 2 is A 2. At first, since F0 is at a high level, only A0 of AO, Al, and A2 changes in synchronization with T0. RT rises in response to the rise of AO, and a short pulse is generated by AND logic of the inverted signal RB and the delay signal. This becomes the self-refresh start signal SRS, and the refresh operation of the DRAM cell array block 1 is performed. If the ECC circuit does not detect an error during this refresh operation and EF remains at low level, that is, if EJ is at low level, the refresh operation of the DRAM cell array block 1 ends. Thereafter, the SRS generates a CT pulse and the refresh cycle determination shift register is counted up. That is, F 1 becomes high level together with F 0. As a result, A 1 is synchronized with T 1. The rising cycle of RT is the cycle in which A 0 and A 1 rise at the same time. , That is, the period of A 1 (2 t). The next SRS pulse is generated in response to the next rising edge of RT whose period has changed. If no error is confirmed in the refresh operation accompanying this, the shift register is further counted up and F2 changes to high level. As a result, A2 is synchronized with T2, and the rising edge of RT is the position where A0, Al, and A2 rise simultaneously. That is, the cycle of the refresh start signal SRS generated based on the rising edge of RT matches the cycle of A2 (4t). In this way, if no error is detected during the self-refresh operation, the cycle is doubled.

FIG. 8 is an operation waveform showing that, when an error is detected during the self-refresh operation, the refresh cycle is fixed at that time. For example, as in FIG. 7, F 0 and F 1 sequentially become high level, and an error occurs in a 2 t refresh cycle.

When EF changes to a high level, EJ also changes to a high level and is then clamped to a high level. Since EJ is at the high level, the CT pulse does not rise ΔT after the rise of SRS. Therefore, F2 remains at the low level, and the refresh cycle is fixed at 2t. On the other hand, the ECC circuit corrects the error and rewrites the DRAM cell array. An ECC circuit that can detect and correct a 1-bit error, for example, is sufficient. This is because the information retention time of the DRAM cell varies, and if the refresh cycle is gradually extended as in the present invention, when the ECC circuit detects an error for the first time, only one bit error is detected. There can be. Therefore, even if the refresh cycle is extended until the ECC circuit detects an error, the data that caused the error can be detected and corrected, and no information is lost. In the configurations described in FIGS. 6 and 8, after the refresh cycle is fixed, a 1-bit error occurs every time the self-refresh operation is performed, and it is necessary to detect and correct this. Even in this case, no information will be lost, but for higher reliability, return to the previous cycle before the refresh cycle at the time when an error occurs during the self-refresh operation. What should I do? According to the embodiment of the present invention described above with reference to FIGS. 6 to 8, the refresh cycle is automatically set in accordance with the ability of the memory cell to retain information, so that the semiconductor device that consumes a small amount of current during standby is used. Memory power, 'can be realized.

As described above, the embodiments of FIGS. 2 to 8 have described the method in which the current consumption during standby can be reduced by extending the refresh cycle until an error that can be corrected occurs for each DRAM cell array block.

FIG. 9 shows an embodiment of the present invention in which the current consumption during standby and during operation is reduced by lowering the internal voltage until a correctable error occurs. In FIG. 9, only the block 1 of the plurality of blocks is extracted and shown. Refresh clock (Self-refresh start signal) When SRS is applied to the self-refresh circuit, the self-refresh circuit sequentially generates refresh addresses by an internal counter, and the refresh operation in the DRAM cell array block 1 is performed. If a stored information error is detected by the ECC circuit during a self-refresh operation after at least one write operation to the DRAM cell relay block 1, the 1-bit error flag EF is set to High level, otherwise low level. As a result, the node EJ of the 1-bit error determination register is at a low level until a 1-bit error occurs from power-on, and a 1-bit error occurs. Until the power is turned off, it is held at high level. On the other hand, the refresh clock becomes the clock signal CT of the internal voltage decision shift register after a delay of ΔT required for the refresh operation of the DRAM cell array block 1 to end. However, a CT pulse is generated when EJ of the 1-bit error occurrence determination shift register is at low level and no 1-bit error has occurred at all. When the power is turned on, the internal state of the shift register changes to Fl, F2,... In sequence each time a pulse is input. I will do it. The exclusive OR logic between the adjacent nodes of F O. F 1, F 2... Is output to the internal power supply voltage generation circuit, so that one of the outputs is at a high level. As a result, the internal power supply voltage VL is generated. Here, VL decreases as the range of the high level of the nodes F 0, F 1, F 2... Of the internal voltage determination shift register increases. When the EJ of the 1-bit error occurrence determination register changes to high level, the reduction of VL due to the refresh clock stops, and thereafter, it is fixed to the internal power supply voltage at that time.

FIG. 10 shows a specific circuit example of the internal power supply voltage generation circuit in FIG. (A) is a reference voltage generation circuit EB that generates a constant reference voltage VR1 regardless of the power supply voltage, and (b) is a voltage conversion circuit TB that generates a variable voltage VR2 based on VR1. . The threshold voltage V th1 of the MOS transistor ME 1 and the threshold voltage V th2 of the MOS transistor ME 2 are designed to be different values in the EB shown in FIG. At this time, VR l = | V thl I-IV th 2 I. That is, due to the current mirror circuit, the sum I 0 of the currents flowing through ME 1 and ME 2 is twice the current I 2 flowing through ME 2. Therefore, the current flowing through ME 1 I 1 is equal to I 0. From this, focusing on ME1, the source voltage VM is IV thll + Δν, and focusing on ΜΕ2, VM is | V th2 l + AV + VR l. From the above, it can be seen that VR l = | V thl I — IV th 2 I.

FIG. 10 (b) is a circuit for generating a variable VR2 based on VR1. One of the multiple inputs from the internal voltage shift register becomes a high level, and one end of the input of the differential amplifier is connected to any one of the connection portions of the resistors connected in series. The other end of the input is connected to reference potential VR1. By the action of the p-channel MOS transistor connected to the differential amplifier and the output, the input and VR2 of the differential amplifier connected to the series resistor are stabilized at a constant potential. The more the input is connected to the Vss side, the higher the VR2, and the more the input is connected to the Vcc side, the lower the VR2. When applying the circuit shown in Fig. 10 (b) to Fig. 9, every time a CT pulse is input to the internal voltage decision shift register, the input should be connected to the side of the series resistor close to Vcc. To

According to the embodiment of the present invention described above with reference to FIGS. 9 and 10, the minimum internal voltage is set in accordance with the ability of the memory cell to retain information in each DRAM cell array block. Therefore, a semiconductor memory with low current consumption, which is suitable for a storage device of a portable device, a memory card, or the like, can be obtained. Fig. 11 shows that in a DRAM cell array block divided into a plurality of blocks, the self-refresh operation is performed only for the blocks in the used area, and the refresh cycle of the blocks in the unused area is set to infinity. This is one embodiment of the present invention. To achieve this A register for storing a used area is provided, and based on the information in this register, an upper address register of a self-refresh circuit for designating a block for performing a self-refresh operation is controlled. According to the embodiment of the present invention, the refresh operation is performed only in the area where the information needs to be held, so that the current consumption during standby can be minimized.

FIG. 12 is an embodiment of the present invention showing a more specific configuration example of the configuration of FIG. When the refresh circuit outputs the refresh address by the signal CBR or the self-refresh signal Se1f, the refresh of the entire memory cell array is normally performed. However, in this embodiment, in a DRAM cell array block divided into a plurality of blocks, a block to which writing has been performed is detected, and a refresh operation is performed only on that block. That is, the used area storage register is controlled by the signal WE designating the write operation and the row address. In Figure 12, the block is divided into four, and each block is selected by a part of the address, for example, A0 and A1. For each block, a use area storage register is provided for determining whether or not a write operation has been performed, and storing the information. The used area storage register is composed of four flip-flop circuits corresponding to each block. When the power is turned on, all the nodes on the side of the flip-flop circuit to which a high resistance is connected to V ss are at a low level due to the action of the high resistance. In this state, since the address data does not reach the DRAM array block, no operation is performed, including the refresh operation. If DRAM write-lock signal is accessed while write enable signal WE is at high level, the flip-flop circuit of the used area storage register corresponding to the above block is reset. Turn over. As a result, the address can reach the above-mentioned block, and the refresh operation as well as the information writing and reading operation to the above-mentioned block is performed. The block may be a DRAM sub-array or a single word line. As described above, according to the embodiment of the present invention, the write operation is performed, and therefore, the refresh operation is performed only in the area where the information needs to be held. FIG. 13 shows an embodiment of the present invention in which the use area storage register in FIG. 12 is configured to be reset by a reset signal. In Fig. 12, when the power is turned on, the used area storage register is automatically reset. On the other hand, in FIG. 13, the reset can be performed by setting the reset signal line Reset to a high level. (A) shows a configuration that clears all registers at once, and (b) shows a configuration that clears each register corresponding to each block. According to the embodiment of the present invention, the refresh area can be newly specified when the used area of the memory is completely changed, for example, when a certain work is completed on a personal computer and then another work is started. . In other words, the refresh area can be specified more flexibly, and the current consumption during standby can be reduced. Furthermore, in the configuration of (b), the refresh area can be specified more finely by the control of the processor, and the current consumption during standby can be greatly reduced. FIG. 14 is an embodiment of the present invention showing a system configuration for controlling the used area storage register in FIG. 13 (b). In the DRAM array in the memory chip, an area for storing the used area is secured in addition to the normally used area. From the processor side, data on the used area Evening is sent at the time of new use or at the end of use, and this information is stored in the above use area storage area. The self-refresh operation in the above-mentioned memory chip is performed according to steps 1 to 4 shown in FIG. Ie

First, the memory cells in the used area storage area are refreshed. The information of this memory cell is read out to the block reset signal generation circuit, and the circuit resets the reset signal R eseti (i = 1, 2, 3, 4) are generated. When the refresh operation is continuously performed in the normal use area, the refresh operation is performed only for the used block by the control shown in FIG. 12, for example. According to the embodiment of the present invention, it is possible to obtain a system capable of variably controlling the area of the refresh operation only by changing the software.

Fig. 15 shows an example of a DRAM cell array block

This is an embodiment of the present invention in which a block to which writing has been performed is detected, and the power of an unused block is turned off. According to the same operation as in FIG. 12, the power supply voltage Vcc does not reach the DRAM array block until the write operation is performed after the power is turned on. When a write operation to a block (for example, 1) starts (when WE is high and the address specifies block 1), the flip-flop corresponding to block 1 of the used area storage register is inverted, and Vcc is supplied to block 1. Become so. However, since it takes time for the voltage to stabilize after the supply of Vcc to block 1 starts, an AAS 1 pulse is generated to indicate that block 1 is in the rising state. During this time, for example, a write operation to block 1 is suspended. According to the embodiment of the present invention, since only the used blocks are activated, it is possible to reduce current consumption during operation and standby. As described above, according to the present invention, the current consumption required for the refresh operation in the DRAM can be minimized, so that a semiconductor memory suitable for a storage device of a portable device ゃ a memory card can be provided. can get.

Claims

The scope of the claims

1. In a semiconductor memory having a dynamic 'random' access memory, each block has a plurality of blocks each having a plurality of memory cells and a refresh cycle of each block of the plurality of blocks. A semiconductor memory comprising:

2. The semiconductor memory according to claim 1, wherein an error correction circuit for correcting an error in storage information of the plurality of memory cells of the plurality of blocks, and wherein the error correction circuit corrects an error in the storage information. And a signal line indicating that there is a signal, wherein the control circuit sets a refresh cycle of each block of the plurality of blocks in response to a signal from the signal line. .

3. The semiconductor memory according to claim 2, wherein a voltage lower than a standard power supply voltage is connected to a power supply terminal of the semiconductor memory, and a refresh cycle of each block of the plurality of blocks is set. Specialized semiconductor memory.

4. The semiconductor memory according to claim 1, further comprising: a register for storing a block of the plurality of blocks that needs to hold storage information, wherein the control circuit includes: A semiconductor memory, which executes refresh of a block that needs to hold the stored information in response to the information.

5. The semiconductor memory according to claim 4, wherein the control circuit sets a refresh cycle of a block which does not need to hold stored information among the plurality of blocks to infinity. memory.

6. The semiconductor memory according to claim 4, wherein the register stores a block to which storage information has been written out of the plurality of blocks. A semiconductor memory characterized by remembering.

7. The semiconductor memory according to claim 4, wherein said register comprises a plurality of memory cells provided in addition to said plurality of blocks.

8. In a semiconductor memory having a dynamic random access memory, each block has a plurality of blocks having a plurality of memory cells, and an error in information stored in the plurality of memory cells of the plurality of blocks has been corrected. An error correction circuit to correct, a signal line indicating that the error correction circuit has an error in the storage information, and a refresh cycle of each block of the plurality of blocks in response to a signal from the signal line. And a control circuit for setting the voltage.

9. In a semiconductor memory having dynamic random access memory, each block stores a plurality of blocks having a plurality of memory cells and a block in which storage information is written among the plurality of blocks. A semiconductor memory, comprising: a register; and a control circuit that specifies a block that supplies a power pack among the plurality of blocks in response to information in the register.