WO1996021296A1

WO1996021296A1 - Data recovery circuit

Info

Publication number: WO1996021296A1
Application number: PCT/EP1995/005078
Authority: WO
Inventors: Fernando Ortiz Saenz; Maria Del Mar Gutierrez Serratosa; José Luis MERINO GONZALEZ; Rafael Sanz Gomez
Original assignee: Alcatel Standard Electrica S.A.; Alcatel N.V.
Priority date: 1994-12-29
Filing date: 1995-12-21
Publication date: 1996-07-11
Also published as: ZA9510563B

Abstract

For obtaining the data clock (R1) in optimum phase from the incoming data signal (DAT) and the input clock signal (R2), at a frequency that is multiple of the data bit rate, by means of two digital counters (CONT1, CONT2) that divide the frequency of the input clock signal (R2). This circuit shortens or lengthens certain cycles of the data clock (R1) by an amount significantly less than their duration, as a function of the relative positions of the data signal (DAT) transitions and of the active edges of the recovered data clock (R1), so that these edges occur at the optimum sampling instant of the incoming data signal (DAT). To perform this operation, the first digital counter (CONT 1) carries out, in these periods, a count that is one unit less or more, respectively, than that which is usually performed.

Description

DATA RECOVERY CIRCUIT OBIECT OF THE INVENTION

This invention concerns a digital circuit for the sampling and recovery of binary digital data and the extraction of its data clock of which the active edge samples the data in question at the optimum instant. This permits a minimum probability of error in the recovered data sequence.

This circuit permits binary data sequences to be obtained with minimum probability of error from a comparator the logical values of which, "1" or "0", are being produced continuously, that is, without they being sampled by any data clock. The invention also permits the recovery of this data clock in a very short interval of time, meaning that it can be used in burst data systems with headers of reduced size. BACKGROUND OF THE INVENTION

There are various data circuits available that permit recovery of the optimum data clock in burst communications systems and, consequently, of the data, with a minimum probability of error. For this, some of them are based on digital phase-locking techniques like, for example, the integrated circuit SN54LS297 of Texas Instruments, as explained on pages 3-783 to 3-788 of their catalogue "The TTL Data Book, Volume I, Standard TTL, Low Power Schottky, Schottky", published in 1989.

Basically this circuit (termed DPLL, Digital Phase-Locked Loop), as shown in figure 2 of the publication mentioned, receives an input clock signal that is a multiple of the loop centre frequency and which corresponds to the data clock, with optimum phase, that it is desired to recover This input clock signal is applied to a digital counter that divides its frequency by N and which is sent to a phase detector which also receives the incoming binary data signal.

Once the loop is closed, this circuit permits a data clock signal to be obtained with a frequency which is locked to that of the incoming data in order to track the relative shifts in frequency and /or phase between the input clock and the data clock.

This circuit, however, has as its principal drawback the requirement for a second clock signal that is sent to a second divider, of the up-down type, the outputs of which indicate when the data clock edge has to be brought forward or delayed. In addition, in the case when the input data to this circuit do not have a width equal to the clock cycle, a shift would take place in the recovered clock phase towards an instant at which the error probability is not optimum. CHARACTERISATION OF THE INVENTION The above drawbacks are resolved by the circuit according to the invention which receives an input data signal and an input clock signal, at a frequency that is a multiple of the data bit rate, from which it recovers its own data clock by means of two digital counters that divide the frequency of the input clock signal in such a way that certain data clock cycles are shortened or lengthened by an amount significantly less than their duration, depending on the relative positions of the data signal transitions and of the active edges of the recovered data clock pulses.

This amount by which the data clock cycle is shortened or lengthened is one cycle of the input clock signal. To carry out this operation, the first digital counter performs, in the cycles in question, a counting process that is one unit less or more, respectively, than that which it normally does when there is no need to shorten or lengthen any cycle of the data clock.

In this way the circuit of the invention permits, in a simple manner, a data clock to be obtained the active edges of which are shifted in time in accordance with the transitions of the input signal data with the object of these occurring at the optimum instant and absorbing the relative variations in frequency between the data clock signal and the actual input data signal. BRIEF FOOTNOTES TO THE FIGURES Below a fuller explanation of the invention is given based on the description of an implementation of it in accordance with the attached figures, in which:

- figure 1 shows a functional block diagram of the data recovery circuit according to the invention, - figure 2 shows the implementation of one of the metering devices of figure 1,

- figure 3 shows the implementation of the second counter of figure 1, and

- figure 4 shows the clock diagram for the locking process of the recovered data clock starting from the input data. DESCRIPTION OF A PREFERRED IMPLEMENTATION

In order to achieve correct recovery of a sequence of binary digital data, at a given rate of 1,152 kbit/s, it is first necessary to recover their clock, such that the active edges of the clock coincide with the optimum instant for sampling, that is when the error probability is least.

By the very nature of the signal, this happens at the centre of the data bit pulse since, due to the effects of noise and other sources of degradation (inter-symbol interference, etc.), the data transitions, when coming from a level comparator, are shifted with respect to the theoretical instant at which they should occur. For this reason, if the data are read at instants close to their extremities, there is a greater probability of obtainig an erroneous reading than if the reading is taken at a central point.

The block diagram of figure 1 shows, functionally, the implementation of a data recovery device in accordance with this invention. In this case the starting point is an input clock signal R2 which is working 18 times faster than the incoming data rate, that is at 20,736 MHz. This clock signal is applied to a first digital counter CONTl and, from here, to a second digital counter CONT2 which, by dividing its frequency by 9 and by 2 respectively, obtains the frequency of the data clock Rl but with a shift (due to tolerances) with respect to that which the input data DAT originates, which would prevent them from being correctly recovered.

For this reason, the first counter CONTl, which is a modulus 9 digital counter, also includes the facility of counting to 8 or to 10, depending on certain input control signals F and S for going faster or slower. Thus, when the fast control signal F is high, the counter is modulus 8, and when the slow control signal S is high, then the counter works as modulus 10 (in any other situation the counter will be modulus 9).

This means that if in a half-cycle of the output clock, which corresponds to the recovered data clock Rl, ah 8 count is carried out, this half-cycle will have been shortened by a nineth part of its normal duration, consequently the next clock pulse edge (and all those following), will have been brought forward by this same amount. Likewise, if the count is to 10, in one half-cycle this clock pulse edge will have been delayed by the same amount. The output signal from this first counter CONTl is also used to provide feedback for its zero resetting input R, whereby it starts a new count corresponding to the next half-cycle of the data clock Rl each time that a value of 8, 9 or 10 is reached, depending on the status of the fast F or slow S control signals, as explained above. As a consequence of this, whenever these control signals are not high, this first counter CONTl generates a narrow pulse every nine cycles of the input clock signal R2. The second counter CONT2 receives these pulses and changes its output level each time that one of them arrives; in this way a square wave signal is obtained with a frequency which is half of that at the output from the first counter; in other words, its fequency is 1/18 of the frequency of the input clock signal R2 in the absence of active fast F or slow S control signals.

The timing adjustments of the data clock Rl permit the phase of this clock to be adapted to the transitions of the input data DAT, so that its active edges are produced, with respect to the data cycles, at the instant considered optimum (i.e. in the centre of the data pulse).

To obtain the fast F and slow S control signals, the following procedure is employed:

In a first metering circuit MED1 a first count Ml is made of the number of cycles of the input clock signal R2 that occur from the occurrence of a transition in the input data DAT until the first rising edge of the data clock Rl. In a second metering circuit MED2, a second count M2 is made of the number of cycles of input clock signal R2 that occur from the arrival of a rising edge of the data clock Rl until there is a new transition of the input data DAT. Depending on these two measurements Ml and M2, a decoder DEC generates the fast F or slow S control signals that are applied to the first counter CONTl.

The criteria employed to decide whether the fast F and slow S control signals become high (active) are explained below.

The fast F control signal is high when any one of the following circumstances arise:

- the distance between the rising edge of the data clock Rl and the transition of the data signal DAT is less than half a cycle of data clock Rl; that is, the first count Ml is less than 9,

- the transition of the data signal DAT and the clock pulse rising edge coincide and there has been no clock pulse rising edge within the previous data element.

The slow S control signal is high when any one of the following circumstances arise:

- the distance between the transition of the data signal DAT and the rising edge of the data clock Rl is less than half a cycle of data clock Rl; that is, the second count M2 is less than 9,

- the transition of the data signal DAT and the rising edge of the data clock Rl coincide and there has been no transition of the data signal DAT from the time of the last rising edge of the data clock Rl. These fast F and slow S control signals can be inhibited by means of an enabling control signal EN to permit or not the phase adapting process of the obtained data clock Rl.

Figure 2 shows in greater detail the implementation of each of the metering devices MED1, MED2 employed in the invention. First there is an edge detector formed by a D-type bistable and an OR-exclusive gate. This edge detector receives the input clock signal R2 and the data signal DAT and produces a pulse equal in width to that of the input clock signal R2 each time that there is a transition in the data signal DAT. This pulse serves to initiate counting in a digital counter CONT. The edge of the signal of the data clock Rl is used to stop this counter, thus the value that it will have reached between the two instants of start and stop determines the time elapsed between the two edges expressed in terms of number of cycles of input clock signal R2.

As has been mentioned, for the first metering device MED1, the initiating signal I is generated from the transitions of the data signal DAT, and the stop signal P is the active edge of data clock Rl, while, for the second metering device MED2, the opposite is the case: that is, the initiating signal I is the active edge of data clock Rl and the stop signal P is obtained from the transition of the data signal DAT. Depending on the values of Ml and M2 obtained from the preceding measurements, the decoder DEC, which is a logical combinational block, generates the fast F and slow S control signals, the truth tables of which respect the criteria indicated earlier.

Figure 3 shows the second counter CONT2 that is formed from a D-type bistable the output signal from which inverts each time an active edge of a clock pulse is received, which is normally the signal coming from the first counter CONTl. When a pulse is missed, this gives rise to a delay of one half-cycle of data clock Rl as shall be explained below; in this way, a square wave signal is produced with a frequency that is one half of that of its input clock R3, independent of the pulse width of this clock R3.

This invention also includes an inversion-phase detector CPHD that detects whenever the obtained data clock Rl is delayed by one half-cycle with respect to the optimum clock or, in other words, the optimum instant of sampling the input data DAT coincides with the non-active (falling) edges of the data clock Rl and, moreover, this occurs during at least two consecutive bits.

To achieve this, in the absence of inversion-phase correction, the output signal from the inversion-phase detector CPHD applies to the input of an AND type logical gate a high level which permits the output of the first counter CONTl to reach the second counter CONT2. When an inversion-phase correction is made, this dete^'ctor transmits a low level to the input of the AND gate mentioned, so that one of the pulses of the output signal of the first counter CONTl is lost. In this way, the output signal of the second counter CONT2, that does not change level until it receives a new pulse, delays the new edge of its output signal, which is the recovered data clock Rl, bv one half-cvcle, which is equivalent to its phase being changed by 180°.

Figure 4 shows some of the signals that are produced in the circuit of the invention, in comparison with the input clock signal R2. The signals a and b of this figure show the clock diagrams of the output of the first counter CONTl and of the second counter CONT2, respectively, for the case in which no modification is made to the data clock Rl recovered in this way- Notice that both half-cycles (high and low) have a duration of nine input clock signal R2 pulses. In this situation, the input data DAT, which, moreover, do not always have the same width due to the effects mentioned above, have their transitions very close to the active edges (rising in this case) of the clock; this leads to a much greater error probability than when the clock active edges occur in the centre of the data pulse. In accordance with the invention, the signal c of this figure shows how in one of the half-cycles, corresponding to the output from the first counter CONTl, the latter only counts 8 cycles of the input clock signal R2 so that the duration of each cycle of the output clock Rl is one cycle of the input clock signal R2 shorter (that is, 17 pulses of input clock signal R2). For this to happen, the fast F control signal, coming from the decoder DEC, adopts the high level as a result of detecting one of the situations mentioned earlier. This means that the rising edge is gradually brought forward until it occupies the central section of the input data DAT as indicated by clock Rl of figure 4. Once this has been achieved, the fast control signal F takes the low level and the count of the first counter CONTl becomes 9.

A similar situation would arise if the signal that is active is the slow control signal S, but this time the first counter CONTl would perform a count to 10, thereby delaying the appearance of the next clock edge by one cycle of the input clock signal R2.

Claims

1.- DATA RECOVERY CIRCUIT which receives a data signal (DAT) and an input clock signal (R2), at a frequency being a multiple of the data bit rate, from which it recovers its own data clock (Rl) by means of two digital counters (CONTl, CONT2) which divide the frequency of the input clock signal (R2), characterised in that it shortens or lengthens a cycle of the data clock (Rl) in an amount significantly less than its duration as a function of the relative positions of the transitions of the data signal (DAT) and of the edges of the pulses of the recovered data clock (Rl).

2.- CIRCUIT according to claim 1, characterised in that the amount by which a cycle of the data clock (Rl) is shortened or lengthened is one cycle of the input clock signal (R2) .

3.- CIRCUIT according to claim 1, characterised in that the data clock (Rl) is shortened when the distance from the active edge of the data clock (Rl) to a transition of the data signal (DAT) is less than one half of the cycle of the data clock (Rl), and it is lengthened when the distance from a transition of the data signal (DAT) to the active edge of the data clock (Rl) is also less than one half of the cycle of the data clock (Rl).

4.- CIRCUIT according to claim 3, characterised in that the separations in time between the transitions of the data signal (DAT) and the edges of the data clock (Rl) signal, are counted in number of cycles of input clock signal (R2).

5.- CIRCUIT according to claim 2, characterised in that in order to shorten or lengthen the cycle of the data clock (Rl), the first digital counter (CONTl) performs a count that is one unit less or more, respectively, than that which it normally does.

6.- CIRCUIT according to claim 3, characterised in that the cycle of the data clock (Rl) is also shortened when a transition of the data signal (DAT) and the active edge of the data clock (Rl) occur simultaneously and, in addition, there has been no other active edge of the data clock (Rl) during the previous data pulse.

7.- CIRCUIT according to claim 3, characterised in that the cycle of the data clock (Rl) is also lengthened when a transition of the data signal (DAT) and an active edge of the data clock (Rl) occur simultaneously and there has been no other transition of the data signal (DAT) since the last active edge of the data clock (Rl).

8.- CIRCUIT according to claim 1, characterised in that in addition there is a phase change of 180° in the data clock (Rl) signal when in two data pulses there occur only non-active edges of the data clock (Rl) and between these there is no other data pulse with an active edge of the data clock (Rl).