WO1996017505A1 - Method, flip-chip module, and communicator for providing three-dimensional package - Google Patents

Method, flip-chip module, and communicator for providing three-dimensional package Download PDF

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Publication number
WO1996017505A1
WO1996017505A1 PCT/US1995/012130 US9512130W WO9617505A1 WO 1996017505 A1 WO1996017505 A1 WO 1996017505A1 US 9512130 W US9512130 W US 9512130W WO 9617505 A1 WO9617505 A1 WO 9617505A1
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WIPO (PCT)
Prior art keywords
integrated circuit
mounting unit
flip
stacked
unit
Prior art date
Application number
PCT/US1995/012130
Other languages
French (fr)
Inventor
Michael Edward Thomas
James Oscar Tomaszewski
Cathryn Elizabeth Goodman
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to AU37229/95A priority Critical patent/AU3722995A/en
Publication of WO1996017505A1 publication Critical patent/WO1996017505A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/023—Stackable modules
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/01073—Tantalum [Ta]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/19042—Component type being an inductor

Definitions

  • the present invention relates generally to hybrid integrated circuit technology, and more particularly to flip chip bonding.
  • Standard hybrid and multichip module, MCM products are assembled by placing components in a single layer on a substrate that provides interconnections.
  • the minimum thickness of the module is limited by a discrete part such as a tantalum capacitor, a multilayer ceramic capacitor, or a discrete inductor.
  • IC integrated circuit
  • Stacking integrated circuits or die in a three- dimensional, 3-D, configuration can significantly reduce the surface area required by the hybrid.
  • FIG. 1 is a flow diagram of steps for implementing a method for packaging flip-chip bonded integrated circuits in accordance with the present invention.
  • FIG. 2 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises two integrated circuits and a mounting unit, in accordance with the present invention.
  • FIG. 3 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises an integrated circuit and two mounting units, in accordance with the present invention.
  • FIG. 4 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises a memory unit, a microcontroller, and a mounting unit, in accordance with the present invention.
  • FIG. 5 is a diagram of a communicator having a stacked module for packaging flip-chip bonded integrated circuits, wherein the communicator is a radio, in accordance with the present invention.
  • FIG. 6 is a diagram of a communicator having a stacked module for packaging flip-chip bonded integrated circuits, wherein the communicator is a computer, in accordance with the present invention.
  • the present invention provides a method, a flip-chip stacked module, and a communicator for packaging flip-chip bonded integrated circuits.
  • a first integrated circuit is flip-chip bonded to a surface of a mounting unit.
  • a second integrated circuit is mounted on the first integrated circuit using an adhesive and is wire bonded to the surface of the mounting unit. This provides a high density packaging of integrated circuits that utilizes standard equipment and any off-the-shelf die without wafer level processing.
  • FIG. 1 numeral 100, is a flow diagram of steps for implementing a method for packaging flip-chip bonded integrated circuits in accordance with the present invention.
  • a top side of a first integrated circuit is flip-chip bonded to a first mounting unit (102).
  • the top side of an integrated circuit is the side which contains a plurality of conductive pads.
  • a stacked unit is attached, using an adhesive, to a first bottom side of the first integrated circuit (104) and is wire bonded to the first mounting unit to achieve a high density packaging (106).
  • the mounting unit may be a ceramic substrate or a printed circuit board.
  • the adhesive may be a non-conductive epoxy or a conductive epoxy. If the conductive epoxy is used, a ground strap may connect the conductive epoxy to the first mounting unit.
  • the stacked unit is a second mounting unit.
  • the second mounting unit may provide a second mounting surface for additional flip-chip mounted and standard mounted integrated circuits.
  • the stacked unit may be a second integrated circuit.
  • FIG. 2 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises two integrated circuits, ICs, (204 and 206) and a mounting unit (202), in accordance with the present invention.
  • a ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive.
  • the first and second integrated circuits (204 and 206) are fabricated by patterning a daisy chain aluminum path on 20 mil thick silicon.
  • the first mounting unit (202) is a 10 mil alumina substrate patterned with chrome/ copper/ nickel/ gold.
  • the 3-D stacked module (200) is assembled by attaching the first integrated circuit (204) to the substrate (202) with a flip-chip bond (208), epoxy bonding (210) a second integrated circuit (206) to the first integrated circuit (204), and attaching a wire bond (212) from the second integrated circuit (206) to the substrate (202).
  • the integrity of the connections in stacked module is verified by electrically testing the resistance of the daisy chain path. Once verified, the stacked module (200) is epoxied into a hermetically sealed package.
  • Flip-chip bonding is a high density integrated circuit packaging technique. With flip-chip bonding an integrated circuit is bonded top side down to a substrate using gold or solder bumps on the conductive pads. The bumps provide both electrical and mechanical interconnection. The gap between the integrated circuit and the substrate is filed with epoxy to provide additional mechanical support.
  • the flip-chip bonding may be performed using gold balls placed on the substrate pads and on the IC pads by a Hughes automatic wire bonder and thermocompression flip-chip bonding using a modified Kullicke and Soffa 578 bonder.
  • the gold balls may be made with 1 mil gold wire on a Hughes automatic wire bonder. Gold balls measuring 3 to 4 mils in diameter are used.
  • the Kullicke and Soffa 578 bonder performs thermocompression bonding by allowing for manual alignment of the integrated circuit to the substrate and then providing controlled force and temperature.
  • FIG. 3 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises an integrated circuit (204) and two mounting units (202 and 302), in accordance with the present invention.
  • the first integrated circuit (204) would be attached to the first mounting unit (202) by a flip-chip bond (208).
  • the first mounting unit (202) could be a ceramic or laminated printed circuit board material.
  • a second mounting unit (302) would then be bonded using adhesive (210) to the back of the first integrated circuit.
  • Wire bond (21 ) would make the electrical connection from the second mounting unit (302) to the first mounting unit (202).
  • a ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive.
  • stacking may continue by adding a second integrated circuit that is standard mounted or flip-chip mounted.
  • a third mounting unit may be attached to a flip- chip mounted second integrated circuit.
  • the pattern of alternating flip-chip bonded integrated circuits and mounting units may continue as long as there is an unused space above the stacked module.
  • FIG. 4, numeral 400 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises a memory unit (402), a microcontroller (404), and a mounting unit (202), in accordance with the present invention.
  • the memory unit (402) would be attached to the first mounting unit (202) by a flip-chip bond (208).
  • the first mounting unit (202) could be a ceramic or laminated printed circuit board material.
  • a microcontroller (404) would then be bonded using adhesive (210) to the back of the memory unit. Wire bonds (212) would make the electrical connection from the microcontroller (404) active area to the first mounting unit (202).
  • a ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive.
  • An example 3-D stacked module (400) comprises a 128K x 8 EEPROM IC as the memory unit (402), a gold-ball thermocompression flip-chip bond (208), an MCM-D alumina/polyimide substrate as the first mounting unit (202), and a Motorola MC68HC71 1 P2 microcontroller epoxy bonded on top as the microcontroller (404). Since the EEPROM manufacturer recommends that the backside be grounded, a silver-filled conductive adhesive (210) is used to bond a nickel-plated copper ribbon as a ground strap (214) between the stacked chips. The conductive adhesive (210) is also used to bond the ribbon to the substrate.
  • the substrate (202) which is fabricated by MIC Technology Corporation, has two metallization layers and three polyimide layers deposited on 10 mil alumina.
  • FIG. 5, numeral 500 is a diagram of a communicator having a stacked module (506) for packaging flip-chip bonded integrated circuits, wherein the communicator is a radio (502), in accordance with the present invention.
  • the stacked module (506) reduces the surface area required to package two or more integrated circuits and hence it reduces the size of the radio (502). This high density packaging approach is desirable since the size of a radio communicator of this type is an important customer satisfaction feature.
  • FIG. 6, numeral 600 is a diagram of a communicator having a stacked module (606) for packaging flip-chip bonded integrated circuits, wherein the communicator is a computer (602), in accordance with the present invention.
  • the stacked module reduces the surface area required to package two or more integrated circuits and hence it reduces the size of the computer (602). This high density packaging approach is desirable since the size of a computer, particularly laptop or portable types, is an important customer satisfaction feature.
  • Standard flip-chip and wire bonding assembly techniques can be combined to utilize space more effectively in standard hybrid and multichip module (MCM) products.
  • MCM multichip module
  • This approach can also be used wherever there is a carrier used. For example, it could be used in the ball grid array overmolded pad array carrier, OMPAC, by flipping one die onto the OMPAC substrate and then wire bonding a second die on its back. This technique could be used to provide a single OMPAC with either a microcontroller with a large memory device or twice the memory capability.
  • the present invention provides a method, a flip-chip stacked module, and a communicator for packaging flip-chip bonded integrated circuits.
  • a first integrated circuit is flip-chip bonded to a surface of a mounting unit.
  • a second integrated circuit is mounted on the first integrated circuit using an adhesive and is wire bonded to the surface of the mounting unit. This provides a high density packaging of integrated circuits that utilizes standard equipment and any off-the-shelf die without wafer level processing.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A method (100), stacked module (200, 300 and 400), and communicator (500 and 600) are provided for packaging flip-chip bonded integrated circuits. A first integrated circuit is flip-chip bonded to a surface of a mounting unit. A second integrated circuit is mounted on the first integrated circuit using an adhesive and is wire bonded to the surface of the mounting unit.

Description

METHOD, FLIP-CHIP MODULE, AND COMMUNICATOR FOR PROVIDING THREE- DIMENSIONAL PACKAGE
Field of the Invention
The present invention relates generally to hybrid integrated circuit technology, and more particularly to flip chip bonding.
Background of the Invention
Standard hybrid and multichip module, MCM, products are assembled by placing components in a single layer on a substrate that provides interconnections. In a typical hybrid, the minimum thickness of the module is limited by a discrete part such as a tantalum capacitor, a multilayer ceramic capacitor, or a discrete inductor. Hence, the volume above an integrated circuit, IC, is unused space. Stacking integrated circuits or die in a three- dimensional, 3-D, configuration can significantly reduce the surface area required by the hybrid.
Several 3-D approaches have been presented in the literature. Two of the most widely known approaches were developed separately by Texas Instruments Inc. and Irvine Sensors Corp. The Texas Instruments approach has been used to assemble a 1.2 Gbit solid-state recorder using stacks of static random access memory, SRAM, chips. In this approach, die are received from the vendor in wafer form and the I/O are rerouted and bumped for attachment to tape automated bonding, TAB, tape. The bumped die are then diced and mounted on TAB frames. After testing, the good die are excised from the frame and laminated in groups of eight to form a 3-D stack. The stacks are connected to a silicon substrate with solder. The approach developed by Irvine Sensors is also designed for stacks of memory ICs. Dynamic random access memory, DRAM, chips and SRAM chips have successfully been stacked in stacks ranging from four to one hundred chips. This process also involves wafer modification for interconnects and lamination. The stacks are polished to produce a finished part.
Both of these approaches require that die be obtained in wafer form and are applicable only to stacks of the same die. These are significant limitations in the assembly of a telecommunications hybrid since massive memory generally is not required. Rather, stacks of two or three different die would be most beneficial. Each of the above techniques involves a significant number of process steps. This would add to both the cycle time and the cost of a hybrid circuit. In addition, these techniques would require significant capital equipment investment to a standard hybrid assembly line.
There exists, therefore, a need for a method, flip-chip stacked module, and communicator for providing three-dimensional packaging of integrated circuits, wherein the method, flip-chip stacked module, and communicator utilize standard equipment and any off-the-shelf die without wafer level processing.
Brief Description of the Drawings
FIG. 1 is a flow diagram of steps for implementing a method for packaging flip-chip bonded integrated circuits in accordance with the present invention.
FIG. 2 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises two integrated circuits and a mounting unit, in accordance with the present invention. FIG. 3 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises an integrated circuit and two mounting units, in accordance with the present invention.
FIG. 4 is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises a memory unit, a microcontroller, and a mounting unit, in accordance with the present invention.
FIG. 5 is a diagram of a communicator having a stacked module for packaging flip-chip bonded integrated circuits, wherein the communicator is a radio, in accordance with the present invention.
FIG. 6 is a diagram of a communicator having a stacked module for packaging flip-chip bonded integrated circuits, wherein the communicator is a computer, in accordance with the present invention.
Detailed Description of a Preferred Embodiment
Generally, the present invention provides a method, a flip-chip stacked module, and a communicator for packaging flip-chip bonded integrated circuits. A first integrated circuit is flip-chip bonded to a surface of a mounting unit. A second integrated circuit is mounted on the first integrated circuit using an adhesive and is wire bonded to the surface of the mounting unit. This provides a high density packaging of integrated circuits that utilizes standard equipment and any off-the-shelf die without wafer level processing.
The present invention is more fully described in FIGs. 1 - 6. FIG. 1 , numeral 100, is a flow diagram of steps for implementing a method for packaging flip-chip bonded integrated circuits in accordance with the present invention. A top side of a first integrated circuit is flip-chip bonded to a first mounting unit (102). The top side of an integrated circuit is the side which contains a plurality of conductive pads. A stacked unit is attached, using an adhesive, to a first bottom side of the first integrated circuit (104) and is wire bonded to the first mounting unit to achieve a high density packaging (106).
The mounting unit may be a ceramic substrate or a printed circuit board. The adhesive may be a non-conductive epoxy or a conductive epoxy. If the conductive epoxy is used, a ground strap may connect the conductive epoxy to the first mounting unit. In one embodiment, the stacked unit is a second mounting unit. The second mounting unit may provide a second mounting surface for additional flip-chip mounted and standard mounted integrated circuits. In another embodiment, the stacked unit may be a second integrated circuit. An example application of this technique is combining a large EEPROM memory unit with a microcontroller in the original microcontroller package.
FIG. 2, numeral 200, is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises two integrated circuits, ICs, (204 and 206) and a mounting unit (202), in accordance with the present invention. A ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive.
For testing the stacked module (200), the first and second integrated circuits (204 and 206) are fabricated by patterning a daisy chain aluminum path on 20 mil thick silicon. The first mounting unit (202) is a 10 mil alumina substrate patterned with chrome/ copper/ nickel/ gold. The 3-D stacked module (200) is assembled by attaching the first integrated circuit (204) to the substrate (202) with a flip-chip bond (208), epoxy bonding (210) a second integrated circuit (206) to the first integrated circuit (204), and attaching a wire bond (212) from the second integrated circuit (206) to the substrate (202). The integrity of the connections in stacked module is verified by electrically testing the resistance of the daisy chain path. Once verified, the stacked module (200) is epoxied into a hermetically sealed package.
Flip-chip bonding is a high density integrated circuit packaging technique. With flip-chip bonding an integrated circuit is bonded top side down to a substrate using gold or solder bumps on the conductive pads. The bumps provide both electrical and mechanical interconnection. The gap between the integrated circuit and the substrate is filed with epoxy to provide additional mechanical support.
The flip-chip bonding may be performed using gold balls placed on the substrate pads and on the IC pads by a Hughes automatic wire bonder and thermocompression flip-chip bonding using a modified Kullicke and Soffa 578 bonder. The gold balls may be made with 1 mil gold wire on a Hughes automatic wire bonder. Gold balls measuring 3 to 4 mils in diameter are used. The Kullicke and Soffa 578 bonder performs thermocompression bonding by allowing for manual alignment of the integrated circuit to the substrate and then providing controlled force and temperature.
FIG. 3, numeral 300, is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises an integrated circuit (204) and two mounting units (202 and 302), in accordance with the present invention. The first integrated circuit (204) would be attached to the first mounting unit (202) by a flip-chip bond (208). The first mounting unit (202) could be a ceramic or laminated printed circuit board material. A second mounting unit (302) would then be bonded using adhesive (210) to the back of the first integrated circuit. Wire bond (21 ) would make the electrical connection from the second mounting unit (302) to the first mounting unit (202). A ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive. Since the top layer of the stacked module (300) is a mounting unit, stacking may continue by adding a second integrated circuit that is standard mounted or flip-chip mounted. A third mounting unit may be attached to a flip- chip mounted second integrated circuit. The pattern of alternating flip-chip bonded integrated circuits and mounting units may continue as long as there is an unused space above the stacked module.
FIG. 4, numeral 400, is a diagram of a stacked module for packaging flip-chip bonded integrated circuits, wherein the stacked module comprises a memory unit (402), a microcontroller (404), and a mounting unit (202), in accordance with the present invention. The memory unit (402) would be attached to the first mounting unit (202) by a flip-chip bond (208). The first mounting unit (202) could be a ceramic or laminated printed circuit board material. A microcontroller (404) would then be bonded using adhesive (210) to the back of the memory unit. Wire bonds (212) would make the electrical connection from the microcontroller (404) active area to the first mounting unit (202). A ground strap (214) could be used if required. The use of the ground strap may require the adhesive (210) to be conductive.
An example 3-D stacked module (400) comprises a 128K x 8 EEPROM IC as the memory unit (402), a gold-ball thermocompression flip-chip bond (208), an MCM-D alumina/polyimide substrate as the first mounting unit (202), and a Motorola MC68HC71 1 P2 microcontroller epoxy bonded on top as the microcontroller (404). Since the EEPROM manufacturer recommends that the backside be grounded, a silver-filled conductive adhesive (210) is used to bond a nickel-plated copper ribbon as a ground strap (214) between the stacked chips. The conductive adhesive (210) is also used to bond the ribbon to the substrate. The substrate (202), which is fabricated by MIC Technology Corporation, has two metallization layers and three polyimide layers deposited on 10 mil alumina.
As used in this description and in the appended claims, the word communicator means any electronic device which receives an input and processes the input to provide an output. The stacked module may be used in a wide variety of communicators. FIG. 5, numeral 500, is a diagram of a communicator having a stacked module (506) for packaging flip-chip bonded integrated circuits, wherein the communicator is a radio (502), in accordance with the present invention. The stacked module (506) reduces the surface area required to package two or more integrated circuits and hence it reduces the size of the radio (502). This high density packaging approach is desirable since the size of a radio communicator of this type is an important customer satisfaction feature.
FIG. 6, numeral 600, is a diagram of a communicator having a stacked module (606) for packaging flip-chip bonded integrated circuits, wherein the communicator is a computer (602), in accordance with the present invention. The stacked module reduces the surface area required to package two or more integrated circuits and hence it reduces the size of the computer (602). This high density packaging approach is desirable since the size of a computer, particularly laptop or portable types, is an important customer satisfaction feature.
Standard flip-chip and wire bonding assembly techniques can be combined to utilize space more effectively in standard hybrid and multichip module (MCM) products. This approach can also be used wherever there is a carrier used. For example, it could be used in the ball grid array overmolded pad array carrier, OMPAC, by flipping one die onto the OMPAC substrate and then wire bonding a second die on its back. This technique could be used to provide a single OMPAC with either a microcontroller with a large memory device or twice the memory capability.
Thus, the present invention provides a method, a flip-chip stacked module, and a communicator for packaging flip-chip bonded integrated circuits. A first integrated circuit is flip-chip bonded to a surface of a mounting unit. A second integrated circuit is mounted on the first integrated circuit using an adhesive and is wire bonded to the surface of the mounting unit. This provides a high density packaging of integrated circuits that utilizes standard equipment and any off-the-shelf die without wafer level processing.
Although exemplary embodiments are described above, it will be obvious to those skilled in the art that many alterations and modifications may be made without departing from the invention. Accordingly, it is intended that all such alterations and modifications be included within the spirit and scope of the invention as defined in the appended claims.

Claims

CLAIMS We claim:
1. A method for achieving a high density packaging of a plurality of integrated circuits, wherein the plurality of integrated circuits each comprise a top side, which contains a plurality of conductive pads, and a bottom side, the method comprising the steps of:
1 A) flip-chip bonding a first top side of a first integrated circuit to a first mounting unit;
1 B) attaching, using an adhesive, a stacked unit to a first bottom side of the first integrated circuit; and
1 C) wire bonding the stacked unit to the first mounting unit to achieve a high density packaging.
2. The method of claim 1 , wherein at least one of 2A-2D: 2A) the first mounting unit is a ceramic substrate; 2B) the first mounting unit is a printed circuit board; 2C) the adhesive is non-conductive epoxy; and
2D) the stacked unit is a second mounting unit.
3. The method of claim 1 , wherein the adhesive is a conductive epoxy, and where selected, wherein a ground strap connects the conductive epoxy to the first mounting unit.
4. The method of claim 1 , wherein the stacked unit is a second integrated circuit, and where selected, wherein:
4A) the first integrated circuit is a memory unit; and 4B) the second integrated circuit is a microcontroller.
5. A stacked module for achieving a high density packaging of a plurality of integrated circuits, wherein the plurality of integrated circuits each comprise a top side, which contains a plurality of conductive pads, and a bottom side, the stacked module comprises:
5A) a first mounting unit for providing a mounting surface for flip-chip bonding to a first top side of a first integrated circuit;
5B) the first integrated circuit, coupled by a flip-chip bond to the first mounting unit, for providing a predetermined operation; and
5C) a stacked unit, coupled by an adhesive to the first integrated circuit and coupled by a wire bond to the first mounting unit, for achieving a higher density packaging.
6. The stacked module of claim 5, wherein at least one of 6A-6D: 6A) the first mounting unit is a ceramic substrate;
6B) the first mounting unit is a printed circuit board; 6C) the adhesive is non-conductive epoxy; and 6D) the stacked unit is a second mounting unit.
7. The stacked module of claim 5, wherein the adhesive is a conductive epoxy, and where selected, wherein a ground strap connects the conductive epoxy to the first mounting unit.
8. The stacked module of claim 5, wherein the stacked unit is a second integrated circuit, and where selected, wherein:
8A) the first integrated circuit is a memory unit; and 8B) the second integrated circuit is a microcontroller.
9. A communicator having a stacked module for achieving a high density packaging of a plurality of integrated circuits, wherein the plurality of integrated circuits each comprise a top side, which contains a plurality of conductive pads, and a bottom side, the stacked module comprising:
9A) a first mounting unit for providing a mounting surface for flip-chip bonding to a first top side of a first integrated circuit;
9B) the first integrated circuit, coupled by a flip-chip bond to the first mounting unit, for providing a predetermined operation; and
9C) a stacked unit, coupled by an adhesive to the first integrated circuit and coupled by a wire bond to the first mounting unit, for achieving a higher density packaging.
10. The communicator of claim 9, wherein one of: 1 OA) the communicator is a radio; and 10B) the communicator is a computer.
PCT/US1995/012130 1994-12-01 1995-09-25 Method, flip-chip module, and communicator for providing three-dimensional package WO1996017505A1 (en)

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