WO1996008870A1

WO1996008870A1 - Semiconductor device

Info

Publication number: WO1996008870A1
Application number: PCT/JP1995/001804
Authority: WO
Inventors: Tadashi Shibata; Tadahiro Ohmi; Tsutomu Nakai
Original assignee: Tadashi Shibata; Tadahiro Ohmi; Tsutomu Nakai
Priority date: 1994-09-12
Filing date: 1995-09-12
Publication date: 1996-03-21
Also published as: JP3285109B2; JPH0884062A

Abstract

A semiconductor device which can drive a large-capacitance load such as the wiring existing in a very large scale integrated circuit chip or a circuit outside the chip. In a circuit in which at least a pair of NMOS and PMOS transistors whose source electrodes are connected to each other, a bias having a higher potential than the bias given to the drain electrode of the PMOS is given to the drain electrode of the NMOS, the mutually connected source electrodes are connected to the input of a CMOS inverter, and a capacitive load is connected to the output of the CMOS inverter, the magnitude of the capacitive load is larger than the gate input capacitance of the CMOS inverter, and the gate input capacitance of the CMOS inverter is larger than the sum of the gate input capacitances of the NMOS and PMOS transistors.

Description

Description Semiconductor device

Technical field

The present invention relates to a semiconductor device, and more particularly, to a buffer circuit capable of driving a large capacitive load at high speed. Background art

Recent advances in LSI technology have been remarkable. Transistor dimensions are getting smaller and smaller, with gate lengths down to 0.1 / m. While miniaturization and high integration are progressing, circuits on the chip are becoming larger. For this reason, the wiring capacitance is large, which is a major cause of a reduction in the operation speed of the entire circuit. For example, microprocessors use a system clock to control the operation of the entire chip, which is usually supplied from a single clock generation circuit to the entire chip. In other words, the clock supply wiring is very long, and can be as large as several cm, and how to drive such a very large capacitive load on a bus line at high speed is a major problem. Furthermore, the output buffer must drive an external load that is several thousand to tens of thousands of times the basic gate, and signal delay at the output stage is a major factor in determining the overall speed of the system. ing.

Normally, in order to drive a large-capacity load, an inverter composed of a transistor with a very large gate width is used as a buffer circuit. However, increasing the gate width itself becomes a capacitive load, which requires a great deal of time to drive the buffer circuit itself, and ultimately makes high-speed driving impossible.

Therefore, an object of the present invention is to realize a buffer circuit that can drive a large-capacity load at high speed. Disclosure of the invention

The present invention relates to at least a pair of NMOSs having source electrodes connected to each other and A drain electrode of the NMOS is supplied with a bias having a higher potential than a drain electrode of the PMOS, and the mutually connected source electrodes are connected to an input of a CM0S member; In a circuit in which a capacitive load is connected to an output of a CMOS inverter, the magnitude of the capacitive load is larger than a gate input capacitance of the CMOS inverter, and a gate input capacitance of the CMOS inverter is provided. The amount is set to be larger than the sum of the respective gate input capacitances of the NMOS and PMOS. Action

In order to drive a large capacitive load at high speed, a CMOS source follower circuit was taken up and its effectiveness was verified by a SPICE simulation. As a result, in addition to the “anti-mirror effect” in which the input gate capacitance is effectively invisible, there is also a “bootstrap effect” in which the output is positively fed back to the input side via the gate capacitance. It was found that this was effective for high-speed driving. Furthermore, it was found that large-capacity loads can be driven at high speed with a small number of stages by using a buffer circuit composed of a plurality of inverters, source followers, and inverters.

Therefore, the magnitude of the capacitive load is set larger than the gate input capacitance of the CMOS inverter, and the gate input capacitance of the CMOS inverter is set to the gate input capacitance of each of the NMOS and PMOS. By setting a value larger than the sum of the above, a buffer circuit capable of driving a large-capacity load at high speed can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a CMOS source follower buffer circuit.

FIG. 2 is a circuit diagram of a CMOS source follower's buffer circuit.

FIG. 3 is a circuit diagram showing a CMOS source follower circuit, which is composed of a debris type NMOS and a PMOS.

Figure 4 is a graph showing the substrate bias effect dependence of the DC voltage transfer characteristics of a CMOS source follower circuit (debrisation threshold voltage is 1 V earth).

Figure 5 shows the output transient response when driving three types of capacitive loads in the basic The input capacitance of the CMOS source follower circuit is 50 C (j is reduced by the anti-mirror effect. The fall time of the input signal to the receiver is 20 psec.

FIG. 6 is a graph showing the dependence of the transient response of the basic chamber output on the source follower output load capacity.

FIG. 7 is a graph showing the load capacitance dependency of the transient response of the 50 CQ source follower output.

FIG. 8 is a graph showing the delay time of the CMOS source follower's buffer circuit with respect to the size m and the source follower size n when the capacitive load 100 is driven.

Figure 9 is a graph showing a transient response when driving the capacitive load 1 00 C ₀ in CMO S source follower. Inba Yu Chiwein buffer circuit diagram及Biteichi Pas ring factor 3.

FIG. 10 is a CMOS source follower buffer circuit diagram and a graph showing a transient response when a load capacitance of 600 OCQ is driven by a tapper chain of a taping factor 3.

FIG. 11 is a circuit diagram showing a third embodiment of the present invention.

(Explanation of Shingo)

1 0 1, 1 0 2 CMO Simpa 'One Night,

1 03 Source follower circuit,

1 04, 1 00 1 Capacity load,

210, 301, 1101, 1104 NMOS,

202, 302, 1102, 1105 PMOS,

3 0 3 Voltage

304 voltage V _IN ,

30 5.306 channels,

5 0 1 Basic event

5 0 2, 5 03, 90 1 Capacitive load,

5 04, 6 02, 70 1, 1002, 1003 601, 1004, 1005, 1 1 03 Inver evening,

603, 702 output load capacity,

902 CMO S Source Follower 'Nopeffer Circuit,

903.1 006 Invertachi Inn.

BEST MODE FOR CARRYING OUT THE INVENTION

(Example 1)

FIG. 1 shows a first embodiment of the present invention. Reference numeral 101 denotes, for example, a CMOS inverter, which is composed of an NMOS 201 and a PMOS 202 having the structure shown in FIG. 2 and each having the device parameters shown in Table 1. This will be called the basic imperial evening. Cjj shown in the symbol of 101 is the sum of the gate input capacitances of the NMOS and the PMOS. For example, in this example, it represents 2.6 fF. 102 is also a CMO S invert, for example, and the symbol mCjj is written in the symbol because the channel width W of the NMOS and PMOS is m times the channel width of the basic impeller (the value in Table 1). Means that Since the other parameters are the same as the basic incubator, the sum of the gate input capacitances is mC ^ (mx 2.6 fF). In other words, the impeller has a current drive power that is m times that of the basic inverter, and the input capacity is correspondingly larger.

Reference numeral 103 denotes a CMOS follower source follower circuit whose structure is shown in FIG. The combination of 103 and 102 is the semiconductor device of the present invention, which is a buffer capable of driving a large capacitive load C _L (104) at high speed with the output signal of the basic inverter having only a small current driving force. It is a circuit. The essence of the operation of this circuit lies in the 103 source follower circuit, and its operation will be described in detail below.

Figure 3 shows a circuit diagram of a CMOS source follower circuit. The circuit configuration is similar to the CMOS Inverter, except that the positions of the NMOS 301 and the PMOS 302 have been interchanged. Each transistor is of a debris-type, and _νουτ303 follows _VΙΝ304 . Voltage gain is slightly less than 1, t.

Figure 4 shows the results of the HSPICE simulation of the DC characteristics of the CMOS source follower circuit with the substrate concentration varied. Substrate concentration 2 X In the case of 10 ¹⁴ cnT ³ , the NMOS or PMOS operates within the triode region.

V () IJ end ⁼ deviation from the characteristics of ^V IN (NMOS and PMOS thresholds are IV and IV, respectively. In the region of V _1N > 4V, V _1N , 1 V PMOS becomes triode operation). This characteristic (broken line) agrees very well with the result calculated analytically without taking the substrate bias effect into account. On the other hand, when the substrate concentration is 3>: 10 ¹⁶ cnT ³ (solid line), the results do not agree with the analytical calculation results, and are greatly deviated. This is because a substrate bias effect appears strongly on a substrate of 3 × 10 ¹⁶ cm ^ϋ . For this reason, the gain of the source follower slightly decreases. However, it can be seen that the substrate bias effect of the NMOS and the PMOS cancels out and the linearity is improved.

By the way, the most remarkable thing about this circuit is that the inversion layer of each transistor, that is, the channels 305 and 306 are electrically connected to _νουτ 303, and the potential thereof follows v _1N . This means that there is no need to charge and discharge the gate capacitance. The effective input capacitance is (1 κ) c _IN . Where K is the voltage gain of the CMOS source follower circuit. Since K is negative in the inverting amplifier, the effective input capacitance increases and the operating speed decreases. This is the so-called Mira-Ichi effect. On the other hand, in the case of a source follower circuit, the effective input capacitance is extremely small because of K ^ l. This is called the "anti-mirror effect".

Next, the "anti-mirror effect" will be described. Figure 5 shows the output transient response when three capacitive loads are driven by the basic impeller 501 (see Table 1). At time 0, a pulse falling from 5 V to 0 V is input to input V at 20 psec. C ₀ in the figure indicates the input gate capacitance (2.6 fF) of the basic amplifier. Looking at the two types of output capacitive loads C ₀ (502) and 51 C _Q (503), it is natural that the C node is significantly slower than the A node rising. You can see that there is. In other words, because the current drive capability in the inverter was the same, the rise of the node C with a large output capacitive load was delayed. For example, if the time to reach 90% of the final value is defined as the rise time, A is 27 psec (this is defined as τ) and C is 512 psec, which is a difference of about 19 times. (table 1)

(Basic imper 'overnight device' parameters)

Next, let's look at the transient response of the output of the inverter (B in this case) when a source follower 504 with a gate width of 50 times is connected to the output of the basic chamber. The Roh one de of B, despite the next stage of the source follower 5 0 4 of the gate capacitance 5 0 and a capacitor C (j, i.e. a total of 5 1 C _Q is One Burasaga, the rise in the C It can be seen that it is faster than the rise of the node (^ = 5 12 psec), where r = 92 psec, because the next-stage source follower changes the C _{Q of the} D node. In order to drive quickly, the potentials of the C and D nodes rise at the same time and the anti-mirror effect appears, that is, the potentials of the C and D nodes rise at the same time, resulting in the gate capacitance of the source follower 5 Since both ends of O CQ are kept at the same potential and no charge is charged, the equivalent gate input capacitance of 50 C _Q cannot be seen, but there is a delay compared to the response of node A. Because the voltage gain of the source follower is less than 1. That is, if the potentials of the nodes C and D completely change and match, the gate capacitance 50 CQ becomes equivalently 0. However, the force, in fact, the voltage gain of the source follower must be smaller than 1. As a result, the change in the potential of the node D becomes smaller than the change in the potential of the node B, and as a result, a slight potential difference appears at both ends of the input capacitance 50 C ₀ . . in result of obtaining C _f, it was found to be approximately 8 9 C ₀ Additionally, since the voltage gain 0.8 4 in FIG. 4 KaraMotome meth source follower circuit, C _EFF is 5 0 C _FL (1 - 0. 8 4) == 8 0 ^, which is in good agreement with the simulation result.

Fig. 6 shows the results of a calculation using HSPICE simulations for the circuit using the source follower shown in Fig. 5 and the difference in response due to the magnitude of the capacitive load hanging from the output of the source follower circuit. It is shown in FIG. 6, the first stage of Inba Isseki 6 0 1 of the output voltage, i.e. the change in V _A. V _A is the input voltage of the source follower (602) of 50. For n = 1 to 200, almost the same characteristics are obtained. It should be noted here that when the output load capacitance 603 is increased (that is, n is increased), an overshoot phenomenon is observed. This is due to the so-called bootstrap effect. In other words, as the output load capacitance increases, the current drive capability of the source follower is constant, so the speed at which the node of v _B rises slows, and the output v _B does not follow v _A (this is because the anti-Miller effect works). Not mean). Therefore, the large load capacity 51 CJJ can be seen as it is from the node of V ,. However, once this capacitance is charged, the potential of V _A is raised by the bootstrap effect together with the rise of the potential of V _N. Furthermore, by the potential of the V _A is lifted, increasing source one Sufo Roi current driving capability, v potential of _B, that Ru can drive the output load capacitance at a high speed. Figure 7 shows the change in the output V _n of source one source-follower 7 0 1. It can be seen that the output load capacity 702 is driven at high speed, and the current drive capability of the source follower is very large.

The semiconductor device of the present invention shown in FIG. 1 is used to effectively utilize the current drive capability of the source follower described above, and a buffer circuit in which the source follower 103 and the impeller 102 are paired. It is. By doing so, the small voltage amplitude of the source follower 103 can be recovered by the impeller 102, and the large inverter can be driven by the large current drive capability of the source follower to complete Can be increased in current driving capability.

With respect to C _L = 100 C _Q , the optimum values of the size n of the source follower 103 and the size m of the Imbedah 102 were examined. First, a simulation was performed for the source follower size n in the range of 5 to 50, and it was found that the delay time _f became minimum near n = 10. Next, for n = 5, 10, 0, 20 The simulation was performed by changing the size m. Fig. 8 shows the result of calculating the delay time „when m is changed in the range of 20 to 200 with respect to 100 CQ. Is minimum when n = 10. Furthermore, when n = 10 and m = 60, the minimum value of r _r is obtained, and 3.44 and ₀ are obtained. in certain and _r = 3. 7 7 _r ₀ buffer inverter chain, the tapering factor 3, but when the 4 stages. (This is a buffer circuit used conventionally well, each inverter evening size Is 3 times, 9 times, 27 times, and 81 times.) That is, it can be seen that the CMOS source circuit lower-speed buffer circuit is faster than the fastest one-time chain.

Figure 9 shows a capacitive load 901 of C, = 100 C ₀ with n = 10 and an optimized CM 0 S source follower 'buffer circuit 902 with m = 60 and an inverter 903 with a taping factor 3. It is a result of examining a transient response when driven. The delay time (time to reach 90% of the final value) is the smallest when the number of stages n is four. Also, the fastest when the a becomes time to 50% of the final value that defines a r _d, the _d Te number n is three. In any case, can be seen the CM 0 S source follower 'buffer circuit 902 is driving the C _L 901 faster than Inpa evening Chiwein.

(Example 2)

Next, a second embodiment of the present invention is shown in FIG. This is a circuit for driving an even larger load 1001. The source followers 1002, 1003 and Impa's 1004, 1005 are successively increased by four stages.

10, C, = 6000 result of load capacity was examined transient response when driven with n = 10, m = 60 of the CMOS-to-source-follower 'Patsufa circuit and Tepari ring factor 3 in perturbation Chey emissions 1006 C ₀ It is. In this embodiment, a two-stage cascaded buffer circuit as shown in FIG. 1 comprising a source follower and an impeller is used. Also in this case, the CMO S source follower's buffer circuit drives Cj ^ faster than the Imba overnight chain, and the current drive capability of the CMO S source follower / buffer circuit is larger than the EMBTA's chain. You can see that. As described above, as shown in the first and second embodiments, the semiconductor device of the present invention is extremely effective for realizing high-speed operation of a semiconductor super LSI. That is, the CMOS source follower circuit is effective for high-speed driving of a large-capacity load, that is, it has an anti-mirror effect and a bootstrap effect. Furthermore, the CMOS source follower circuit is paired with an inverter. Thus, it became clear that configuring the buffer circuit can increase the total current drive capability. As a result, when driving a capacitance load of 100 times or 600 times the gate capacitance of the CMOS inverter (basic inverter) of the minimum size, the CMOS source follower buffer circuit is more effective than the impeller group. It showed that it can be driven at high speed. Therefore, the CMOS source buffer circuit is an effective buffer circuit that can effectively reduce large capacity such as a bonding pad and a long bus line, and is extremely effective in realizing high-speed operation of a super LSI. .

The puffer circuit, which is a semiconductor device of the present invention, is a combination of a source follower 103 and an inverter 102 as shown in FIG. 1 or a pair of a source follower and an inverter as shown in FIG. Are connected in two stages like 1002 and 1004 and 1003 and 1005. It goes without saying that this may be connected in more stages. In this case, it is necessary to always use the larger one in the later stage. In the embodiments shown in FIGS. 1 and 10, the input to the buffer circuit is “in” (101, 1007), and the load of the output is the capacitance (104, 100). 1), but this is only an example, and the output and input of any circuit may be used. For example, the output of the logic circuit may be input to the buffer circuit of the present invention, and the output of the buffer circuit may be connected to the input of the logic circuit. In the circuit of the present invention, a source follower is provided in the input stage, and the input capacitance is effectively made very small. Therefore, it is very effective to provide it at the output stage of a logic circuit whose capacitance load is to be minimized. For example, a single electron 'transistor' (single electron transistor) uses the phenomenon of Coulomb's opening, so it will not work unless the capacity of the transistor is extremely small. Therefore, the major problem is that the current driving force is small and the data reading is very slow. The present invention is based on such a single 'electron' transistor. It can also be applied very effectively to the configured circuit output readout unit.

(Example 3)

Next, FIG. 11 shows a third embodiment of the present invention. In this embodiment, a source follower is constituted by the NMOS 1101 and the PMOS 1102, and 1103 is a member for forming a pair with the source follower. An NMOS 1104 and a PMOS 1105 are added to the gate, and a signal X and its inverted signal X (bar) are respectively applied to the gates. That is, when X = 0, both NMOS 1104 and PMOS 1105 are turned off, and the DC current flowing to the source lower can be cut. This is effective because power consumption can be reduced. When X = 1, if both transistors are turned on, the circuit will be the same as in Figure 1.

Until now, both the NMOS and the PMOS constituting the source follower have been of the debris type, but the enhancement type may be used. In this case, there is no need to use the configuration shown in Fig. 3 to reduce power consumption. However, in this case, the operating speed is slower than in the case of the debris type. Industrial applicability

According to the present invention, it is possible to drive a load having a large capacity, such as a wiring existing in an VLSI chip or a circuit outside the chip, at a very high speed.

Claims

The scope of the claims

1. A source electrode has at least a pair of NM 0 S and PM 0 S connected to each other, and the NMOS drain electrode is biased to a higher potential than the PMOS drain electrode, and is connected to each other. In a circuit in which a source electrode is connected to an input of a CMOS inverter and a capacitive load is connected to an output of the CMOS inverter, the magnitude of the capacitive load is larger than the gate input capacitance of the CMOS inverter. Wherein the gate input capacitance of the CMOS inverter is set to be larger than the sum of the respective input gate capacitances of the NMOS and PMOS.