WO1995010880A1 - Adaptive bandwidth controlled frequency synthesizer - Google Patents

Adaptive bandwidth controlled frequency synthesizer Download PDF

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Publication number
WO1995010880A1
WO1995010880A1 PCT/US1994/011543 US9411543W WO9510880A1 WO 1995010880 A1 WO1995010880 A1 WO 1995010880A1 US 9411543 W US9411543 W US 9411543W WO 9510880 A1 WO9510880 A1 WO 9510880A1
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WO
WIPO (PCT)
Prior art keywords
signal
frequency
sink
source
phase
Prior art date
Application number
PCT/US1994/011543
Other languages
French (fr)
Inventor
Barry W. Herold
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to TW083110047A priority Critical patent/TW271517B/zh
Publication of WO1995010880A1 publication Critical patent/WO1995010880A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Definitions

  • This invention relates in general to phase lock loops and more particularly to a phase lock loop having adaptive bandwidth control.
  • PLL phase lock loop
  • phase lock loops typically use a prescaler (commonly referred to as a divide-by-N counter, dual modulus counter, or the like) for scaling the output frequency to a lower frequency such that it may be coupled to a low power phase/frequency detector and the loop filter to control a voltage controlled oscillator.
  • the voltage controlled oscillator in turn produces the output frequency responsive to the phase/frequency difference detected by the phase/frequency detector and further in response to the time and frequency domain characteristics of the loop filter.
  • the components of the phase lock system, especially the loop filter are typically designed for optimal performance at a selected operating power, divider count, and corresponding output frequency. This constraint produces compromised performance (especially with respect to lock or settling time) during low power operation, and at frequencies other than that produced by the selected divider count.
  • Many artisans have attempted to solve the problems associated with operation at low power levels, with no success.
  • phase lock loop synthesizers do not operate in a mode that minimizes total power consumption and consequently, have relatively slow lock times and wide frequency variations during tracking.
  • phase lock loop frequency synthesizer topology that offers improved frequency lock and tracking characteristics.
  • a phase lock loop frequency synthesizer having a programmable output frequency signal
  • the phase lock loop frequency synthesizer comprising: a phase/frequency detector having a detector output signal representing a phase/frequency difference between a reference frequency signal and the programmable output frequency signal; a sink-source-float circuit coupled to the phase/frequency detector for generating a sink-source-float output signal; a voltage mode loop filter coupled to the sink-source-float circuit for converting the sink-source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal; a voltage controlled variable frequency oscillator coupled to the voltage mode loop filter, the voltage controlled variable frequency oscillator producing the programmable output frequency signal in response to the band- limited voltage spectra; a prescaler coupled to the voltage controlled variable frequency oscillator for dividing the programmable output frequency signal to produce a prescaled feedback signal; and a sink-source-float control circuit coupled to the pre
  • FIG. 1 is a block diagram of a selective call receiver suitable for use with the present invention.
  • FIG. 2 is a partial block diagram of the selective call receiver depicted in FIG. 1 implementing a frequency synthesized zero-IF receiver in accordance with a first embodiment of the invention.
  • FIG. 3 is a partial block diagram of the selective call receiver depicted in FIG. 1 implementing a frequency synthesized dual conversion receiver in accordance with a second embodiment of the invention.
  • FIG. 4 is a block diagram of an adaptive bandwidth phase lock loop in accordance with the preferred embodiment of the present invention.
  • a battery 101 powered selective call receiver operates to receive a signal via an antenna 102.
  • a receiver 103 couples a received signal to a demodulator 104, which recovers any information present using conventional techniques .
  • the recovered information signal is coupled to a controller 105 that interprets and decodes the information contained therein.
  • the controller 105 comprises a microprocessor having a signal processor (e.g., a decoder) implemented in both hardware and software.
  • the recovered information is checked by the decoder, which implements the signal processor for correlating a recovered address with a predetermined address .
  • the non ⁇ volatile memory 107 typically has a plurality of registers for storing the predetermined address and a plurality of configuration words that characterize the operation of the selective call receiver.
  • determining the selection of the selective call receiver a correlation is performed between a recovered address contained within the information signal with a predetermined address corresponding to the selective call receiver.
  • a detect is generated indicating selection of the selective call receiver and the controller 105 couples decoded message information to the message memory 106.
  • the support circuit 108 operates to process at least a portion of the message information for presentation, such as by a display 110, and may signal the user via an audible or tactile alert 111 that a message has been received.
  • the user may view the information presented on the display 110 by activating the appropriate controls 109.
  • the support circuit 108 preferably comprises a conventional signal multiplexing integrated circuit, a voltage regulator 300 that may supply a regulated voltage to portions of the support circuit 108, receiver 103, demodulator 104, or other selective call receiver components.
  • the support circuit may be integrally coupled with the controller (e.g., a microcontroller includes features such as A/D, D/A converters, programmable I/O ports, a control buss, etc. ) .
  • the support circuit 108 may include environmental sensing circuitry such as for light or temperature conditions, audio power amplifier circuitry, control interface circuitry, a clock frequency synthesizer, and display illumination circuitry. These elements are conventionally assembled to provide the information display receiver as requested by a customer. Referring to FIG. 2, the partial block diagram illustrates a frequency synthesized zero-IF receiver implemented in the selective call receiver depicted in FIG. 1, in accordance with a first embodiment of the invention..
  • a received signal that may include a modulated carrier signal is converted down to baseband using a conventional frequency converter 201.
  • the resulting baseband signal is then demodulated using a conventional zero-if demodulator 202 such as a differentiate and cross-multiply topology or the like.
  • the conversion is accomplished by mixing the received signal with a local oscillator signal provided by a controllable frequency synthesizer (i.e., a controllable signal source) 203.
  • controllable frequency synthesizer 203 comprises a programmable phase-locked loop synthesizer 204, using for example, at least one of a conventional divide-by-N prescaler, a dual modulus divider, or a fractional N division scheme such that the local oscillator signal frequency may be stepped in coarse or fine increments .
  • the controllable frequency synthesizer 203 may also be used to synthesize a number of frequencies required to clock digital logic circuitry associated with other of the components comprising the selective call receiver.
  • the controllable frequency synthesizer 203 is responsive to a controller module (e.g., an MC68HC05C4 manufactured by Motorola, Inc.) 105, that performs a sequence of decisions and controlling actions, as will be subsequently more fully discussed.
  • the controller module 105 adjusts the local oscillator signal frequency by writing a control word (e.g., a divide factor) into the controllable frequency synthesizer 203, thereby programming the phase-locked loop 204 to a target frequency.
  • the control word is derived from a relation between the frequency reference element 205 and the desired output frequency. The relation may be predetermined and its parameters are stored in the non-volatile memory 107 that is accessed by the controller 105.
  • the partial block diagram illustrates a frequency synthesized dual conversion receiver implemented in the selective call receiver depicted in FIG. 1, in accordance with a second embodiment of the invention.
  • the selective call receiver "RF front end" 301, 302, 303, 304, 305 is responsive to a transmitted signal that is received and coupled in via an antenna 102, as is commonly known in the art.
  • the received signal from the antenna 102 may be optionally preconditioned using known techniques to provide an optimum signal level within a predetermined frequency bandwidth that is coupled to a first mixer 304.
  • the optional preconditioning of the received signal is usually performed by a matching circuit 301, a radio frequency amplifier 302, and a preselector filtering circuit 303, the design and function of these circuits being generally well known in the art.
  • the matching circuit 301 matches the antenna 102 impedance characteristics to the RF amplifier 302.
  • the matching circuit is designed to provide the RF amplifier 302 with an optimum noise match (minimum noise figure) and low insertion loss, thereby optimally delivering the received signal power from the antenna 102 to the RF amplifier 302.
  • the amplified signal is then coupled to a preselector filtering circuit 303 that accepts a desired signal with minimal attenuation (e.g., within a predetermined frequency band) and attenuates (i.e., rejects) all undesired signals. Consequently, the received signal is preconditioned and coupled to the first signal mixer 304.
  • a preselector filtering circuit 303 that accepts a desired signal with minimal attenuation (e.g., within a predetermined frequency band) and attenuates (i.e., rejects) all undesired signals. Consequently, the received signal is preconditioned and coupled to the first signal mixer 304.
  • the first mixer 304 subsequently mixes the preconditioned received signal with a first local oscillator injection signal provided by the controllable frequency " synthesizer 203.
  • the controllable frequency synthesizer has an output frequency derived from the frequency reference element 205.
  • the resulting conversion generates a first intermediate frequency signal that is subsequently coupled to a crystal filter 305 that passes the first intermediate frequency signal and attenuates any undesired signals such as the first mixer image signal and the first local oscillator injection signal.
  • a second mixer 306 mixes the first intermediate frequency signal with a second local oscillator injection signal provided by the controllable frequency synthesizer 203.
  • the resulting second intermediate frequency signal is typically filtered and amplified (i.e., by an intermediate frequency amplifying and filtering circuit 307) and coupled to the demodulator 104.
  • the demodulator in this embodiment comprises a modulation detector 308 that recovers information (i.e., FSK digital data, audio tones, PSK digital data, SSB, etc.) that is coupled to a decoder via a data filter 309 in a manner well known in the art.
  • the controller 105 is coupled to the controllable frequency synthesizer 203 including the phase lock loop 204.
  • the controller operates to execute a microcode program that generates a frequency control signal.
  • the frequency control signal serves to program the output frequency of the controllable frequency syn-hesizer 203 to reflect a frequency error of substantially zero parrs per million with respect to a desired operating frequency (e.g., the local oscillator frequency, clock frequency, or the like) .
  • the non-volatile ram (e.g., read only memory, backed-up random access memory, EEPROM, or the like) 107 may provide storage for executable controller instructions, storage for a table representing programmed output frequencies and their corresponding control word(s) (e.g., divide factor(s)), and storage for non-volatile configuration information that may be necessary to perform the decisions and actions in the control process, as will be subsequently more fully discussed.
  • the block diagram illustrates an adaptive bandwidth phase lock loop 204 in accordance with the preferred embodiment of the present invention.
  • the adaptive bandwidth phase lock loop 204 operates as part of the controllable frequency synthesizer 203 and may generate an output signal that can be used for a local oscillator frequency source, clock frequency source (for digital or analog circuitry), or the like.
  • a crystal controlled clock (not shown) is applied to a divide by K programmable counter 401 to create the reference signal, FR 402.
  • the output of the VCO 410 is applied to a high speed prescaler 412 whose output is applied to a programmable divide by N counter 405 to create the feedback signal, FV 404.
  • the two counter outputs, FR 402 and FV 404, are compared by the phase / frequency detector 403 to create pump up (NPU) 406 and pump down (NPD) 407 output signals that are coupled to the sink-source-float 408 (hereafter SSF) circuit.
  • the pump up signal 406 causes the SSF 408 to activate a source current at the output
  • the pump down signal 407 causes the SSF 408 to activate a sink current at the output.
  • the filter 409 translates the current pulse corresponding to either the output sink or source current into a DC voltage to control the operating frequency of the VCO 410.
  • the FR 402 and FV 404 signals have coincident edges, thus indicating a frequency / phase lock condition. A t this point, if the N counter 405 is adjusted to a higher value to cause the loop to adjust to a higher frequency, then at the end of the next reference cycle, the feedback cycle will lag by a time given by:
  • a pump up signal 406 is generated to adjust the VCO to a higher frequency.
  • the total time of the pump up signal is given by:
  • T L2 ⁇ N / f 2
  • the phase of the VCO control signal (voltage) required to force the oscillator up or down in frequency may be inverted. This would effectively reverse the conditions discussed above in that the phase lead and lag corrections would force the loop oscillator frequency in a direction that would still drive the output frequency to lock.
  • the preferred embodiment of the present invention incorporates a sink-source-float control (hereafter SSFC) circuit 413 to modify the output drive of the SSF 408 if a phase / frequency difference is detected for more than a specified number of prescaler cycles.
  • SSFC sink-source-float control
  • integer increments of a time difference between the pump up 406 and pump down 407 signals is accumulated by the SSFC circuit 413, utilizing the prescaler output as a time reference. Once a predetermined time difference has occurred, such as two cycles of the prescaler output frequency, then the multiplication factor of the SSF currents is increased by the SSFC circuit 413 to reduce lock time.
  • FIG. 5 A preferred implementation of the SSFC circuit 413 is depicted in FIG. 5.
  • Signals NPU (pump-up) 506 and NPD ( pump- down) 501 are coupled from the outputs of the phase / frequency detector 403.
  • the pump up signal 406 causes the SSF 408 to activate a source current at the output
  • the pump down signal 407 causes the SSF 408 to activate a sink current at the output.
  • the NPU (pump-up) 506 and NPD (pump-down ) 501 signals are monitored by the SSFC circuit 413 for an active low occurrence using AND gate 507.
  • a phase lock loop frequency synthesizer is implemented having a programmable output frequency signal.
  • the phase lock loop frequency synthesizer comprises a phase/frequency detector having a detector output signal that represents a phase/frequency difference between a reference frequency signal and the programmable output frequency signal.
  • the phase/frequency detector is coupled to a sink-source-float circuit for generating a sink-source-float output signal that couples to a voltage mode loop filter that converts the sink- source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal.
  • a voltage controlled variable frequency oscillator receives the band-limited voltage spectra and in response, produces the programmable output frequency signal.
  • the programmable output frequency signal is coupled to a prescaler that divides the programmable output frequency signal to produce a prescaled feedback signal.
  • a sink-source-float control circuit is coupled to the prescaler, phase/frequency detector, and sink-source-float circuit.
  • the sink-source-float control circuit operates to adjust a multiplication factor of the sink-source-float output signal in response to a phase error determined within the phase lock loop by comparing the prescaled feedback signal to the detector output signal, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
  • the sink-source-float output signal comprises the states as follows: a pump-up source current when a feedback signal lags the reference frequency signal; a pump-down sink current when the feedback signal leads the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
  • the sink- source-float output signal comprises the states as follows: a pump-up source current when a feedback signal leads the reference frequency signal; a pump-down sink current when the feedback signal lags the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
  • the SSF 408 provides sink and source currents depending upon the NPU 506 and NPD 501 signals, and the SSFCNTL signal 509.
  • the SSF 408 provides a sink current.
  • the SSF 408 provides a source current.
  • the output of the SSF 408 is in a tri-state (high impedance) mode.
  • the SSFCNTL signal 509 controls the gain of the SSF 408. With the SSFCNTL 509 high, the SSF 408 provides a higher current level to provide a fast lock response to a large detected phase error. When the SSFCNTL 509 is low, a lower current level is selected for normal loop lock operation.
  • a frequency error greater than 80 KHz would activate the SSFC and significantly reduce the synthesizer lock time.
  • the SSFC realizes a significant reduction in loop lock time by utilizing the output of the prescaler and the outputs of the phase/frequency detector to determine the phase error within the loop. This reduction is achieved by monitoring the NPD 501 or the NPU 506 signals for activation, then sampling, with the SSFC circuit 413, the NPD 501 or NPU 506 signals at the prescaler output frequency. If either signal is active for more than two prescaler clocks, the phase error is determined to be to large, and the gain of the SSF 408 is adjusted to the high bandwidth limit. Thus, phase errors as small as 1/10 of 1% can be detected and corrected. Consequently, the lock time of the loop when operating in both an initial acquirement and a frequency hopping mode.

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Abstract

A selective call receiver (100) includes a phase lock loop frequency synthesizer (204) having a programmable output frequency signal that has an associated lock time. The associated lock time is adaptively decreased by using a sink-source-float control circuit (413) that adjusts a loop bandwidth and sink-source-float gain responsive to a frequency/phase error and a prescaled feedback signal.

Description

ADAPTIVE BANDWIDTH CONTROLLED FREQUENCY SYNTHESIZER
Field Qf the Invention
This invention relates in general to phase lock loops and more particularly to a phase lock loop having adaptive bandwidth control.
Back roun gf the Tnventi nn
In portable battery operated products such as a selective call receiver, it is desirable to have the lowest possible current drain in order to maximize battery life, while maintaining high performance standards for receiving and decoding systems. Today's state-of-the-art selective call receivers typically use conventional phase lock loop(s) (PLL's) to synthesize frequencies needed for digital logic or radio frequency circuits. These components operate in a fashion such that when switched from a first frequency to a second frequency, an output frequency is achieved relative to a reference frequency. Conventional PLL's, during switching, require a significant amount of power to achieve short lock times. The output frequency variations and ultimate tracking are limited by the loop response as determined by the performance of a loop filter and a controlled oscillator. By design, conventional phase lock loops typically use a prescaler (commonly referred to as a divide-by-N counter, dual modulus counter, or the like) for scaling the output frequency to a lower frequency such that it may be coupled to a low power phase/frequency detector and the loop filter to control a voltage controlled oscillator. The voltage controlled oscillator in turn produces the output frequency responsive to the phase/frequency difference detected by the phase/frequency detector and further in response to the time and frequency domain characteristics of the loop filter. The components of the phase lock system, especially the loop filter, are typically designed for optimal performance at a selected operating power, divider count, and corresponding output frequency. This constraint produces compromised performance (especially with respect to lock or settling time) during low power operation, and at frequencies other than that produced by the selected divider count. Many artisans have attempted to solve the problems associated with operation at low power levels, with no success.
Hence, conventional phase lock loop synthesizers do not operate in a mode that minimizes total power consumption and consequently, have relatively slow lock times and wide frequency variations during tracking.
Thus, what is needed is a phase lock loop frequency synthesizer topology that offers improved frequency lock and tracking characteristics.
Summary—ai— t & inv irm
Briefly, according to the invention, there is provided a phase lock loop frequency synthesizer having a programmable output frequency signal, the phase lock loop frequency synthesizer comprising: a phase/frequency detector having a detector output signal representing a phase/frequency difference between a reference frequency signal and the programmable output frequency signal; a sink-source-float circuit coupled to the phase/frequency detector for generating a sink-source-float output signal; a voltage mode loop filter coupled to the sink-source-float circuit for converting the sink-source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal; a voltage controlled variable frequency oscillator coupled to the voltage mode loop filter, the voltage controlled variable frequency oscillator producing the programmable output frequency signal in response to the band- limited voltage spectra; a prescaler coupled to the voltage controlled variable frequency oscillator for dividing the programmable output frequency signal to produce a prescaled feedback signal; and a sink-source-float control circuit coupled to the prescaler, phase/frequency detector, and sink- source-float circuit, the sink-source-float control circuit operating to adjust a multiplication factor of the sink- source-float output signal responsive to a phase error determined within the phase lock loop by comparing the prescaled feedback signal to the detector output signal, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
Brief Description of the τvr»tHγ^
FIG. 1 is a block diagram of a selective call receiver suitable for use with the present invention.
FIG. 2 is a partial block diagram of the selective call receiver depicted in FIG. 1 implementing a frequency synthesized zero-IF receiver in accordance with a first embodiment of the invention.
FIG. 3 is a partial block diagram of the selective call receiver depicted in FIG. 1 implementing a frequency synthesized dual conversion receiver in accordance with a second embodiment of the invention.
FIG. 4 is a block diagram of an adaptive bandwidth phase lock loop in accordance with the preferred embodiment of the present invention.
Pes riPtJPB Of a Preferred EmhorH meni-
Referring to FIG. 1, a battery 101 powered selective call receiver operates to receive a signal via an antenna 102. A receiver 103 couples a received signal to a demodulator 104, which recovers any information present using conventional techniques . The recovered information signal is coupled to a controller 105 that interprets and decodes the information contained therein. In the preferred embodiment, the controller 105 comprises a microprocessor having a signal processor (e.g., a decoder) implemented in both hardware and software.
The recovered information is checked by the decoder, which implements the signal processor for correlating a recovered address with a predetermined address . The non¬ volatile memory 107 typically has a plurality of registers for storing the predetermined address and a plurality of configuration words that characterize the operation of the selective call receiver. In determining the selection of the selective call receiver, a correlation is performed between a recovered address contained within the information signal with a predetermined address corresponding to the selective call receiver. When the addresses substantially correlate, a detect is generated indicating selection of the selective call receiver and the controller 105 couples decoded message information to the message memory 106. In accordance with the recovered information, settings associated with the user controls 109, and detection, the support circuit 108 operates to process at least a portion of the message information for presentation, such as by a display 110, and may signal the user via an audible or tactile alert 111 that a message has been received. The user may view the information presented on the display 110 by activating the appropriate controls 109. The support circuit 108 preferably comprises a conventional signal multiplexing integrated circuit, a voltage regulator 300 that may supply a regulated voltage to portions of the support circuit 108, receiver 103, demodulator 104, or other selective call receiver components. Alternatively, the support circuit may be integrally coupled with the controller (e.g., a microcontroller includes features such as A/D, D/A converters, programmable I/O ports, a control buss, etc.). Furthermore, the support circuit 108 may include environmental sensing circuitry such as for light or temperature conditions, audio power amplifier circuitry, control interface circuitry, a clock frequency synthesizer, and display illumination circuitry. These elements are conventionally assembled to provide the information display receiver as requested by a customer. Referring to FIG. 2, the partial block diagram illustrates a frequency synthesized zero-IF receiver implemented in the selective call receiver depicted in FIG. 1, in accordance with a first embodiment of the invention.. A received signal that may include a modulated carrier signal is converted down to baseband using a conventional frequency converter 201. The resulting baseband signal is then demodulated using a conventional zero-if demodulator 202 such as a differentiate and cross-multiply topology or the like. The conversion is accomplished by mixing the received signal with a local oscillator signal provided by a controllable frequency synthesizer (i.e., a controllable signal source) 203. In the preferred embodiment, the controllable frequency synthesizer 203 comprises a programmable phase-locked loop synthesizer 204, using for example, at least one of a conventional divide-by-N prescaler, a dual modulus divider, or a fractional N division scheme such that the local oscillator signal frequency may be stepped in coarse or fine increments . The controllable frequency synthesizer 203 may also be used to synthesize a number of frequencies required to clock digital logic circuitry associated with other of the components comprising the selective call receiver. The controllable frequency synthesizer 203 is responsive to a controller module (e.g., an MC68HC05C4 manufactured by Motorola, Inc.) 105, that performs a sequence of decisions and controlling actions, as will be subsequently more fully discussed. The controller module 105 adjusts the local oscillator signal frequency by writing a control word (e.g., a divide factor) into the controllable frequency synthesizer 203, thereby programming the phase-locked loop 204 to a target frequency. The control word is derived from a relation between the frequency reference element 205 and the desired output frequency. The relation may be predetermined and its parameters are stored in the non-volatile memory 107 that is accessed by the controller 105.
Referring to FIG. 3, the partial block diagram illustrates a frequency synthesized dual conversion receiver implemented in the selective call receiver depicted in FIG. 1, in accordance with a second embodiment of the invention.
The selective call receiver "RF front end" 301, 302, 303, 304, 305 is responsive to a transmitted signal that is received and coupled in via an antenna 102, as is commonly known in the art. The received signal from the antenna 102 may be optionally preconditioned using known techniques to provide an optimum signal level within a predetermined frequency bandwidth that is coupled to a first mixer 304.
The optional preconditioning of the received signal is usually performed by a matching circuit 301, a radio frequency amplifier 302, and a preselector filtering circuit 303, the design and function of these circuits being generally well known in the art. The matching circuit 301 matches the antenna 102 impedance characteristics to the RF amplifier 302. Preferably, the matching circuit is designed to provide the RF amplifier 302 with an optimum noise match (minimum noise figure) and low insertion loss, thereby optimally delivering the received signal power from the antenna 102 to the RF amplifier 302. The amplified signal is then coupled to a preselector filtering circuit 303 that accepts a desired signal with minimal attenuation (e.g., within a predetermined frequency band) and attenuates (i.e., rejects) all undesired signals. Consequently, the received signal is preconditioned and coupled to the first signal mixer 304.
The first mixer 304 subsequently mixes the preconditioned received signal with a first local oscillator injection signal provided by the controllable frequency "synthesizer 203. The controllable frequency synthesizer has an output frequency derived from the frequency reference element 205. The resulting conversion generates a first intermediate frequency signal that is subsequently coupled to a crystal filter 305 that passes the first intermediate frequency signal and attenuates any undesired signals such as the first mixer image signal and the first local oscillator injection signal.
A second mixer 306 mixes the first intermediate frequency signal with a second local oscillator injection signal provided by the controllable frequency synthesizer 203. The resulting second intermediate frequency signal is typically filtered and amplified (i.e., by an intermediate frequency amplifying and filtering circuit 307) and coupled to the demodulator 104. The demodulator in this embodiment comprises a modulation detector 308 that recovers information (i.e., FSK digital data, audio tones, PSK digital data, SSB, etc.) that is coupled to a decoder via a data filter 309 in a manner well known in the art. In performing frequency selection, the controller 105 is coupled to the controllable frequency synthesizer 203 including the phase lock loop 204. The controller operates to execute a microcode program that generates a frequency control signal. The frequency control signal serves to program the output frequency of the controllable frequency syn-hesizer 203 to reflect a frequency error of substantially zero parrs per million with respect to a desired operating frequency (e.g., the local oscillator frequency, clock frequency, or the like) . The non-volatile ram (e.g., read only memory, backed-up random access memory, EEPROM, or the like) 107 may provide storage for executable controller instructions, storage for a table representing programmed output frequencies and their corresponding control word(s) (e.g., divide factor(s)), and storage for non-volatile configuration information that may be necessary to perform the decisions and actions in the control process, as will be subsequently more fully discussed.
Referring to FIG. 4, the block diagram illustrates an adaptive bandwidth phase lock loop 204 in accordance with the preferred embodiment of the present invention. The adaptive bandwidth phase lock loop 204 operates as part of the controllable frequency synthesizer 203 and may generate an output signal that can be used for a local oscillator frequency source, clock frequency source (for digital or analog circuitry), or the like. In a phase locked loop system, as shown in FIG. 4, a crystal controlled clock (not shown) is applied to a divide by K programmable counter 401 to create the reference signal, FR 402. The output of the VCO 410 is applied to a high speed prescaler 412 whose output is applied to a programmable divide by N counter 405 to create the feedback signal, FV 404. The two counter outputs, FR 402 and FV 404, are compared by the phase / frequency detector 403 to create pump up (NPU) 406 and pump down (NPD) 407 output signals that are coupled to the sink-source-float 408 (hereafter SSF) circuit. The pump up signal 406 causes the SSF 408 to activate a source current at the output, and the pump down signal 407 causes the SSF 408 to activate a sink current at the output. The filter 409 translates the current pulse corresponding to either the output sink or source current into a DC voltage to control the operating frequency of the VCO 410. When the loop is in a steady state, the FR 402 and FV 404 signals have coincident edges, thus indicating a frequency / phase lock condition. At this point, if the N counter 405 is adjusted to a higher value to cause the loop to adjust to a higher frequency, then at the end of the next reference cycle, the feedback cycle will lag by a time given by:
tLi= ΔN/fi
Where N = Change in the value of the N counter
and fi = VCO frequency at time ti
Thus for the time length t∑,ι, a pump up signal 406 is generated to adjust the VCO to a higher frequency. At the end of two reference cycles, the total time of the pump up signal is given by:
TL2 - ι + tL2
Where TL2 = ΔN / f2
and tι-2 < tLχ in a stable system.
In an alternate embodiment of this system, the phase of the VCO control signal (voltage) required to force the oscillator up or down in frequency may be inverted. This would effectively reverse the conditions discussed above in that the phase lead and lag corrections would force the loop oscillator frequency in a direction that would still drive the output frequency to lock. Referring again to FIG. 4, the preferred embodiment of the present invention incorporates a sink-source-float control (hereafter SSFC) circuit 413 to modify the output drive of the SSF 408 if a phase / frequency difference is detected for more than a specified number of prescaler cycles. In the preferred embodiment, integer increments of a time difference between the pump up 406 and pump down 407 signals is accumulated by the SSFC circuit 413, utilizing the prescaler output as a time reference. Once a predetermined time difference has occurred, such as two cycles of the prescaler output frequency, then the multiplication factor of the SSF currents is increased by the SSFC circuit 413 to reduce lock time.
A preferred implementation of the SSFC circuit 413 is depicted in FIG. 5. Signals NPU (pump-up) 506 and NPD (pump- down) 501 are coupled from the outputs of the phase / frequency detector 403. The pump up signal 406 causes the SSF 408 to activate a source current at the output, and the pump down signal 407 causes the SSF 408 to activate a sink current at the output. The NPU (pump-up) 506 and NPD (pump-down) 501 signals are monitored by the SSFC circuit 413 for an active low occurrence using AND gate 507. When an active low signal is detected at the output of AND gate 507, the output is synchronized using D flip-flops 503, 504, that are clocked with the prescaler clock PRECLK 508 through inverter 502, to determine if an activation has occurred for at least one half of the prescaler output period. When these conditions occur, the output of AND gate 505, the SSFCTL signal 509, which is coupled to the SSF 408, is activated to increase the pump current levels, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
In summary, a phase lock loop frequency synthesizer is implemented having a programmable output frequency signal. The phase lock loop frequency synthesizer comprises a phase/frequency detector having a detector output signal that represents a phase/frequency difference between a reference frequency signal and the programmable output frequency signal. The phase/frequency detector is coupled to a sink-source-float circuit for generating a sink-source-float output signal that couples to a voltage mode loop filter that converts the sink- source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal. A voltage controlled variable frequency oscillator receives the band-limited voltage spectra and in response, produces the programmable output frequency signal. The programmable output frequency signal is coupled to a prescaler that divides the programmable output frequency signal to produce a prescaled feedback signal.
A sink-source-float control circuit is coupled to the prescaler, phase/frequency detector, and sink-source-float circuit. The sink-source-float control circuit operates to adjust a multiplication factor of the sink-source-float output signal in response to a phase error determined within the phase lock loop by comparing the prescaled feedback signal to the detector output signal, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
The sink-source-float output signal comprises the states as follows: a pump-up source current when a feedback signal lags the reference frequency signal; a pump-down sink current when the feedback signal leads the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal. Alternatively, in a dual system having a voltage controlled oscillator with a control voltage of opposite sense, the sink- source-float output signal comprises the states as follows: a pump-up source current when a feedback signal leads the reference frequency signal; a pump-down sink current when the feedback signal lags the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
Operationally, the SSF 408 provides sink and source currents depending upon the NPU 506 and NPD 501 signals, and the SSFCNTL signal 509. With the NPU 506 signal activated, the SSF 408 provides a sink current. When the NPD 501 signal is activated, the SSF 408 provides a source current. When both NPU 506 and NPD 501 are not activated, the output of the SSF 408 is in a tri-state (high impedance) mode. The SSFCNTL signal 509 controls the gain of the SSF 408. With the SSFCNTL 509 high, the SSF 408 provides a higher current level to provide a fast lock response to a large detected phase error. When the SSFCNTL 509 is low, a lower current level is selected for normal loop lock operation.
As an example, in a low frequency synthesized system which includes a divide by 32/33 prescaler and a 5 KHz reference, a frequency error greater than 80 KHz would activate the SSFC and significantly reduce the synthesizer lock time.
The SSFC realizes a significant reduction in loop lock time by utilizing the output of the prescaler and the outputs of the phase/frequency detector to determine the phase error within the loop. This reduction is achieved by monitoring the NPD 501 or the NPU 506 signals for activation, then sampling, with the SSFC circuit 413, the NPD 501 or NPU 506 signals at the prescaler output frequency. If either signal is active for more than two prescaler clocks, the phase error is determined to be to large, and the gain of the SSF 408 is adjusted to the high bandwidth limit. Thus, phase errors as small as 1/10 of 1% can be detected and corrected. Consequently, the lock time of the loop when operating in both an initial acquirement and a frequency hopping mode.
What is claimed is:

Claims

1. A phase lock loop frequency synthesizer having a programmable output frequency signal, the phase lock loop frequency synthesizer comprising: a phase/frequency detector having a detector output signal representing a phase/frequency difference between a reference frequency signal and the programmable output frequency signal; a sink-source-float circuit coupled to the phase/frequency detector for generating a sink-source-float output signal; a voltage mode loop filter coupled to the sink-source- float circuit for converting the sink-source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal; a voltage controlled variable frequency oscillator coupled to the voltage mode loop filter, the voltage controlled variable frequency oscillator producing the programmable output frequency signal in response to the band- limited voltage spectra; a prescaler coupled to the voltage controlled variable frequency oscillator for dividing the programmable output frequency signal to produce a prescaled feedback signal; and a sink-source-float control circuit coupled to the prescaler, phase/frequency detector, and sink-source-float circuit, the sink-source-float control circuit operating to adjust a multiplication factor of the sink-source-float output signal responsive to a phase error determined within the phase lock loop by comparing the prescaled feedback signal to the detector output signal, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
2. The phase lock loop frequency synthesizer according to claim 1 wherein the sink-source-float output signal comprises: a pump-up source current when a feedback signal lags the reference frequency signal; a pump-down sink current when the feedback signal leads the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
3. The phase lock loop frequency synthesizer according to claim 1 wherein the sink-source-float output signal comprises: a pump-up source current when a feedback signal leads the reference frequency signal; a pump-down sink current when the feedback signal lags the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal .
4. The phase lock loop frequency synthesizer according to claim 1 wherein the programmable output frequency signal functions as a local oscillator injection signal for a frequency converter in a selective call receiver.
5. The phase lock loop frequency synthesizer according to claim 1 wherein the programmable output frequency signal functions as a clock signal for support circuitry in a selective call receiver.
6. A selective call receiver, comprising: a receiver for providing a received signal; a demodulator for recovering the received signal and providing an information signal; a decoder for correlating a recovered address contained within the information signal with a predetermined address corresponding to the selective call receiver, and responsive to said addresses substantially correlating, generating a detection indicating selection of the selective call receiver; a support circuit to process information for presentation in response to the detection; and a phase lock loop frequency synthesizer having a programmable output frequency signal usable by at least the receiver, the decoder, and the support circuit, the phase lock loop frequency synthesizer comprising: a phase/frequency detector having a detector output signal representing a phase/frequency difference between a reference frequency signal and the programmable output frequency signal; a sink-source-float circuit coupled to the phase/frequency detector for generating a sink-source-float output signal; a voltage mode loop filter coupled to the sink- source-float circuit for converting the sink-source-float output signal to a band-limited voltage spectra representing the phase/frequency difference between the reference frequency signal and the programmable output frequency signal; a voltage controlled variable frequency oscillator coupled to the voltage mode loop filter, the voltage controlled variable frequency oscillator producing the programmable output frequency signal in response to the band- limited voltage spectra; a prescaler coupled to the voltage controlled variable frequency oscillator for dividing the programmable output frequency signal to produce a prescaled feedback signal; and a sink-source-float control circuit coupled to the prescaler, phase/frequency detector, and sink-source-float circuit, the sink-source-float control circuit operating to adjust a multiplication factor of the sink-source-float output signal responsive to a phase error determined within the phase lock loop by comparing the prescaled feedback signal to the detector output signal, thus adaptively decreasing a time necessary to achieve a phase/frequency lock condition.
7. The selective call receiver according to claim 6 wherein the sink-source-float output signal comprises: a pump-up source current when a feedback signal lags the reference frequency signal; a pump-down sink current when the feedback signal leads the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
8. The selective call receiver according to claim 6 wherein the sink-source-float output signal comprises: a pump-up source current when a feedback signal leads the reference frequency signal; a pump-down sink current when the feedback signal lags the reference frequency signal; and a high impedance when the feedback signal is substantially coincident with the reference frequency signal.
9. The selective call receiver according to claim 6 wherein the programmable output frequency signal functions as a local oscillator injection signal for a frequency converter in the selective call receiver.
10. The selective call receiver according to claim 6 wherein the programmable output frequency signal functions as a clock signal for support circuitry in the selective call receiver.
PCT/US1994/011543 1993-10-12 1994-10-12 Adaptive bandwidth controlled frequency synthesizer WO1995010880A1 (en)

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