WO1994019903A1

WO1994019903A1 - Improved video subscriber system and methods for its use

Info

Publication number: WO1994019903A1
Application number: PCT/US1993/001735
Authority: WO
Inventors: Mark C. Koz; Steven D. Wilson; Robert A. Rosenbloom; Masato Hata
Original assignee: Koz Mark C; Masato Hata; Wilson Steven D; Rosenbloom Robert A
Priority date: 1993-02-17
Filing date: 1993-02-17
Publication date: 1994-09-01
Also published as: AU3779493A

Abstract

The technical field of the invention generally concerns systems for receiving and transmitting compressed video and audio data. In particular, a subscriber system (10) includes a communication subsystem (12) to receive compressed data from and transmit compressed data to an ISDN primary access line (14). The communication subsystem (12) exchanges blocks of compressed data with a multi-path memory subsystem (16) that may preserve a copy of the compressed data in a multi-port memory (28) while concurrently exchanging compressed video data with a video decompression engine (52) and/or a video compression engine (178). The multi-path memory subsystem (16) may also concurrently exchange other blocks of compressed data between its multi-port memory (28) and a control microprocessor (212) and/or an auxiliary storage device.

Description

IMPROVED VIDEO SUBSCRIBER SYSTEM AND METHODS FOR ITS USE

Technical Field The present invention relates generally to the technical field of electronic storage and transmission of video data and, more particularly, to an improved subscriber system for receiving and/or transmitting video data in a compressed digital format over a comparatively narrow bandwidth communication channel such as that provided by an Integrated Services Digital Network

("ISDN") twisted pair communication channel, and for presenting images and/or sounds represented by received, compressed video data.

Background Art

To deal rationally with the complexity of present communi¬ cation systems and with the need to make ^{^}different systems mutually compatible, the International Standards Organization ("ISO") developed a model for specifying such systems. Using this model, called the Open Systems Interconnect ("OSI") model, a communication system can be broken down into a hierarchial structure that permits standards to be defined at each level in the structure. The OSI model provides a hierarchy of seven different layers that can occur in a communication system. Each layer in the OSI model specifies a different function performed by the communication system.

The lowest layer in the OSI model, called the physical layer, specifies the physical structure of interfaces in a particular communication system or network. Thus, a standard for the physical layer of a communication system specifies such things as the number of wires, their electrical characteristics, the characteristics of signals transmitted over the wires, connectors used for joining two sets of wires into a single longer set of wires, etc. The next higher layer in the OSI model, called the data link layer, specifies how data is transmitted error free through the communication system. Thus, a standard for the second layer in the OSI model specifies how to detect errors in transmissions passing over the physical layer, and how to correct any errors that may occur during transmission.

The next higher layer in the OSI model, called the network layer, specifies the manner in which connections are formed between various places in the communication system for trans¬ mitting data between them. The standard for the third layer in the OSI model, therefore, specifies the signals transmitted over the data link layer that cause the communication system to transfer data between two places on the network. A recommendation by an International Telegraph and Telephone Consultative Committee ("CCITT") for the ISDN communication channel specifies the three lowest levels in the OSI model. Under the CCITT recommendation, a basic ISDN access consists of two full-duplex 64 kilobits per second ("kbps") digital data channels, called channel Bl and channel B2, plus another full- duplex 16-kbps digital channel, called a D-channel. Under the CCITT recommendation, using time division multiplexing, all three of these digital data channels may be transmitted over a single pair of twisted wires, or over two pairs of twisted wires. ISDN basic rate access, as specified by CCITT, was originally intended to provide a basic digital data transmission capability suitable for use by individuals such as in their homes or small business¬ es.

When ISDN basic rate access was initially specified, each of the B-channels was intended to carry:

1. digital data, such as that from a personal computer or from a computer terminal;

2. Pulse Code Modulation ("PCM") encoded digital voice communication; or 3. a mixture of lower data rate communications including digital data and digitized voice that were each encoded at a fraction of each B-channel's full 64-kbps capacity.

Under the ISDN Recommendation, the D-channel serves two purposes. First, the D-channel carries signaling information that controls the transmission of data over the two B-channels. In addition, when the D-channel is not carrying signaling information, it may be used to transmit packet-switching or low-speed telemetry. The combined data rate at which digital data may be transmitted over twisted pairs of wires in accordance with the ISDN standard for basic rate access is 144-kbps, i.e. 128-kbps for the combined Bl and B2 channels plus 16-kbps for the D-channel. In addition to the ISDN basic rate access specified by CCITT, that organization has also specified a higher performance ISDN communication channel called primary rate access. Depending upon the particular geographic region of the world, using time division multiplexing an ISDN primary rate access has either twenty-four (24) time-slots or thirty-two (32) time-slots, each one of which carries the information of a single ISDN B-channel. The ISDN primary rate access having 24 time-slots is called a Tl-connection. The ISDN primary rate access having 32 time-slots is called an El-connection. One way in which ISDN primary rate access uses these 24 or 32 time-slots is by having each of 23 or 30 time-slots carry an independent B-channel of information with a remaining time-slot carrying a D-channel of" control data.

Moreover, groups of the 23 or 30 time-slots in an ISDN primary rate access may also be used collectively to carry digital information at higher data rates. For example, using a connection identified as HO, six (6) time-slots of an ISDN primary rate access may be dedicated to simultaneously carrying 6 B-channels of information. Thus, an ISDN HO-connection carries 384-kbps of digital information. In addition to the HO-connec- tion, CCITT has also specified a service called a Hll-connection which similarly consists of 24 B-channels. A Hll-connection may be established over an El-connection or alternatively over a Tl-connection plus an independent D-channel of control data. Thus, a Hll-connection simultaneously carries 24 B-channels of information. CCITT has also specified a service called a H12-connection in which an El-connection*s 32 time-slots simultaneously carry 30 B-channels of information plus a D-channel of control data.

While ISDN basic rate access was originally intended to provide voice and slow speed data communication services such as those identified above, over the years developments in digital signal processing and compression techniques have advanced technology to the extent that compressed video data may now be transmitted using ISDN basic rate access. These techniques have progressed to such an extent that there now exist several alternative video data compression techniques such as the CCITT H.261 picture phone recommendation, the Joint Photographic Experts Group ("JPEG") standard, and the Moving Picture Experts Group ("MPEG") standard.

Building upon CCITT*s ISDN recommendation, that organization has also established a recommendation, H.221, which specifies data structures used in transmitting audiovisual teleservices over channels having bandwidths from 56 to 1,920 kbps. CCITT's H.221 Recommendation specifies data structures for communicating audiovisual information over from 1 to 6 B-channels, from 1 to 5 HO-connections, or over either a Hll or a H12-connection. Using 1 to 6 B-channels for transmitting audiovisual information provides data transmission rates of 64 to 384 kbps in increments of 64 kbps. Using 1 to 5 HO-connections provides data transmis¬ sion rates of 384 to 1,920 kbps in increments of 384 kbps. A Hll-connection provides a data transmission rate of 1,536 kbps, while a H12-connection provides a data transmission rate of 1,920 kbps.

In addition to the H.221 Recommendation, CCITT has also established a recommendation, H.242, which specifies a protocol for establishing audiovisual teleservices. The H.242 recommenda¬ tion establishes procedures by which two audiovisual terminals intercommunicate prior to and during an exchange of audiovisual information to match their respective capabilities for transmit¬ ting and receiving audiovisual information. Included among the capabilities intercommunicated between two such terminals are their respective audio capabilities, video capabilities, transfer rate capabilities data capabilities, encryption capabilities, and bit-rate allocation signal ("BAS") capabilities.

United States Patent No. 5,027,400, that issued June 25, 1991, on an application filed in the names of Toru Baji et al. ("the Baji et al. patent") , discloses a multimedia bidirectional broadcasting system that distributes motion picture data using an asynchoronous transfer mode ("ATM") of broadband ISDN communi¬ cation. In the system depicted in FIG. 3 of the Baji et al. patent, a motion picture program data base is maintained at a broadcasting station for transmission using ATM over broadband ISDN communication channels in response to requests received at the broadcasting station from subscriber systems. In the broadcasting station disclosed in the Baji et al. patent, an image encoder compresses a video signal prior to its transmission over the broadband ISDN communication channel to the subscriber system. The subscriber system includes a decoder for decoding the compressed video data and a television monitor for displaying them. Both the broadcasting stations and the subscriber systems disclosed in the Baji et al. patent transmit and receive video data compressed in accordance with a single compression standard.

FIGs. 1-1 through 2-1, 3, 4 13, 15, 20, 28, 32 and 35 of the

Baji et al. patent disclose various different configurations for the subscriber system. FIG. 1-6 depicts a subscriber system adapted for use in a video mail application. In the video mail application, the subscriber system depicted in FIG. 1-6 transmits compressed video data back to the broadcasting station for storage there and subsequent re-transmission to a different subscriber system. While various subscriber systems disclosed in the Baji et al. patent include a "graphic processor 141," it is capable of only simple screen operations such as the shift and drag of an icon. The graphic processor 141 disclosed in the Baji et al. patent is incapable of "realtime number crunching" required for more sophisticated screen operations. Consequently, to provide enhanced graphic capability at the subscriber system of the Baji et al. patent, the broadcasting station, such as that illustrated in FIG. 1-4, may include an image processing engine 187, for effecting time-consuming 3-dimensional graphics processing and the like, and various accelerators (processors) 188. Located in the broadcasting station, the image processing engine 187 and the accelerators 188 are time shared among many subscriber systems communicating with the broadcasting station.

In addition to the broadcasting station disclosed in the Baji et al. patent, a PCT patent application entitled "Adaptive Video File Server and Methods for Its Use," filed February 11, 1992, in the names of Mark C. Koz and Masato Hata, PCT Patent Application No. PCT/US92/01084, discloses a video file server or broadcasting station that includes both a random access data storage subsystem and an archive data storage subsystem for storing compressed video data. In response to commands from subscriber systems, the video file server of this PCT patent application transmits compressed video data to the subscriber systems over communication lines, or receives compressed video data therefrom in accordance with a variety of different compression standards. Compression-decompression cards included in the video file server allow it to adaptively transmit and receive compressed video data compressed in accordance with a variety of different compression standards. The compression- decompression cards of the video file server also provide it with an authoring capability for storing compressed video and/or audio data in the random access data storage subsystem and/or archive data storage subsystem.

In addition to the video file server disclosed in the Koz et al. patent, a second PCT patent application entitled "Adaptive Video Subscriber System and Methods for Its Use," filed February 24, 1992, in the names of Mark C. Koz and Masato Hata, PCT Patent Application No. PCT/US92/01446, discloses a subscriber system adapted for exchanging compressed video data with the video file server or other compatible compressed video systems. The subscriber system disclosed in the second PCT patent application includes a communication subsystem that exchanges compressed video data using ISDN telecommunications. Within the subscriber system, compressed video data is transmitted to a video data format conversion subsystem for decompression and production of a visible image on a CRT. Similarly, compressed audio data is transmitted to an audio data format conversion subsystem for decompression and production of an audible sound on a speaker. Compressed data of visible images and audible sounds may also be obtained with and transmitted from the subscriber system.

While the subscriber system disclosed in the second Koz et al. patent is capable of receiving and transmitting compressed audiovisual data, the organization of the system disclosed there may be incapable of performing certain desirable functions. For example, it appears that the subscriber system disclosed in the second Koz et al. patent might be unable to receive and transmit compressed audiovisual data while concurrently supplying such compressed data for recording on an auxiliary storage device coupled to the subscriber system. For the subscriber system disclosed in the second Koz et al. patent application operating in this way, the combined data rate into and out of its conven¬ tional centralized random access memory ("RAM") due solely to compressed data transfers exceeds 9 megabits per second. Moreover, a microprocessor controlling the subscriber system's operation must effect each of these concurrent memory operations while simultaneously performing other tasks thereby correspond¬ ingly increasing the data rate at the centralized RAM, and on the buses associated therewith.

Disclosure of Invention An object of the present invention is to provide a subscrib¬ er system that can exchange compressed audiovisual data with an ISDN primary rate access while concurrently recording compressed audiovisual data on an auxiliary storage device.

Another object of the present invention is to provide a subscriber system that can retrieve compressed audiovisual data from an auxiliary storage device while concurrently displaying such data and exchanging it with an ISDN primary rate access.

Briefly, in a preferred embodiment, a subscriber system in accordance with the present invention includes a microprocessor for controlling its operation. Also included in the subscriber system is a communication subsystem which responds to commands from the control microprocessor. The communication subsystem preferably exchanges compressed data between the subscriber system and an ISDN communication channel. The subscriber system includes a video data format conver¬ sion subsystem which also responds to commands from the control microprocessor. In one mode of operating the subscriber system, the video data format conversion subsystem receives compressed video data from the communication subsystem and converts it into video data.

Video data produced by the video data format conversion subsystem is transmitted to a video signal generation subsystem included in the subscriber system. The video signal generation subsystem, which also responds to commands from the control microprocessor, generates a video signal from the video data received from the video data format conversion subsystem. The video signal produced by the video signal generation subsystem is adapted for producing a visible image on a display such as a cathode ray tube ("CRT") included in a television or red-blue- green ("RGB") monitor, a liquid crystal display panel, a plasma panel, or any other suitable display device.

The preferred embodiment of the subscriber system of the present invention also includes a video data generation subsys¬ tem. The video data generation subsystem, which also responds to commands from the control microprocessor, receives a video signal obtained from a visible image, for example a signal from a video camera, and generates video data from that video signal. The video data generated by the video data generation subsystem is transmitted to the video data format conversion subsystem. This subsystems converts the video data into compressed data for transmission to the communication subsystem.

A subscriber system in accordance with the present invention also includes a multi-path memory subsystem for efficiently transferring blocks of compressed data concurrently among the communication subsystem, the video data format conversion subsystem, the control microprocessor, and an auxiliary storage device. To effect these transfers of compressed data, the multi- path memory subsystem includes a multi-port memory for storing blocks of compressed data while such data passes through the multi-path memory subsystem. While the multi-path memory system is storing one block of compressed data into the multi-port memory, it concurrently supplies previously stored data from a different block of the memory.

These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiment as illustrated in the various drawing figures. Brief Description of Drawings

FIG. 1 depicts the relationship among FIGs. 1A, IB, 1C and ID, the combined FIGs. 1A-1D depicting a subscriber system in accordance with the present invention; and FIGs. 1A, IB, 1C and ID make up a functional block diagram that depicts a subscriber system in accordance with the present invention including its control microprocessor, communication subsystem, its video data format conversion subsystem including a video decompression engine and a video compression engine, its video signal generation subsystem, its video data generation subsystem, and its multi-path memory subsystem.

Best Mode for Carrying Out the Invention.

Both the PCT patent application entitled "Adaptive Video File Server and Methods for Its Use," filed February 11, 1992, in the names of Mark C. Koz and Masato Hata, PCT Patent Applica¬ tion No. PCT/US92/01084, disclosing a video file server; and the second PCT patent application entitled "Adaptive Video Subscriber System and Methods for Its Use," filed February 24, 1992, in the names of Mark C. Koz and Masato Hata, PCT Patent Application No. PCT/US92/01446, disclosing a subscriber system adapted for exchanging compressed video data with the video file server or other compatible compressed video systems, are incorporated herein by reference. FIGs. 1A through ID depict a subscriber system in accordance with the present invention enclosed within a dashed line 10. Referring now to FIG. 1A, the subscriber system 10 includes a communication subsystem 12 for exchanging compressed data with a communication channel such as an ISDN primary rate access line 14. A preferred embodiment for the communication subsystem 12 is described in a pending PCT patent application PCT/US92/09876 entitled "An Audiovisual Teleservices Interface Subsystem" filed in the names of Mark C. Koz and Jack W. Lix on November 11, 1992, ("the ATIS Patent Application") , which is incorporated herein by reference. Producing a Visible Image

As described in the ATIS Patent Application, a computer program controlling the operation of the communication subsystem 12 upon receiving compressed data from the ISDN line 14 separates it into compressed video data and compressed audio data. The communication subsystem 12 then transmits the separated com¬ pressed data to a multi-path memory subsystem enclosed within a dashed line 16 via an ATIS data bus 18. The multi-path memory subsystem 16 includes an ATIS cycle control register 22 which the computer program executed by the communication subsystem 12 initializes before transmitting data to the multi-path memory subsystem 16. Operating under the control of data loaded into the ATIS cycle control register 22 by the communication subsystem 12, the multi-path memory subsystem 16 may process data received from the communication subsystem 12 in three different ways.

First, the multi-path memory subsystem 16 may cause data received from the communication subsystem 12 via the ATIS data bus 18 to be stored via a first ATIS bi-directional data buffer 24 and a multi-port memory data bus 26 into a multi-port memory 28 included in the multi-path memory subsystem 16. The multi-port memory 28 preferably includes 128k bytes of 25 nanosecond static RAM. The communication subsystem 12 supplies the multi-path memory subsystem 16 with the thirteen low order bits of the address at which data will be stored in the multi-port memory 28 via an ATIS address bus 32. From data loaded into the ATIS cycle control register 22 by the communica¬ tion subsystem 12, the ATIS cycle control register 22 supplies the upper two bits of the address at which data from the communication subsystem 12 will be stored in the multi-port memory 28. The address formed by this combination of bits is transmitted from the ATIS address bus 32 through a first ATIS address buffer 34 to the multi-port memory 28 via a multi-port memory address bus 36.

To create control signals for establishing the preceding operating mode, the multi-path memory subsystem 16 includes a multi-path arbitration Programmable Array Logic ("PAL") Integrat¬ ed Circuit ("IC") 42. The multi-port arbitration PAL 42 is preferably a MACH Field Programmable Gate Array ("FPGA") manufactured by Advanced Micro Devices ("AMD") of Sunnyvale, California . The multi-port arbitration PAL 42 receives signals from the ATIS cycle control register 22 via multi-path mode signal lines 44 that establish the operating mode of the multi-path memory subsystem 16 as specified by the data stored into the ATIS cycle control register 22 by the communication subsystem 12. The multi-port arbitration PAL 42 processes the signals from the ATIS cycle control register 22 to produce various control signals some of which it transmits over first multi-path memory subsystem control signal lines 46 to the first ATIS bi-directional data buffer 24 and the first ATIS address buffer 34. The control signals from the multi-port arbitration PAL 42 determine whether the first ATIS address buffer 34 is activated for transmitting addresses from the ATIS address bus 32 to the multi-port memory address, bus 36, and also whether the first ATIS bi-directional data buffer 24 is activated for exchanging data between the ATIS data bus 18 and the multi-port memory data bus 26. A signal from the multi-port arbitration PAL 42 to the first ATIS bi-directional data buffer 24 also controls the direction of data exchange between the ATIS data bus 18 and the multi-port memory data bus 26. If the control signals from the multi-port arbitration PAL 42 inactivate the first ATIS address buffer 34 and the first ATIS bi-directional data buffer 24, their respective bus output signals are "tri-stated" to allow other portions of the subscriber system 10 access to the multi-port memory 28.

In a second operating mode, the multi-path memory subsystem 16 transmits addresses from the communication subsystem 12 to a video decompression engine 52, illustrated in FIG. IC, via the ATIS address bus 32, a second ATIS address buffer 54, and a video format conversion subsystem address bus 56. Similarly, the multi-path memory subsystem 16 exchanges data between the communication subsystem 12 and the video decompression engine 52 via the ATIS data bus 18, a second ATIS bi-directional data buffer 62, and a video format conversion subsystem data bus 64. Signals transmitted from the multi-port arbitration PAL 42 to a video format conversion subsystem buses PAL 66 via video conversion buses mode signal lines 67 indicate that data is to be exchanged between the ATIS data bus 18 and the video format conversion subsystem data bus 64. The video format conversion subsystem buses PAL 66 is preferable a 22V10 PAL of a type manufactured by AMD. Responsive to the signals from the multi-port arbitration PAL 42, the video format conversion subsystem buses PAL 66 transmits control signals over second multi-path memory subsystem control signal lines 68 which specify whether the second ATIS address buffer 54 and the second ATIS bi-directional data buffer 62 are activated for exchanging addresses and data and the direction of data exchange, or are tri-stated.

In the third operating mode of the multi-path memory subsystem 16, control signals from the multi-port arbitration PAL 42 concurrently activate the first ATIS bi-directional data buffer 24 and the first ATIS address buffer 34 for exchanging addresses and data, while control signals from the video format conversion subsystem buses PAL 66 concurrently activate the second ATIS address buffer 54 and the second ATIS bi-directional data buffer 62 for exchanging addresses and data. Accordingly, in this third operating mode, the multi-path memory subsystem 16 stores data received from the communication subsystem 12 into the multi-port memory 28 while concurrently transmitting such data to the video decompression engine 52. Operating in this third mode, the multi-port arbitration PAL 42 and the video format conversion subsystem buses PAL 66 exchange synchronization signals via multi-path synchronization lines 70 to coordinate concurrent data exchanges respectively occurring with the multi-port memory 28, and over the video format conversion subsystem data bus 64. The video decompression engine 52 includes an Integrated Information Technology, Inc. ("IIT") Vision Controller ("VC") IC 72, and an IIT Vision Processor ("VP") IC 74. The VC IC 72 and the VP IC 74 are marketed by Integrated Information Technology, Inc. of Santa Clara, California. In addition to the VC IC 72 and the VP IC 74, the video decompression engine 52 includes a IM or 4M byte or larger frame buffer dynamic RAM 76 that is accessible via a decompression engine bus 78 both to the VC IC 72 and to the VP IC 74. The video decompression engine 52 also includes a 32k byte boot ROM 82 and a 64k byte static RAM 84 that only the VC IC 72 may access. Similarly, the VP IC 74 accesses its own 32k byte static RAM 86.

Upon receiving compressed video data from the communication subsystem 12, a computer program executed by the VC IC 72 performs Huffman decoding on the compressed video data. The VC IC 72 then supplies the Huffman decoded video data to the VP IC 74, and supervises decompression of the video data by the VP IC 74. After the VP IC 74 decompresses the video data, the VC IC 72 generates digital pixel video data from the decompressed video data, and transmits the video data thus produced over a decom¬ pressed video data bus 88 to a first video data input 90 of a Digital Video Processor ("DVP") IC 92. .

The DVP IC 92 is preferably a CL-PX2070 marketed by Pixel Semiconductor, Inc., a subsidiary of Cirrus Logic, Inc. of Fremont, California. In addition to receiving video data from the video decompression engine 52, the DVP IC 92 receives video timing signals via a video timing signal bus 94 from either a SAA7151 Digital Multistandard Colour Decoder or a SAA7191 Digital Multistandard Colour Decoder - Square Pixel ("DMSCD") IC 96 included in a video data generation subsystem enclosed within a dashed line 98. Operating in synchronization with the video timing signals, the DVP IC 92 performs real-time interpolated scaling operations on the video data received from the video decompression engine 52, and arbitrarily scales and clips that digitized video data. The DVP IC 92 then incorporates the scaled and clipped video data into a frame of pixel video data that is separated into its red-green-blue color components.

The frame of color separated pixel video data is then transmitted from the DVP IC 92 over an image data bus 104 to a parallel input port of a dual page video RAM 106, illustrated in FIG. ID. In response to timing signals supplied to the video RAM 106 via the video timing signal bus 94 from the DMSCD IC 96, the video RAM 106 transmits successive frames of pixel video data from its serial port over a video DAC input bus 112 to a video signal generation subsystem 114. The video signal generation subsystem 114 includes a video digital-to-analog converter ("DAC") IC 116 which preferably is a CL-PX2080 MediaDAC™ marketed by Pixel Semiconductor, Inc. The video DAC IC 116 includes a video input interface adapted for receiving digitized video data from the video RAM 106.

The video DAC IC 116 processes successive frames of video data from the video RAM 106 in synchronism with timing signals supplied to the video DAC IC 116 via the video timing signal bus 94 to generate either RS-343A or RS-170 compatible video signals. If the video DAC IC 116 produces RS-343A video signals, then the video signals are supplied as red-green-blue ("RGB") video signals via a RGB bus 122 directly to a color cathode ray tube ("CRT") 124 included in an RGB monitor for producing a visible image on the CRT 124. If the video DAC IC 116 produces RS-170 video signals, the RGB video signals are supplied to a BAL7230LS RGB Encoder for National Television Systems Committee ("NTSC") IC 126 manufactured by ROHM Co., Ltd. of Kyoto, Japan. The RGB encoder IC 126 converts the RGB video signals that it receives via the RGB bus 122 into an NTSC color composite video signal. The NTSC color composite video signal is transmitted from the RGB encoder IC 126 via a composite video signal output line 128 to a color television set for producing a visible image on its CRT 124. The RGB encoder IC 126 also produces chroma and luminance signals that are transmitted from the subscriber system 10 via a chroma output line 132 and a luminance output line 134 of a video output signal bus 136 for creating a visible image on a CRT 124 included in a component video monitor.

Transmitting Compressed Video Data

The video data generation subsystem 98 of the subscriber system 10, illustrated in FIG. IC, receives a color composite video signal obtained from a visible image by a video camera 142 via a composite video signal input line 144. The composite video signal from the video camera 142 is supplied to a composite-and- luminance analog-to-digital converter ("ADC") 146 via the composite video signal input line 144. The composite-and-luminance ADC 146 is preferably a TDA8708 Video Analog Input Interface IC manufactured by Philips Semiconductors of Sunnyvale, California. The composite-and-luminance ADC 146 digitizes the color composite video signal in synchronization with timing signals supplied to the composite-and-luminance ADC 146 by the DMSCD IC 96 via the video timing signal bus 94.

The digitized video signal produced by the composite-and-luminance ADC 146 from a composite video signal is transmitted to a CVBS-or-Y input 152 of the DMSCD IC 96 via a first digitized video signal bus 154. The DMSCD IC 96, which is manufactured by Philips Semiconductors of Sunnyvale, California, processes the digitized video signal from the composite-and-luminance ADC 146 to obtain both video timing signals and video data. To provide all clock signals required for either the SAA7151 or SAA7191 DMSCD IC 96, the video data generation subsystem 98 also includes respectively either a SAA7157 or a SAA7197 clock signal generator IC (not illustrated in the FIGs.) that is also manufactured by Philips Semiconductors of Sunnyvale, California.

Instead of receiving color composite video signals, the video data generation subsystem 98 may receive a chroma signal via a chroma input signal line 156 of a video input signal bus 158, and a luminance signal via a luminance input signal line 162 of the bus 158, perhaps from a component VCR 164. If the video data generation subsystem 98 receives chroma and luminance signals instead of composite video signals, the composite-and-luminance ADC 146 selects and digitizes the luminance signal on the luminance input signal line 162 while a chroma ADC 166 digitizes the chroma signal on the chroma input signal line 156. The chroma ADC 166 is preferably a TDA8709 Video Analog Input Interface IC manufactured by Philips Semicon¬ ductors of Sunnyvale, California. The digitized video signal produced by the composite-and-luminance ADC 146 is supplied to the DMSCD IC 96 via the first digitized video signal bus 154 while the digitized video signal produced by the chroma ADC 166 is supplied to a chrominance input 168 of the DMSCD IC 96 via a second digitized video signal bus 172. The DMSCD IC 96 processes the digitized video signals that it receives on the buses 154 and 172 to produce video timing signals and video data in a manner analogous to the processing described previously for a digitized composite video signal. The uncompressed video data produced by the DMSCD IC 96 is transmitted via a video data bus 174 both to a second video data input 176 of the DVP IC 92, and to a video compression engine 178. Analogously to the video decompression engine 52, the video compression engine 178 includes a VC IC 182, and a pair of VP ICs 184 and 186. In addition to the VC IC 182 and the VP ICs 184 and 186, the video compression engine 178 includes a IM or 4M byte or larger frame buffer dynamic RAM 188 that is accessible via a compression engine bus 192 both to the VC IC 182 and to the VP ICs 184 and 186. The video compression engine 178 also includes a 32k byte boot ROM 194 and a 64k byte static RAM 196 that only the VC IC 182 may access. Analogously, each of the VP ICs 184 and 186 accesses its own 32k byte static. RAM 198 and 202.

A computer program executed by the VC IC 182 controls the passage of data through the video compression engine 178, and the processing of that data into Huffman encoded compressed video data by the VC IC 182 and the two VP ICs 'l84 and 186. In receiving video data from the DMSCD IC 96, the VC IC 182 operates in synchronism with timing signals supplied to the VC IC 182 from the DMSCD IC 96 via the video timing signal bus 94. (In decompressing compressed video data, the VC IC 72 of the video decompression engine 52 also operates in synchronism with timing signals supplied by the DMSCD IC 96 via the video timing signal bus 94.) To compress the video data received from the DMSCD IC 96, the VC IC 182 first preprocesses that data, supplies the preprocessed video data to both of the VP ICs 184 and 186, and supervises the compression of the video data by the VP ICs 184 and 186. After the VP ICs 184 and 186 compress the video data, the VC IC 182 performs Huffman coding on the compressed video data.

The multi-path memory subsystem 16, illustrated in FIG. 1A, accesses compressed video data produced by the video compression engine 178 in response to signals from the communication subsystem 12. Similar to a transfer of compressed video data from the communication subsystem 12 to the video decompression engine 52 described previously, before transferring compressed video data from the video compression engine 178 the communica¬ tion subsystem 12 first loads appropriate control data into the ATIS cycle control register 22. Then, in response to the control data in the ATIS cycle control register 22 and to addresses from the communication subsystem 12, the multi-path memory subsystem 16 transfers compressed video data from the video compression engine 178 to the communication subsystem 12, to the multi-port memory 28 included in the multi-path memory subsystem 16, or to both the communication subsystem 12 and the multi-port memory 28. After the communication subsystem 12 has received both compressed video data and compressed audio data, it then merges them for transmission over the ISDN line 14.

The combined functions of the video decompression engine 52 and the video compression engine 178 constitutes a video data format conversion subsystem that receives compressed video data and decompresses it into video data, and that also receives video data and converts it into compressed video data. Such a video compression-decompression system may be referred to as a "CODEC." While the video decompression engine 52 and the video compression engine 178 preferably use IIT's VC and VP ICs, that CODEC may also be assembled using other programmable video decompression and compression ICs such as the CL4000 family of ICs marketed by C-Cube Microsystems of Milpitas, California. Because IIT's VCs 72 and 182, and its VPs 74, 184 and 186 all operate under software control, and similarly C-Cube Microsystems' CL4000 family operate under software control, they may be readily adapted to compress or to decompress video data in accordance with various protocols such as H.261, the JPEG or the MPEG standards, or in accordance with a video compression technique developed in the future.

Control of the Subscriber System 10

A control microprocessor 212 illustrated in FIG. IB supervises the operation of the various elements of the subscrib¬ er system 10 described thus far. The control microprocessor 212 is preferably a Motorola MC68EC030 microprocessor that is more completely described in a "Motorola Semiconductor Technical Data" sheet MC68EC030/D, copyright Motorola Inc., 1991, which is incorporated herein by reference. The control microprocessor 212 exchanges control signals with various parts of the subscriber system 10 via a control signal bus 214, a system address bus 216, and a system data bus 218.

To control the operation of the communication subsystem 12, a computer program executed by the control microprocessor 212 exchanges messages through the multi-port memory 28 with a computer program executed by a digital signal processor IC included in the communication subsystem 12. To transfer these messages, the control microprocessor 212 transmits control signals to the multi-port arbitration PAL 42 via the control signal bus 214 requesting access to the multi-port memory 28. The multi-port arbitration PAL 42 responds to such a request from the control microprocessor 212 by transmitting control signals over third multi-path memory subsystem control signal lines 222 to a multiplexer 224 and to a first processor bus bi-directional data buffer 226. The control signals from the multi-port arbitration PAL 42 activate the multiplexer 224 for transferring addresses from the system address bus 216 to the multi-port memory 28 via the multi-port memory address bus 36, and activate the first processor bus bi-directional data buffer 226 for exchanging data between the multi-port memory 28 and the control microprocessor 212 via the multi-port memory data bus 26 and the system data bus 218. As with the first ATIS bi-directional data buffer 24 and second ATIS bi-directional data buffer 62, the control signals from the multi-port arbitration PAL 42 to the first processor bus bi-directional data buffer 226 specify the direction of data exchange between the multi-port memory data bus 26 and the system data bus 218. In this way, the control microprocessor 212 may store messages into the multi-port memory 28 that are subsequently read by the communication subsystem 12, and may fetch messages from the multi-port memory 28 that the communication subsystem 12 previously stored there. When the multiplexer 224 and first processor bus bi-directional data buffer 226 are not activated by control signals from the multi-port arbitration PAL 42, their outputs are tri-stated to allow other portions of the subscriber system 10 access to the multi-port memory 28.

The control microprocessor 212 communicates with the VC ICs 72 and 182, such as for loading computer programs for decom- pressing compressed video data into the VC IC 72 and for compressing video data into the VC IC 182, by transmitting control signals via the control signal bus 214 to the video format conversion subsystem buses PAL 66 requesting access to the video format conversion subsystem address bus 56 and video format conversion subsystem data bus 64. The video format conversion subsystem buses PAL 66 responds to such a request from the control microprocessor 212 by transmitting control signals over fourth multi-path memory subsystem control signal lines 232 to a processor address buffer 234 and to a second processor bus bi-directional data buffer 236. The control signals transmitted from the video format conversion subsystem buses PAL 66 activate the processor address buffer 234 so addresses from the system address bus 216 are transferred to the video format conversion subsystem address bus 56, and activate the second processor bus bi-directional data buffer 236 for exchanging data between the video format conversion subsystem data bus 64 and the system data bus 218. The control signals from the video format conversion subsystem buses PAL 66 to the second processor bus bi-directional data buffer 236 specify the direction of data exchange between the video format conversion subsystem data bus 64 and the system data bus 218. Thus, the computer program executed by the control microprocessor 212 may write data including decompression computer programs to the VC IC 72, may write data including compression computer programs to the VC IC 182, and may read data from both the VC ICs 72 and 182. When the processor address buffer 234 and second processor bus bi-directional data buffer 236 are not activated by control signals from the video format conversion subsystem buses PAL 66, their outputs are tri-stated to allow other portions of the subscriber system 10 access to the video format conversion subsystem address bus 56 and to the video format conversion subsystem data bus 64.

In addition to controlling the operation of the communica¬ tion subsystem 12, the video decompression engine 52, and the video compression engine 178 by commands and data transmitted to them through the multi-path memory subsystem 16; the control microprocessor 212 controls the operation of the DMSCD IC 96 by signals and data transmitted directly over the control signal bus 214. Signals from the control microprocessor 212 may select various features of the DMSCD IC 96 such as enabling the processing either of Phase Alternation Line ("PAL") or of NTSC video signals. Analogously, signals and data transmitted to the DVP IC 92 from the control microprocessor 212 over the control signal bus 214 and the system data bus 218 may specify details of and parameters for window processing performed by the DVP IC 92 on video data that it receives from the video decompression engine 52 and from the video data generation subsystem 98. Similarly, the computer program executed by the control micropro¬ cessor 212 may transmit control signals and data over the control signal bus 214 and the system data bus 218 to the video DAC IC 116.

The subscriber system 10 includes several different types of memories that the control microprocessor 212 accesses via the system address bus 216 and the system data bus 218. The subscriber system 10 includes an 8k byte battery backed RAM 242 for storing configuration information and other data used by the subscriber system 10 when it is initially turned on. The subscriber system 10 also includes a 2M to 4M byte "FLASH" memory 244 organized into 32 bit words for storing the computer programs executed by the communication subsystem 12 and the control microprocessor 212, for storing the decompression computer program executed by the video decompression engine 52, and for storing the compression computer program executed by the video compression engine 178. The subscriber system 10 further includes a 512k byte RAM 246 that is organized as 128k of 32 bit words that are available for general use by the computer program executed by the control microprocessor 212. The subscriber system 10 also includes a 256k byte Erasable Programmable Read Only Memory ("EPROM") 248 for storing the computer program executed by the control microprocessor 212 when it is initially turned on, i.e. "booted." This boot program includes a telecom¬ munications capability that permits the subscriber system 10 to receive, via the ISDN line 14 and the communication subsystem 12, copies of computer programs for storage in the FLASH memory 244. The EPROM 248 also stores a monitor program used for remote debugging and analysis of the subscriber system 10 via the communication subsystem 12 and ISDN line 14. The subscriber system 10 may also include an EPROM 252 which stores data for adapting the subscriber system 10 for operation in foreign languages. Depending upon specific language requirements, the EPROM 252 may contain up to 4M bytes of data.

In addition to coupling the control microprocessor 212 to the various memories, the system address bus 216 and the system data bus 218 couple the control microprocessor 212 to a serial controller IC 262. The serial controller IC 262, preferably a 16C552 manufactured by National Semiconductor of Santa Clara, California, receives signals from a track-ball keypad 264. The track-ball keypad 264 is preferably a PowerTrack 100 marketed by ProHance of Sunnyvale, California. An operator of the subscriber system 10 may use the track-ball keypad 264 for entering commands to control the operation of the subscriber system 10, and also for entering commands to control the operation of a video file server supplying compressed data to the subscriber system 10 over the ISDN line 14. For a more complete description of a video file server adapted for supplying the subscriber system 10 with compressed data, refer to the PCT patent application entitled "Adaptive Video File Server and Methods for Its Use," filed February 11, 1992, in the names of Mark C. Koz and Masato Hata, PCT Patent Application No. PCT/US92/01084, that is incorporated herein by reference. An operator of the subscriber system 10 may use the track-ball keypad 264 to interact with an image presented on the CRT 124 for entering commands by moving a cursor displayed on the CRT 124 for selecting among menu items displayed there. To present an operator with such menus, the computer program executed by the control microprocessor 212 stores appropriate video data into a frame buffer 266, illustrated in FIG. ID. The computer program transmits such video data to the frame buffer 266 via the system address bus 216 and the system data bus 218. The frame buffer 266, which preferably is a 3130 Logic Cell™ Array ("LCA") marketed by Xilinx® of San Jose, California, is preferably programmed to store 485 lines of video data with each line containing 720 bits of video data. Operating in synchronism with video timing signals supplied to the frame buffer 266 over the video timing signal bus 94, the frame buffer 266 supplies video data to a graphics frame buffer interface of the video DAC IC 116. To present on the CRT 124 video data transmitted from the frame buffer 266, the computer program executed by the control microprocessor 212 appropriately programs the video DAC IC 116 via the control signal bus 214 and the system data bus 218.

The serial controller IC 262 also provides a RS-232C serial port 268 illustrated in FIG. IB. The serial port 268 permits communication between the subscriber system 10 and various different types of devices including personal computers. By communicating with the subscriber system 10 through the serial port 268, a personal computer may use the subscriber system 10 as an ISDN modem for exchanging data with other computers. In addition to the track-ball keypad 264 and the serial port 268, the subscriber system 10 includes a Sony S-Control™ bus plug 276, illustrated in FIG. IB, for interconnecting and exchanging control signals with a variety of different devices including video devices. The S-Control bus plug 276 permits such devices to exchange control signals directly with the control micropro¬ cessor 212 via the control signal bus 214. The component VCR 164 illustrated in FIG. IC exemplifies a video device whose operation may be controlled by signals transmitted through the S-Control bus plug 276. Depending upon precise details of the computer program executed by the control microprocessor 212, a VCR or a component VCR connected either to the composite video signal output line 128 or to the video output signal bus 136 can automa¬ tically record video images transmitted to the subscriber system 10 via the ISDN line 14. Similarly, depending upon precise details of the computer program executed by the control micropro¬ cessor 212, upon precise details of whether the component VCR 164 is connected to the composite video signal output line 128 or to the video output signal bus 136, and upon precise details of whether the line 128 or the bus 136 are suitably connected respectively to the component VCR 164; control signals supplied through the S-Control bus plug 276 may cause the subscriber system 10 to operate as a telephone answering machine for video telephone communications. Updating Computer Programs

As mention above, a subscriber system 10 in accordance with the present invention may receive by telecommunications via the ISDN line 14 and the communication subsystem 12 various computer programs executed by the communication subsystem 12, by the control microprocessor 212, and by the subsystems 58 and 178. Thus, each time the subscriber system 10 communicates with a suitable centralized facility such as a video file server, that facility may interrogate the subscriber system 10 to determine if it is executing the most recent versions of the various computer programs. If it is determined that the computer programs being executed by the subscriber system 10 should be upgraded, then the centralized facility may transmit newer versions to the subscriber system 10 over the ISDN line 14 for storage in the FLASH memory 244. ..In view of the anticipated evolution of video compression anlgorithms and of protocols for telecommunication of audio-visual data, the ability to upgrade the computer programs executed by various subsystems included in the subscriber system 10 facilitates adapting it for operation in an environment of evolving standards.

Audio Decompression and Compression

To generate an audible output signal for the subscriber system 10, the computer program executed by the digital signal processor IC included in the ISDN line 14 stores compressed audio data into the multi-port memory 28. When the communication subsystem 12 notifies the control microprocessor 212 that compressed audio data has been stored in the multi-port memory 28, the control microprocessor 212 communicates with the multi-path memory subsystem 16 to retrieve such data from the multi-port memory 28 in substantially the same way as it retrieves messages stored there by the communication subsystem 12. After retrieving compressed audio data from the multi-port memory 28, the computer program executed by the control micropro- cessor 212 transfers such data to an audio data format conversion subsystem 282 for decompression into audio data. The audio data format conversion subsystem 282 includes a TMS320C31 Digital Signal Processor IC for decompressing compressed audio data. The TMS320C31 digital signal processor is more completely described in a "Texas Instrument DSP Hand Book" and is manufactured by Texas Instruments Incorporated of Dallas, Texas. In addition to the TMS320C31 IC, each audio data format conversion subsystem 282 also includes static RAM that is not separately illustrated in FIG. IB. Analogous to the video decompression engine 52 and the video compression engine 178, the computer program executed by the control microprocessor 212 can store a selected one of several different computer programs for decompressing compressed audio data, or for compressing audio data, into the audio data format conversion subsystem 282 for execution by its TMS320C31 IC. Each such computer program may be adapted for decompressing compressed audio data or for compressing audio data in accordance with a pre-specified compression technique such as the CCITT Recommendation G.711 or G.722 that respectively establish standards for transmitting audio data over an ISDN communication channel.

Audio data obtained by decompressing compressed audio data with the audio data format conversion subsystem 282 is trans it- ted from the audio data format conversion subsystem 282 to an audio signal/data generation subsystem 284 via an audio data output bus 286. Within the audio signal/data generation subsystem 284, the audio data is supplied over the audio data output bus 286 to two audio DACs 288A and 288B included in a CS4215 Stereo Audio Codec IC 292. The Stereo Audio Codec IC 292 is marketed by Crystal Semiconductor Corporation of Austin, Texas. Upon receiving the audio data from the audio data format conversion subsystem 282, responsive to control signals received from the control microprocessor 212 via the control signal bus 214, the audio DACs 288A and 288B convert the digitized audio data into audio signals. Audio signals produced by the audio DACs 288A and 288B are supplied directly both to a line-out jack 294 and to a headphone jack 296. The line-out audio signal produced by the audio DAC 288A is also supplied to a telephone interface circuit 298. The audio DAC 288A also supplies an audio output signal to a speaker 302 for producing an audible sound.

Because the Stereo Audio Codec IC 292 includes two audio DACs 288A and 288B, by supplying stereo audio data from the audio data format conversion subsystem 282 to both of the audio DACs 288A and 288B the audio signal present at the line-out jack 294 can be a stereo signal rather than merely a monaural signal. Moreover, connecting the line-out jack 294 to audio inputs of a VCR 164 connected either to the composite video signal output line 128 or to the video output signal bus 136 permits recording both the video and audio information present in compressed data received by the subscriber system 10.

The subscriber system 10 also includes a microphone 304 that produces an audio signal in response to an audible sound. The microphone 304 supplies its audio signal to an ADC 306A that is one of two ADCs 306A and 306B included in the Stereo Audio Codec IC 292. A stereo audio signal may be supplied directly to both ADCs 306A and 306B from a line-in jack 308. The telephone interface circuit 298 supplies only.a single audio signal to the ADC 306A. Responsive to control signals received from the control microprocessor 212 via the control signal bus 214, the ADCs 306A and 306B digitize the audio signals received either from the microphone 304, from the line-in jack 308, or from the telephone interface circuit 298 to generate audio data. The audio data generated by the ADCs 306A and 306B is then transmit¬ ted via an audio data input bus 312 to the audio data format conversion subsystem 282.

Upon receiving audio data from the ADCs 306A and 306B, the computer program executed by the digital signal processor included in the audio data format conversion subsystem 282 compresses the audio data in accordance with a compression standard selected from the various different existing audio compression standards, or in accordance with an audio compression technique developed in the future. The compressed audio data thus produced by the audio data format conversion subsystem 282 is then transferred by the control microprocessor 212 from the audio data format conversion subsystem 282 to the multi-port memory 28. The communication subsystem 12 then fetches the compressed audio data from the multi-port memory 28 and merges it with compressed video data from the video compression engine 178 for transmission from the subscriber system 10 over the ISDN line 14. If the subscriber system 10 is not transmitting compressed audio data, the TMS320C31 included in the audio data format conversion subsystem 282 is capable of decompressing two channels of compressed stereo audio data. Similarly, if the subscriber system 10 is not receiving compressed audio data, the TMS320C31 can compress two channels of stereo audio data. However, if the subscriber system 10 operates as a video telephone to both receive and transmit compressed data containing both compressed video data and compressed audio data, the TMS320C31 can decom- press only a single channel of compressed audio data for transmission to the audio DAC 288A while concurrently compressing a single channel of audio data received from the ADC 306A.

The telephone interface circuit 298 receives an audio signal from the Stereo Audio Codec IC 292 and may supply an audio signal to the Stereo Audio Codec IC 292. The telephone interface circuit 298 supplies an audio signal to and receives an audio signal from a RJ-11 telephone jack 316 included in the subscriber system 10. Inclusion of the RJ-11 telephone jack 316 in the subscriber system 10 permits a conventional telephone or fac- simile machine to communicate via the ISDN line 14.

In addition to decompressing and compressing audio data, the TMS320C31 included in the audio data format conversion subsystem 282 also generates Dual Tone Multi Frequency ("DTMF") signals in response to commands received from the control microprocessor 212. DTMF signals are used for telephone dialing, and may be used to transmit commands such as for controlling the transmis¬ sion of compressed video data from a video file server.

Microprocessor Generated Sounds The subscriber system 10 also includes a sound generator IC 318 that responds to control signals and data respectively transmitted from the control microprocessor 212 to the sound generator IC 318 over the control signal bus 214 and the system data bus 218. The sound generator IC 318 is preferably a Yamaha YM3812 FM Operator Type-LII ("OPL II") IC manufactured by Nippon Gakki Co., Ltd. The sound generator IC 318 produces an audio signal that is supplied to one contact of the line-out jack 294 for producing an audible sound. A primary use of the sound generator IC 318 by the computer program executed by the control microprocessor 212 is for generating sounds to accompany computer generated images appearing on the CRT 124 such as during the presentation of a video game. As described previously, the computer program executed by the control microprocessor 212 may generate such images on the CRT 124 by storing appropriate video data into the frame buffer 266 and appropriately enabling the video DAC IC 116 to display such data.

Auxiliary Storage Devices

The subscriber system 10 includes a SCSI controller IC 332 that exchanges control signals with the control microprocessor 212 via the control signal bus 214, receives addresses from the control microprocessor 212 via the system address bus 216, and exchanges data with the control microprocessor 212 via the system data bus 218. Preferably, the SCSI controller IC 332 is a MB86601 SCSI protocol controller manufactured by Fujitsu VLSI Inc. The SCSI controller IC 332 also exchanges control signals with the multi-port arbitration PAL 42 of the multi-path memory subsystem 16 via fifth multi-path memory subsystem control signal lines 336, and data with the multi-port memory 28 of the multi-path memory subsystem 16 via the multi-port memory data bus 26. The interface in the SCSI controller IC 332 that receives data from or transmits data to the multi-port memory data bus 26 may be tri-stated by control signals transmitted from the multi-port arbitration PAL 42 via the fifth multi-path memory subsystem control signal lines 336 to allow other portions of the subscriber system 10 access to the multi-port memory 28.

The SCSI controller IC 332 provides a SCSI-2 bus 338 that connects to a Floptical disk drive 342 preferably included in the subscriber system 10, and to an external SCSI connector 344. The SCSI controller IC 332 and external SCSI connector 344 permit the subscriber system 10 to exchange commands and data with a variety of different computer peripheral devices such as hard and/or floppy disk drives, a Digital Audio Tape ("DAT") drive, a CD-ROM drive, an optical disk unit, a printer, a scanner, a plotter, etc. Accordingly, the subscriber system 10 may include one or more of these other types of devices connected to the SCSI-2 bus 338. Specifically the subscriber system 10 may include any of the auxiliary storage devices identified above instead of or in addition to the Floptical disk drive 342.

To facilitate data transfers between the SCSI controller IC 332 and the multi-port memory 28 of the multi-path memory subsystem 16, the multi-path memory subsystem 16 includes a SCSI DMA counter 348. To store on an auxiliary storage device connected to the SCSI-2 bus 338 a block of compressed data that is passing through the multi-path memory subsystem 16 either from the communication subsystem 12 to the video decompression engine 52 and the audio data format conversion subsystem 282, or from the video compression engine 178 and in the audio data format conversion subsystem 282 to the communication subsystem 12; the computer program executed by the control microprocessor 212 first requests configuration of the multi-path memory subsystem 16 for exchanging data with the SCSI controller IC 332 by transmitting a message to the communication subsystem 12 via the multi-port memory 28. After each block of data is completely present in the multi-port memory 28, the computer program executed by the control microprocessor 212 initializes the SCSI controller IC 332 and the SCSI DMA counter 348 for DMA operation. During DMA data exchanges between the multi-port memory 28 and the SCSI control¬ ler IC 332, the SCSI DMA counter 348 specifies the address of data to the multi-port memory 28 via a DMA address bus 352, the multiplexer 224, and the multi-port memory address bus 36.

Thus, the multi-path memory subsystem 16 permits compressed audio-visual data received by the ISDN line 14 to be concurrently displayed on the CRT 124, audiblized on the speaker 302 and recorded on an auxiliary storage device connected to the SCSI-2 bus 338 with only a minimal involvement of the control micropro¬ cessor 212. That is, after configuring the operation of the multi-path memory subsystem 16 by transmitting a suitable message to the communication subsystem 12 via the multi-port memory 28, the control microprocessor 212 need only transfer each successive block of compressed audio data from the multi-port memory 28 to the audio data format conversion subsystem 282 and initialize the operation of the SCSI controller IC 332 and SCSI DMA counter 348 for storing each successive block of compressed data on the auxiliary storage device. In concurrently receiving compressed data from the communication subsystem 12 and transmitting it to the video decompression engine 52, storing it into the multi-port memory 28, permitting the control microprocessor 212 to access a previously stored block of compressed audio data in the multi-port memory 28 for transfer to the audio data format conversion subsystem 282, and also transmitting compressed data to the SCSI controller IC 332 from a previously stored block of compressed data in the multi-port memory 28; the multi-port arbitration PAL 42 of the multi-path memory subsystem 16 interleaves the various accesses to the multi-port memory 28 that are required to perform each of these data transfers. Thus, in performing these respective transfers the communication subsystem 12, the control microprocessor 212 and the SCSI controller IC 332 each operates independently as though it had exclusive access to the multi-port memory 28 while the multi-port arbitration PAL 42 invisibly shares the multi-port memory 28 among them.

Operation of the subscriber system 10 for transmitting compressed audio-visual data while concurrently recording it on an auxiliary storage device is similar to that described above for receiving compressed data except that blocks of compressed data that are stored into the multi-port memory 28 before being transmitted to the SCSI controller IC 332 originate respectively in the video compression engine 178 and in the audio data format conversion subsystem 282 rather than in the communication subsystem 12. Operation of the subscriber system 10 for replaying compressed audio-visual data previously recorded on an auxiliary storage device and/or for transmission from the subscriber system 10 via the ISDN line 14 is the converse of that described above for recording data. That is, the multi-path memory subsystem 16 first receives a block of compressed data from the SCSI controller IC 332 and stores it into the multi-port memory 28 before the communication subsystem 12 accesses it for transmission to the ISDN line 14 and/or accesses the compressed video portion of the data for transmission to the video decom¬ pression engine 52, and before the control microprocessor 212 accesses the compressed audio portion of the data for transmis¬ sion to the audio data format conversion subsystem 282. To coordinate accesses to the multi-port memory 28, three independent state machines operate within the multi-port arbitration PAL 42. A first state machine arbitrates among the communication subsystem 12, the control microprocessor 212, and the SCSI controller IC 332 to determine which of them the multi-path memory subsystem 16 will respond at any instant. If the first state machine determines that the multi-path memory subsystem 16 will effect an exchange of data between the multi-port memory 28 and the SCSI controller IC 332, then the second state machine operates to effect that exchange. If the first state machine determines that the SCSI controller IC 332 will not exchange data with the multi-port memory 28 and either or both of the communication subsystem 12 and the control microprocessor 212 have requested an exchange of data with the multi-port memory 28, then the third state machine operates to effect such an exchange either with the communication subsystem 12 or with the control microprocessor 212. As stated previously, signals transmitted from the multi-port arbitration PAL 42 to the video format conversion subsystem buses PAL 66 via video conversion buses mode signal lines 67 indicate whether data is to be concurrently exchanged between the ATIS data bus 18 and the video format conversion subsystem data bus 64. A state machine operating in the video format conversion subsystem buses PAL 66 independently arbitrates whether data will be exchanged between the video format conversion subsystem data bus 64 and either the ATIS data bus 18 or the system data bus 218. Signals exchanged via the multi-path synchronization lines 70 coordinate the operation of the various state machines operating in the multi-port arbitration PAL 42 and in the video format conversion subsystem buses PAL 66 to insure proper completion of concurrent data exchanges with the multi-port memory 28 and with the video decompression engine 52 or the video compression engine 178. For example, if data from a block previously stored into the multi-port memory 28 by the SCSI controller IC 332 is concurrent- ly being transferred both to the communication subsystem 12 and to the video decompression engine 52, then the state machine in the multi-port arbitration PAL 42 that effects the transfer of data from the multi-port memory 28 to the communication subsystem 12 cannot complete that exchange until receiving a notification from the state machine operating in the video format conversion subsystem buses PAL 66 via the multi-path synchronization lines 70 that the data transfer has been completed to the video decompression engine 52. Similar considerations apply to other data transfers that concurrently exchange data both with the multi-port memory 28 and with either the video decompression engine 52 or the video compression engine 178.

Industrial Applicability

As described above, the communication subsystem 12 may configure the multi-path memory subsystem 16 both for transmit¬ ting compressed video data received from the communication subsystem 12 to the video decompression engine 52, and for concurrently storing such data into the multi-port memory 28 for subsequent transfer to an auxiliary storage device via the SCSI controller IC 332. However, data from the communication subsystem 12 that the multi-path memory subsystem 16 has stored into the multi-port memory 28 may be used for other purposes. For example, if a color printer is attached to the subscriber system 10 via the external SCSI connector 344, then the subscrib¬ er system 10 may transfer data from the multi-port memory 28 to such a color printer thereby producing a color copy of an image on paper. Accordingly, the capability of the multi-path memory subsystem 16 to preserve a copy of video data in the multi-port memory 28 and concurrently facilitate the production of an image from such data on the CRT 124 adapts the subscriber system 10 to use data preserved in the multi-port memory 28 for purposes in addition to those specifically disclosed herein. Analogous other uses for compressed data transferred through the multi-path memory subsystem 16 in its two other multi-path operating modes exist in addition to those specifically described herein.

While the subscriber system 10 described above specifically focuses on the use of a CRT 124 for displaying images, the subscriber system 10 may be readily adapted to display images on all other forms of electronic display technology such as projection television displays, liquid crystal displays ("LCDs") and plasma panel displays. While the preceding disclosure has been generally made with reference to an ISDN line 14, the subscriber system 10 of the present invention may be readily adapted for use with other comparatively narrow bandwidth communication channels other than ISDN communication channels. Such alternative communication channels include mere twisted wire pairs within only a single building or a portion of a building, for example, a school or a Karaoke business establishment. Conversely, the subscriber system 10 of the present invention is also readily adaptable for use with digital communication channels capable of much higher data transfer rates than that provided by ISDN primary access. Thus, it is envisioned that the subscriber system 10 of the present invention may be readily adapted for communicating over a Very Small Aperture Terminal ("VSAT") communication channel, or over any type of digital communication channel, including both electronic or optical digital communication channels whether dedicated or shared, including shared digital communication channels provided by local area networks such as Ethernet®, token ring, or ArcNet®. Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is purely illustrative and is not to be interpreted as limiting. Consequently, without departing from the spirit and scope of the invention, various alterations, modifications, and/or alternative applications of the invention will, no doubt, be suggested to those skilled in the art after having read the preceding disclosure. Accordingly, it is intended that the following claims be interpreted as encompassing all alterations, modifications, or alternative applications as fall within the true spirit and scope of the invention.

Claims

The ClaimsWhat is claimed is:

1. A subscriber system adapted for receiving compressed data and for concurrently generating from the received data video and audio signals respectively adapted for producing a visible image and an audible sound, said subscriber system comprising: a control microprocessor for controlling the operation of the subscriber system; a communication subsystem, responsive to commands from said control microprocessor, for receiving compressed data transmitted to said subscriber system, and for separating compressed data into compressed video data and compressed audio data; a video data format conversion subsystem, responsive to commands from said control microprocessor, for receiving compressed video data and for converting received compressed video data into video data; a multi-path memory subsystem including a multi-port memory, said multi-path memory subsystem being responsive to commands from said control microprocessor and being coupled to said control microprocessor, to said communication subsystem, and to said video data format conversion subsystem for receiving, in a first operating mode of said multi-path memory subsystem, com¬ pressed video data and compressed audio data from said communica- tion subsystem, for storing such compressed video data and audio data into said multi-port memory, and for concurrently supplying such compressed video data to said video data format conversion subsystem; a video signal generation subsystem, responsive to commands from said control microprocessor, for receiving video data from said video data format conversion subsystem, and for generating from the received video data a video signal adapted for producing a visible image; an audio data format conversion subsystem, responsive to commands from said control microprocessor, for receiving compressed audio data, and for converting received compressed audio data into audio data; and an audio signal generation system, responsive to commands from said control microprocessor, for receiving audio data from said audio data format conversion subsystem, and for generating from the received audio data an audio signal adapted for producing an audible sound.

2. The subscriber system of claim 1 wherein said multi-path memory subsystem operates in a plurality of modes.

3. The subscriber system of claim 2 wherein said communi¬ cation subsystem specifies in which one of the plurality of modes said multi-path memory subsystem operates.

4. The subscriber system of claim 3 wherein said multi-path memory subsystem includes a control register into which said communication subsystem stores data for specifying the mode in which said multi-path memory subsystem operates.

5. The subscriber system of claim 2 further comprising a video data generation subsystem, responsive to commands from said control microprocessor, for receiving a video signal obtained from a visible image, and for generating video data from said received video signal; and wherein said video data format conversion subsystem generates compressed video data from video data generated by said video data generation subsystem, and said multi-path memory subsystem receives, in a second operating mode of said multi-path memory subsystem, compressed video data from said video data format conversion subsystem, stores such compressed video data into said multi-port memory, and concur- rently supplies such compressed video data to said communication subsystem.

6. The subscriber system of claim 5 wherein said multi-path memory subsystem, in another operating mode, stores compressed data including compressed video data and compressed audio data into said multi-port memory, supplies said communica¬ tion subsystem with compressed data from said multi-port memory, and concurrently supplies said video data format conversion subsystem with compressed video data from said multi-port memory.

7. The subscriber system of claim 2 wherein said multi-path memory subsystem, in another operating mode, stores compressed data including compressed video data and compressed audio data into said multi-port memory, supplies said communica¬ tion subsystem with compressed data from said multi-port memory, and concurrently supplies said video data format conversion subsystem with compressed video data from said multi-port memory.

8. The subscriber system of claim 1 further comprising a controller, responsive to commands from said control microproces¬ sor, adapted for exchanging compressed data between the subscrib- er system and an auxiliary storage device.

9. The subscriber system of claim 8 wherein the controller exchanges compressed data directly with said multi-port memory of said multi-path memory subsystem.

10. The subscriber system of claim 9 further comprising an auxiliary storage device.

11. A subscriber system adapted for converting a video signal into compressed video data and for concurrently transmit¬ ting the compressed video data from said subscriber system, said subscriber system comprising: a control microprocessor for controlling the operation of the subscriber system; a video data generation subsystem, responsive to commands from said control microprocessor, for receiving a video signal obtained from a visible image, and for generating video data from said received video signal; a compressed video data generation subsystem, responsive to commands from said control microprocessor, for receiving the video data generated by said video data generation subsystem and generating compressed video data from the received video data; a multi-path memory subsystem including a multi-port memory, said multi-path memory subsystem being responsive to commands from said control microprocessor and being coupled to said control microprocessor, to said communication subsystem, and to said compressed video data generation subsystem for receiving, in a first operating mode of said multi-path memory subsystem, compressed video data from said compressed video data generation subsystem, for storing such compressed video data into said multi-port memory, and for concurrently supplying such compressed video data to a communication subsystem; said communication subsystem, responsive to commands from said control microprocessor, receiving from said multi-path memory subsystem compressed video data generated by said compressed video data generation subsystem, and transmitting such compressed video data from the subscriber system.

12. The subscriber system of claim 11 wherein said multi-path memory subsystem operates in a plurality of modes.

13. The subscriber system of claim 12 wherein said communication subsystem specifies in which one of the plurality of modes said multi-path memory subsystem operates.

14. The subscriber system of claim 13 wherein said multi-path memory subsystem includes a control register into which said communication subsystem stores data for specifying the mode in which said multi-path memory subsystem operates.

15. The subscriber system of claim 11 further comprising a controller, responsive to commands from said control micropro¬ cessor, adapted for exchanging compressed data between the subscriber system and an auxiliary storage device.

16. The subscriber system of claim 15 wherein the control- ler exchanges compressed data directly with said multi-port memory of said multi-path memory subsystem.

17. The subscriber system of claim 16 further comprising an auxiliary storage device.

18. A subscriber system adapted for producing a visible image and an audible sound from stored compressed data and for concurrently transmitting such compressed data from said subscriber system, said subscriber system comprising: a control microprocessor for controlling the operation of the subscriber system; a multi-path memory subsystem including a multi-port memory, said multi-path memory subsystem being responsive to commands from said control microprocessor and being coupled to said control microprocessor, said multi-path memory subsystem storing compressed data including compressed video data and compressed audio data into said multi-port memory; a communication subsystem, responsive to commands from said control microprocessor and coupled to said multi-path memory subsystem, for receiving from said multi-path memory subsystem compressed data stored into said multi-port memory; a video data format conversion subsystem, responsive to commands from said control microprocessor and coupled to said multi-path memory subsystem, for receiving compressed video data from said multi-path memory subsystem concurrently with the receipt of such data by said communication subsystem and for converting received compressed video data into video data; a video signal generation subsystem, responsive to commands from said control microprocessor, for receiving video data from said video data format conversion subsystem, and for generating from the received video data a video signal adapted for producing a visible image; an audio data format conversion subsystem, responsive to commands from said control microprocessor, for receiving compressed audio data, and for converting received compressed audio data into audio data; and an audio signal generation system, responsive to commands from said control microprocessor, for receiving audio data from said audio data format conversion subsystem, and for generating from the received audio data an audio signal adapted for producing an audible sound.

19. The subscriber system of claim 18 wherein said multi-path memory subsystem operates in a plurality of modes.

20. The subscriber system of claim 19 wherein said communication subsystem specifies in which one of the plurality of modes said multi-path memory subsystem operates.

21. The subscriber system of claim 20 wherein said multi-path memory subsystem includes a control register into which said communication subsystem stores .data for specifying the mode in which said multi-path memory subsystem operates.

22. The subscriber system of claim 18 further comprising a controller, responsive to commands from said control micropro¬ cessor, adapted for exchanging compressed data between the subscriber system and an auxiliary storage device.

23. The subscriber system of claim 22 wherein the control¬ ler exchanges compressed data directly with said multi-port memory of said multi-path memory subsystem.

24. The subscriber system of claim 23 further comprising an auxiliary storage device.

25. A method for producing a visible image and an audible sound from compressed data comprising the steps of: receiving compressed data with a communication subsystem; separating compressed data into compressed video data and compressed audio data; supplying the compressed video and audio data to a multi-path memory subsystem, the multi-path memory subsystem, operating in a first mode, storing such compressed data into a multi-port memory and concurrently supplying the compressed video data to a video data format conversion subsystem; converting the compressed video data into video data in the video data format conversion subsystem; generating a video signal adapted for producing a visible image from the video data; converting the compressed audio data into audio data; and generating an audio signal adapted for producing an audible sound from the audio data.

26. The method of claim 25 wherein the multi-path memory subsystem operates in a plurality of different modes, the communication subsystem specifying in which one of such modes the multi-path memory subsystem operates.

27. The method of claim 26 wherein the multi-path memory subsystem includes a control register, the communication subsystem storing data into the control register that specifies the mode in which the multi-path memory subsystem operates.

28. The method of claim 25 further comprising the steps of: receiving a video signal representing a visible image, generating video data from the video signal, and supplying the video data thus generated to the video data format conversion subsystem; converting the video data generated from the video signal of the visible image into compressed video data in the video data format conversion subsystem; and the multi-path memory subsystem, operating in a second mode, receiving the compressed video data from the video data format conversion subsystem, storing such data into the multi-port memory, and concurrently supplying such data to the communication subsystem.

29. The method of claim 28 further comprising the steps of the multi-path memory subsystem, operating in another mode, storing compressed data including compressed video data and compressed audio data into the multi-port memory, supplying the communication subsystem with compressed data from the multi-port memory, and concurrently supplying the video data format conversion subsystem with compressed video data from the multi-port memory.

30. The method of claim 25 further comprising the steps of the multi-path memory subsystem, operating in another mode, storing compressed data including compressed video data and compressed audio data into the multi-port memory, supplying the communication subsystem with compressed data from the multi-port memory, and concurrently supplying the video data format conversion subsystem with compressed video data from the multi-port memory.

31. The method of claim 25 further comprising the step of the multi-path memory subsystem exchanging compressed data with an auxiliary storage device via a controller.

32. The method of claim 31 wherein the controller exchanges compressed data directly between the auxiliary storage device and the multi-port memory.

33. A method for producing compressed video data of a visible image and transmitting such compressed data comprising the steps of: receiving a video signal representing a visible image and generating video data from the video signal; generating compressed video data from the video data; supplying the compressed video data to a multi-path memory subsystem, the multi-path memory subsystem storing such com¬ pressed data into a multi-port memory and concurrently supplying the compressed video data to a communication subsystem; transmitting the compressed video data from the communica¬ tion subsystem.

34. The method of claim 33 wherein the multi-path memory subsystem operates in a plurality of different modes, the communication subsystem specifying in which one of such modes the multi-path memory subsystem operates.

35. The method of claim 24 wherein the multi-path memory subsystem includes a control register, the communication subsystem storing data into the control register that specifies the mode in which the multi-path memory subsystem operates.

36. The method of claim 33 further comprising the step of the multi-path memory subsystem exchanging compressed data with an auxiliary storage device via a controller.

37. The method of claim 36 wherein the controller exchanges compressed data directly between the auxiliary storage device and the multi-port memory.

38. A method for reproducing and transmitting compressed video and audio data comprising the steps of: storing compressed data including compressed video data and compressed audio data into a multimport memory of a multi-path memory subsystem; the multi-path memory subsystem supplying the compressed data to a communication subsystem for transmission; concurrent with supplying compressed data to the communica- tion subsystem, the multi-path memory subsystem supplying compressed video data to a video data format conversion subsys¬ tem; converting the compressed video data into video data in the video data format conversion subsystem; generating a video signal adapted for producing a visible image from the video data; the multi-path memory subsystem supplying compressed audio data to an audio data format conversion subsystem; converting the compressed audio data into audio data in the audio data format conversion subsystem; and generating an audio signal adapted for producing an audible sound from the audio data.

39. The method of claim 38 wherein the multi-path memory subsystem operates in a plurality of different modes, the communication subsystem specifying in which one of such modes the multi-path memory subsystem operates.

40. The method of claim 39 wherein the multi-path memory subsystem includes a control register, the communication subsystem storing data into the control register that specifies the mode in which the multi-path memory subsystem operates.

41. The method of claim 38 further comprising the step of the multi-path memory subsystem exchanging compressed data with an auxiliary storage device via a controller.

42. The method of claim 41 wherein the controller exchanges compressed data directly between the auxiliary storage device and the multi-port memory.