WO1994005089A1

WO1994005089A1 - A bandpass decimation filter suitable for multiple protocols

Info

Publication number: WO1994005089A1
Application number: PCT/US1993/007860
Authority: WO
Inventors: Tim A. Williams
Original assignee: Wireless Access, Inc.
Priority date: 1992-08-25
Filing date: 1993-08-20
Publication date: 1994-03-03

Abstract

A novel bandpass decimator for communication receivers and efficient implementation in VLSI. The bandpass decimator can serve as a decimation filter (303I and 304I) for alternately receiving different protocols. The decimator's characteristics can be electrically modified to accommodate these various protocols. I and Q channels are converted at selectable rates according to the required precision and rate, where the precision is typically higher than that of the composite signal and the rate is typically much lower than the composite signal, hence a decimation of signal rates.

Description

A BANDPASS DECIMATION FILTER SUITABLE FOR MULTIPLE PROTOCOLS

INTRODUCTION

Background

This invention pertains to communication receivers, and more specifically to the creation of an in-phase (I) and quadrature (Q) channels from non-baseband information. The invention is suitable for use in a communications receiver which is capable of being electrically adapted for use in receiving a variety of communications modulation techniques or "protocols. "

Figure 1 is a graph depicting the frequency content of a typical composite signal which requires decimation to baseband. Such a signal is obtained, for example, by the use of an analog to digital converter which has a bandpass sensitivity to the desired information signal which is being converted to a digital signal . Centered around carrier frequency ω„ is the information signal of interest which has a bandwidth BW. Because of the method in which this composite signal was obtained, i.e. the use of an oversampled sigma-delta converter, there is a shaped or colored noise signal which is an additive noise element to the desired signal, labeled X_L. This noise signal is the "shaped noise" which results from a conversion of signals from analog to digital using a bandpass sigma delta modulator loop. It is desired to filter the desired information signal from the noise present in the composite signal. When the information signal was created at the originating transmitter, the information was modulated with an in-phase and a quadrature signal, e.g. cosω_c and -sinω_c. The demodulation of the in-phase and quadrature information from the composite signal is also desired.

Decimation of digital signals from higher data rates to lower data rates is well known in the prior art and is described in "Interpolation and Decimation of Digital Signals - A Tutorial Review", R.E. Crochiere and L.R. Rabiner, Proceeding of the IEEE Vol.69, No. 3, March 1981. Because of the nature of the modulation signals being received there is a need to recover the frequency and phase of the clock signal which was utilized to transmit the information signal . Maintaining clock synchronization between the transmitter and the receiver is important in communication systems since the performance of the system can be traced to the accuracy of the clocks. In a communications system the clock phase and frequency are not transmitted to the receiver—only the data is transmitted. Thus the transmitter's clock frequency and phase must be determined at the receiver based on the received data. This is called timing recovery and is typically implemented with a digital phase locked loop (DPLL) . The DPLL tracks the phase and frequency offset between the transmitter and the receiver clocks and either advances or retards the receiver clock in order to maintain synchronism. The difficulty of determining the transmit clock phase and frequency from the received data only, as well as methods for implementing the timing recovery loop, are discussed in "Digital Communication", by Edward Lee and David Messerschmitt, Kluwer, 1990, Chapter 15.

Prior art implementations of this timing recovery function convert the bandpass signal to baseband by mixing it with ω_c, then recovering the timing information. However, since the receiver is implemented as a sampled data system, the process of converting the signal to baseband will destroy the transmit clock frequency and phase information. Thus the only prior art practical method of timing recovery is to operate the decimator at a much higher sampling rate than is required in the present invention to obtain the desired binary data state at known intervals synchronized to the transmitter clock. Using a higher sampling rate provides a plurality of sample points within each bit cell, and thus allows a minimum or maximum to be selected for use as the recovered data bit. In such a prior art technique, sampling rates of 16 to 32 times greater than the sampling rate required if the transmitter clock is recovered and available for data detection, is required. Such prior art techniques consume too much power and size since the circuitry must be made to operate at a higher clock rate than necessary when the transmitter clock is recovered for use by the receiver.

An example of a baseband decimator is described in "A novel architecture design for VLSI implementation of an FIR decimation filter", Hanafy Meleis and, Peirrer LeFur, ICASSP 1985 pp. 1380-1383. This paper describes a VLSI implementation of a baseband lowpass FIR decimation filter for use with a baseband sigma delta converter. Their implementation uses three adders, shown in figure 5 of the paper, and a coefficient generator, shown in figure 2 of the paper, to implement a sine³ filter. The use of three adders is determined by the number of zeros required at the re¬ sampling rate, which is a function of the order of the sigma delta modulation loop which precedes this circuit. For example, a second order loop requires a third order decimation circuit, hence the use of three adders as described in the paper.

An example of a bandpass decimator circuit is described in

"Decimation for Bandpass Sigma-Delta Analog-to-Digital Conversion", by Richard Schreier and W. Martin Snelgrove,

ICCAS 1990, pp. 1801-1804. This paper discusses the difference between the lowpass and bandpass decimation filter types, and describes a structure for accomplishing bandpass decimation. The structures described in this paper do not consider the difficulties in dealing with a recovered clock and assume that the center frequency ω_c is stable and known. Unfortunately, these assumptions do not apply in practical communications receivers.

Summary

The present invention teaches a novel bandpass decimator which can be utilized in communication receivers and can be efficiently implemented in VLSI circuits. The present invention is designed such that it can serve as a decimation filter for alternately receiving different protocols, such as a fax signal, a cellular telephone signal, a paging signal and the like. The decimator's characteristics can be electrically modified to accommodate these various protocols. The present invention relates to information signals which are bandpass in nature, as opposed to lowpass, and thus the signal of interest is centered at a frequency which is other than DC. The composite received signal Y, which contains the information signal, is generated by a sigma delta modulator which has a low precision, e.g. one bit, and a high rate, e.g. ω_sample. The precision and rates required for the I and Q channels are determined by the type of modulation which is being received. The present invention converts the I and Q channels at selectable rates according to the required precision and rate where the precision is typically higher than that of the composite signal and the rate is typically much lower than the composite signal, hence a decimation of the composite signal is required to generate the I and Q channels.

The composite input signal is obtained from a sigma delta loop, and has a low precision, e.g. one bit, and a high rate, e.g. ω_sample. The precision and rates required by the I and Q channels are determined by the type of modulation which is being received. The present invention selectively converts the I and Q channels according to the required precision and rate where the precision is typically higher than that of the composite signal and the rate is typically much lower than the composite signal, hence a decimation of signal rates.

A novel and efficient implementation of recovering this transmit clock information from a received information signal is also taught .

Brief Description of the Drawings

Figure 1 shows a description of a typical composite input signal which must be filtered and decimated for the I and Q channels;

Figure 2 is a block diagram of one embodiment of the present invention; and

Figure 3 shows in detail one embodiment of the present invention;

Figure 4 shows a detail section of Figure 3 ; and

Figure 5 is a timing diagram depicting the timing relationship between a plurality of three branches.

Detailed Description

Figure 2 depicts a block diagram of one embodiment of a bandpass decimation filter constructed in accordance with the teachings of the present invention, and includes timing recovery circuitry and circuitry for decimation by two of the I and Q channels.

A composite signal Y as shown generally in Fig. 1 is obtained, for example, from a bandpass sigma-delta converter such as that taught in copending U.S. Patent Application Serial No. 07/936,361 on an invention entitled "A Direct Conversion Receiver for Multiple Protocols", Attorney Docket No. WIRE-001US, and more specifically in U.S. Patent Application Serial No. 07/935,018 on an invention entitled "A Bandpass Sigma Delta Converter Suitable for Multiple Protocols", Attorney Docket No. WIRE-002US.

Input signal Y is applied to quadrature multipliers 3021 and 302Q, which receive quadrature local oscillator signals COS(s) and -SIN(s) , respectively, where s has an average frequency which is centered at the carrier frequency of the transmitter, approximately ω_c. The exact frequency of s is determined by the timing recovery digital phase locked loop (not shown) as described above. The output signals from mixers 3021 and 302Q are baseband signals J and K which represent the in-phase (I) and quadrature (Q) components, respectively, of the information signal with an additive noise component .

These J and K signals, each having bandwidth BW, are filtered by decimating low pass filters 3031 and 303Q, respectively. The output signals from decimating filters 3031 and 303Q are further decimated by a factor of two by 2:1 decimators 3041 and 304Q, which in turn provide the desired in-phase and quadrature output signals I and Q, respectively. It should be noted that Figure 2 is drawn such that decimators 3041 and 304Q are independent of decimating filters 3031 and 303Q, while in practice the 2:1 decimators can, if desired, be incorporated within the decimating filters.

Multipliers 3021 and 302Q may be fabricated in any convenient fashion for implementing multiplications, as is well known in the art. Since signal Y is a low resolution high rate digital sampled data signal, the multiplication can be performed using any convenient digital multiplication circuit, as is well known in the prior art. Filters 3031 and 303Q are preferably implemented as digital filters which are well known in the prior art. The characteristics of these filters can be digitally controlled and altered to have characteristics which are most suitable for the selected type of modulation being received.

Decimators 3041 and 304Q may be formed by selectively choosing every other output values of filters 3031 and 303Q, thereby providing a 2:1 decimation of the I and Q signals.

A more detailed block diagram of one embodiment of this invention is shown in Figure 3, having two decimation paths 370-1 and 370-Q which are controlled by two independent state machines 302-1 and 302-Q for providing and in-phase output signal I and a quadrature output signal Q, respectively. In the embodiment shown in Figure 3 for each of the two decimation paths 370-1 and 370-Q, a plurality of n separate branches 371-1 through 371-n; 372-1 through 371-n are shown. In one embodiment, n=3, and thus each decimation path 370-1 and 370-Q implements a third order filter function for use with a second order noise shaping circuit, as described in the above mentioned copending patent application serial number 07/935,018 (attorney docket number WIRE-002US) . It will be appreciated by those of ordinary skill in the art in light of the teachings of this invention that filter functions of any desired order can be employed by utilizing the appropriate number of branches n.

Each branch 371-1 through 371-n of in-phase path 370-1 calculates Σ Y * C_{N K} * Cos(s) for the length of the decimated time K, e.g. 64 samples, of the Y input signal, where C_N/K is the appropriate coefficient Cl through Cn, which are filter coefficients which implement the H(z) functions. Similarly, each branch 372-1 through 372-n of quadrature path 370-Q calculates Σ Y * C_{N K} * -Sin(s) for the length of the decimated time. Multiplexors 351-1 through 351-n of I path 370-1 and multiplexors 352-1 through 352-n of Q path 370-Q may be implemented, for example, as described by Meleis et al . in their figure 5. Coefficients Cl through Cn are generated in PLA 311, which is configured as a state machine programmed to generate the required filter coefficients in a specific order, e.g. as shown in Meleis figure 1. The PNTR1 input to PLA 311 is the state of the process as determined by PLA 311. The CLOCK signal is the nominal receiver clock, and phase adjust signal PA[0:1] is provided by a DPLL (not shown) which is used to determine the receiver/transmitter clock synchronization in a well known manner. The Y input signal is the composite input signal which is to be filtered. Multiplier control signal CM-c[l:n] is generated by PLA 311 and is used by multiplexors 351-1 through 351-n to select the appropriate coefficient Y1*C_{N K} for each branch 371-1 through 371-n of the in-phase path 370-1 for the duration of the impulse response of each branch (i.e. in this example 64 samples) , and thus branches 371-1 through 371-n each provide an output signal each decimation period, e.g. 64 samples, with the output signals from each branch being sequentially available. The outputs of multiplexers 351-1 through 351-n is the term (Y * C_{N κ}) for each new sample input. Figure 5 depicts the timing relationships between branches in an exemplary embodiment which includes three branches (i.e. n=3) .

Similarly, multiplier control signal CM-s[l:n] is generated by PLA 311 and is used by multiplexors 352-1 through 352-n to select the appropriate coefficient Y1*C_{N K} for each branch 372-1 through 372-n for quadrature branch 370-Q for the duration of the impulse response of each branch (i.e. in this example 64 samples) , and thus branches 372-1 through 372-n each provide an output signal each decimation period (e.g. 64 samples) , with the output signals from each branch being sequentially available. The outputs of multiplexers 352-1 through 352-n is the term (Y * C_{N K}) for each new sample input . For each decimation path 370-1 and 370-Q, one of the branches 371-1 through 371-n and 372-1 through 372-n contains the correct decimated output at any time, while the other branches contain values which are as yet incompletely calculated, which will be completely calculated in order to provide subsequent outputs.

PLA 312-1, multiplexors 351-1 through 351-n, and multiply- accumulate logic 371-1 through 371-n implement a modified Booth's algorithm multiply-accumulate function, which implements the Σ (Y * C_N/K) * Cos(s) calculation. Similarly, PLA 312-Q, multiplexors 352-1 through 352-n, and multiply-accumulate logic 372-1 through 372-n implement a modified Booth's algorithm multiply-accumulate function, which implements the Σ (Y * C_N/K) * -Sin(s) calculation. Booth's algorithm recoding is described in "Computer Arithmetic: principles, architecture, and design" by Kai Hwang, John Wiley and Sons, 1970, pp. 198-199.

One embodiment of a modified Booth's algorithm recoding circuit suitable for use as multiply-accumulate logic circuits 371-1 through 371-n and 372-1 through 372-n is depicted in Figure 4. Multiplexors 403-1 through 403-m selectively allow either ±1, ±2, or 0 times its input through to the output depending on the state the recoding signal Re_M, where M is position dependent in the multiplier array. Full adders 405-1 through 405-m add the term Re_M (Y * ^C _N, _K^ ^to t e accumulated sum, with the final output being available from adder 405-m for use by adder 375-1 (for the in-phase path 370-1) and adder 375-Q (for the quadrature path 370-Q) , as shown in Figure 3.

Referring again to Figure 3, PLA 312-1 provides output signals which determine the recoding in each multiplier array 371-1 through 371-n of in-phase path 370-1. PNTR2 is a state vector whose state is dependent on the output state of PLA 312-1. Phase adjust signal PA[0:1] from the DPLL determines either a timing advance, or retard, or null condition of the timing recovery circuit, and adjusts the value of s (as internally derived by PLA 312-1) , which in turn adjusts the COS(s) and -SIN(s) output signals from PLA 312-1. The clock input signal is the recovered receive clock. PLA 312-1 contains a Cosine/Sine function which allows multiplier arrays 371-1 through 371-n and 372-1 through 372-n to efficiently perform the product of (Y* C_{N K}) and Cos(s) for in-phase path 370-1 and (Y*C_{N K}) and -Sin(s) for quadrature path 370-Q.

As shown in Figure 3, PLA 312-1 provides recoding signals Re-l-C through Re-m-C for use in in-phase path 370-1 and PLA 312-Q provides recoding signals Re-l-S through Re-m-S for use in quadrature path 370-Q, where m is determinative of the number of stages within each multiply-accumulate array 371-1 through 371-n and 372-1 through 372-n, and thus precision of the SIN and COS functions. It will be appreciated by those of ordinary skill in the art in light of the teachings of this invention that any desired level of accuracy can be employed, as desired, by providing the appropriate number m of stages within each multiply- accumulate array.

The description given above is of a fully parallel implementation. It should be noted that time division multiplexing of the branches and even the multiplexor/adder blocks within the branches is possible in order reduce the amount of hardware required to implement the decimator.

All publications and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A bandpass decimation filter comprising: an input port for receiving a composite input signal having a non-baseband center frequency; an in-phase channel multiplier having a first input port coupled to said input port of said bandpass decimation filter, a second input port for receiving an in-phase signal at said center frequency, and an output port for providing an in-phase baseband signal; a quadrature channel multiplier having a first input port coupled to said input port of said bandpass decimation filter, a second input port for receiving a quadrature phase signal at said center frequency, and an output port for providing a quadrature phase baseband signal; a first decimating low pass filter having an input port coupled to said output port of said in-phase channel multiplier, and having an output port for providing a decimated baseband in-phase information signal; a second decimating low pass filter having an input port coupled to said output port of said quadrature channel multiplier, and having an output port for providing a decimated baseband quadrature phase information signal .

2. A bandpass decimation filter as in claim 1 wherein one or both of said first and second decimating lowpass filters comprise a decimating low pass filter coupled in series with a decimator.

3. A bandpass decimation filter as in claim 1 wherein said multipliers comprise modified Booth's algorithm multiply- accumulate logic.

4. A bandpass decimation filter as in claim 3 wherein: said in-phase channel multiplier comprises: a first state machine for providing a series of cosine output coefficients related to the cosine function; and one or more multiply paths for generating a desired output signal as a function of said cosine output coefficients and samples of said input signal; and said quadrature channel multiplier comprises: a second state machine for providing a series of sine output coefficients related to the sine function; and one or more multiply paths for generating a desired output signal as a function of said sine output coefficients and samples of said input signal .

5. A bandpass decimation filter as in claim 4 which further comprises: a third state machine which receives said clock signal and provides a set of recoding signals; and wherein each of said multiply paths comprise: a multiplexor to select the desired one of said output coefficients; a multiply-accumulate means for receiving said recoding signals from said third state machine and said selected one of said output coefficients and providing a product output; and an adder for adding said product outputs of said one or more paths.

6. A bandpass decimation filter as in claim 1 wherein said filters comprise digital filters having digital signal control ports for establishing the filter coefficients of said filters.

7. A bandpass decimation filter as in claim 2 wherein said decimators comprise 2:1 decimators.

8. A bandpass decimation filter as in claim 7 wherein said decimators perform their 2:1 decimation by selecting every other input signal as their output signal .

9. A bandpass decimation filter as in claim 1 wherein said center frequency is the frequency of a clock signal recovered from a transmitted signal.