WO1993007565A1 - Procede et appareil concernant la protection d'ecriture en memoire - Google Patents
Procede et appareil concernant la protection d'ecriture en memoire Download PDFInfo
- Publication number
- WO1993007565A1 WO1993007565A1 PCT/US1992/006455 US9206455W WO9307565A1 WO 1993007565 A1 WO1993007565 A1 WO 1993007565A1 US 9206455 W US9206455 W US 9206455W WO 9307565 A1 WO9307565 A1 WO 9307565A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- signal
- memory device
- predetermined time
- generating
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
Definitions
- This invention generally relates to the infrastructure of systems, and more specifically, to accessing a memory device contained within the microprocessing system.
- a microprocessing system typically contains a memory, a data bus, a microprocessor and peripheral devices.
- the memory contains a data bus input, an address bus input, a chip select input and a write enable input.
- a controlling device is used to create the address on the address bus.
- the chip select and the write enable lines are directly coupled between the controlling device and the memory device.
- the write enable signal may be activated for too long or falsely triggered. This may allow extraneous data to be written into the memory device; corrupting the data contained in the memory, which may seriously effect the operation of the microprocessor system.
- the controlling device may execute the wrong code during a write cycle, causing unpredictable results within the memory device.
- the controlling device triggers a logic device and the logic device creates the write enable signal for the memory device for a predetermined amount of time.
- This predetermined amount of time is typically fixed for the amount of time required to write the largest block of data to the memory device,- such that it does not limit the amount of data that is written to the memory location of the memory device.
- This system leaves a window of opportunity for corrupt data to be written into the data device when blocks of data, smaller than the largest block of data, are written to the memory device or a write enable signal is falsely triggered.
- the controlling device may execute the wrong code during a write cycle and cause unpredictable results within the memory device.
- the third system has a protection device built into the memory.
- the memory requires the controller to write a byte of data to three specific addresses prior to writing the desired data to the memory device. This implementation is discussed in the data sheets X28C64, from the XICOR Data Book, Second Edition, 1990. After the three byte sequence is written to the proper addresses, the page write window is open, allowing the controller to write from 1 to 64 bytes of data to the memory device.
- This protection device protects the memory from false triggering, but allows corruption of the memory device during the invariable page write window. Again, the controlling device may execute the wrong code during a write cycle and cause unpredictable results within the memory device.
- an adaptive data protection device which varies the duration of the write enable signal depending upon the size of the data block to be written to the memory device or the activity monitored within the controlling device, and eliminates false triggering of the write enable signal.
- the present invention encompasses a write protection apparatus for protecting a memory device from receiving corrupted data while writing a block of data from a data supplying device to the memory device.
- the memory device has a write enable input and a data input.
- the write protection apparatus couples the data supplying device to the data input of the memory device.
- the memory. protection device generates a first signal which triggers generation of a second signal.
- the second signal is active for a first predetermined time and is coupled to the input of the memory device, thereby allowing the data device to write data to the memory device during this first predetermined time.
- a third signal may be generated disabling said second signal.
- FIG. 1 is a block diagram of radiotelephone communication system which may employ the present invention.
- FIG. 2 is a circuit diagram of the present invention.
- FIG. 3 is a timing diagram of the present invention.
- FIG. 4 is a process flow chart of the method of the present invention.
- the present invention encompasses a microprocessor system incorporated into a digital radiotelephone, such as the Japan Digital Cellular Telephone.
- a digital radiotelephone such as the Japan Digital Cellular Telephone.
- an electronically erasable PROM EEPROM
- EEPROM electronically erasable PROM
- Various sizes of data blocks are written to the EEPROM from different devices.
- the EEPROM contained corrupted data which disabled or impaired the operation of the radiotelephone.
- the corrupt data written to the EEPROM is minimized.
- FIG. 1 is a block diagram of a radiotelephone communications system.
- a fixed- site transceiver 103 which sends and receives radio frequency (RF) signals to and from mobile and portable radiotelephones located in the geographic area serviced by the fixed site transceiver 103.
- Radiotelephone 101 is one such radiotelephone served by the fixed site transceiver 103.
- radiotelephone antennas 105, 107 Upon reception of radio frequency signals, radiotelephone antennas 105, 107 convert the radio frequency signals into electrical radio frequency signals where then they are transmitted to the receivers 111, 113 respectively.
- the receivers 111, 113 convert the electrical radio frequency signals into usable data for use by other parts of the radiotelephone 101.
- the microprocessor 121 Upon transmission of radio frequency signals, the microprocessor 121 inputs the data into the transmitter 109.
- the transmitter takes the data and converts it into the electrical radio frequency signals and transmits it through antenna 105 which converts its radio frequency signals and transmits those back to the fixed-site transceiver 103.
- EEPROM 127 In order for the radiotelephone 101 to operate properly, many parameters need to be stored in a permanent memory 127.
- This permanent memory is EEPROM 127.
- the EEPROM 127 is accessed via the microprocessor 121.
- the EEPROM 127 is programmed with essential operating parameters including: received signal strength information (RSSI), identification information and power level information.
- RSSI received signal strength information
- identification information identification information
- power level information power level information
- the RSSI information is necessary to calibrate the current received signal strengths.
- the calibrated received signal strengths are used to select the appropriate fixed site transceiver 103.
- the current received signal strength recovered from the receivers 111,113 is used to reference the RSSI value stored in the EEPROM 127. If the RSSI values are corrupted, then the wrong fixed site transceiver may be selected, resulting in reduced performance quality of the radiotelephone 101.
- the identification information includes a unique serial number and phone number. This information is stored in the EEPROM 127 during the original programming procedure. This information must be protected to insure the communication system's integrity. If the serial number is changed or corrupted, then the phone may be identified as someone else's or phone calls may be made and the charges applied to another's phone bill.
- the power level table is loaded into the EEPROM 127 in the factory.
- the output power levels are measured for a given input, the output power fluctuate from radio to radio depending upon component and hybrid variations.
- the transmit output power is tuned such that it meets the FCC specification or equivalent Japanese specifications at five predetermined levels.
- the information necessary to excite the power amplifier to the desired output level is stored in the EEPROM 127 and is retrieved whenever the power amplifier needs to be tuned to a predetermined power output. If this information is corrupted the power amplifier contained in the transmitter 109 will not operate within the specifications and may cause serious performance problems for the radiotelephone 101. After the information is loaded into the EEPROM 127, the radiotelephone 101 is ready to operate.
- radiotelephone 101 While the radiotelephone 101 is in use, some user feature data and various parameters are stored in the EEPROM 127 to assist in maintenance procedures when the phone is returned to a dealer for service. First, a timer is used to store the amount of elapsed time the radio is in use from the beginning of time. In order for the radiotelephone 101 to maintain this counter the radiotelephone 101 stores the counter in the
- the radiotelephone 101 When power is turned off or lost, the timer does not reset. Second, the radiotelephone 101 contains an error monitor which utilizes a set of error codes to describe problems within the radiotelephone 101 during operation. If such an error occurs while operating the radiotelephone 101, the error code and the time of occurrence is stored in the EEPROM 127 to assist in maintenance of the radiotelephone 101 at a later point in time. Additionally, the EEPROM 127 is used to store phone numbers and preferences such as ringer volume. The preceding operations are controlled by the microprocessor 121 while operating the radiotelephone 101.
- FIG. 2 is a block diagram employing the invention.
- the write cycle of data from the microprocessor 121 begins by sending a known bit pattern to a predetermined address.
- the predetermined address corresponds to the data verifier 207.
- the data verifier 207 receives the known byte of data from the microprocessor 121 and checks it against its known byte of data. Upon verification, the microprocessor 121 then changes the address to the EEPROM 127 and begins to load the desired data onto the data bus 217. Simultaneously, data verifier 207 generates a write_enable_trigger signal 211 which is input into the one-shot 203. The one-shot 203 generates a write.ok signal 213 for a predetermined time. The predetermined time is equal to the time required to write the largest data block from the microprocessor 121 to the EEPROM 127. In the preferred embodiment, the one-shot time is set to 50 uS.
- the write.ok signal 213 and the read write signal 219 are input into the AND gate 205. This ensures that in case of a false trigger from the one-shot the EEPROM's write_enable_signal 215 is not falsely enabled, protecting the EEPROM 127 from corrupted data.
- the AND gate 205 and the data verifier 207 in the preferred embodiment are implemented in a programmable logic array (PLA) model number PAL16V8, available from Advanced Micro Devices. Upon successful ANDing of the three signals 211, 213, and 219 the AND gate 205 outputs a write_enable_signal 215 to the write enable input of the EEPROM 127.
- the one-shot reset signal 209 may be used to shorten the duration of the one-shot write enable signal, thus creating a variable duration write enable signal. There are several reasons this variable write enable signal duration is desirable. First, if the data block which is to be written to the EEPROM 127 is of shorter duration than the largest block of data, then, the one shot reset signal 209 may be triggered by microprocessor 121, subsequently, disabling the write_ok signal 213 to the EEPROM 127 at the end of the shorter data block has been written. The duration of the write enable signal is equal to the length of the data block to be written to the
- the reset signal 209 may be used to discontinue a write cycle to the EEPROM 127 upon determining a problem within the radio.
- the reset signal 209 is used to discontinue a write cycle when the radiotelephone detects a read request signal or a chip select signal to a device other than the EEPROM 127. Problems are particular to the system within which the invention is employed and equally sufficient criteria for disabling the write cycle may be employed by one of average skill in the art.
- a one-shot 203 is particular to this embodiment.
- Other embodiments may employ equally sufficient timing devices, including digital timers, shift registers and resistor/capacitor (RC) circuits, in place of the one-shot.
- RC resistor/capacitor
- any memory device may be substituted in for the EEPROM 127 by one of average skill in the art.
- FIG. 3 reveals the timing of all the essential signals included in the block diagram of FIG. 2.
- the microprocessor 121 sets the data bus 305 to a known bit pattern, and the address bus 307 to the data verifier 207. After the data verifier 207 receives the known bit pattern, the microprocessor 121 sets the address bus 307 to a memory location within the EEPROM 127 and begins transferring desired data onto the data bus 307.
- the data verifier 207 creates the write_enable_trigger signal (211) 313. This signal is input into the one shot 203.
- the one-shot 203 subsequently creates a write_ok_signal 311(213) which endures for 50 microseconds (uS) and is input into the logic AND device 205.
- the logic AND device 205 uses inputs of the microprocessor's
- RD/WR signal 309 (219), the write_enable_trigger signal (211) 313, and the write.ok.signal 311 to create the EEPROM's write_enable__signal 315.
- the duration of the write_enable_signal 315 may be shortened by the microprocessor 121 enabling the reset signal 317 (209).
- the reset signal 317 (209) will reset the one-shot 203, subsequently inactivating the write_enable_signal 315 (215).
- FIG. 4 is a process flow chart of the method employed by this embodiment to reduce the opportunity of writing corrupt data to the EEPROM 127.
- the flow chart starts at 401.
- the microprocessor 121 generates a known bit pattern onto the data bus 217 and it sets the address on the bus 217 to the data verifier 207.
- the microprocessor 121 sets the address bus 217 to an address located within the EEPROM 127 and begins transferring desired data onto the data bus 217.
- the data verifier 207 upon verifying the known received bit pattern, generates a write.enable.trigger signal 207, which is coupled to both the input of a one-shot 203 and to the AND gate 205.
- the one-shot 203 generates, responsive to the write_enable_trigger signal 313, the write_ok_signal 311 for the time required to transfer the largest block of desired data to the EEPROM 127.
- the time is 50 uS.
- the reset signal 317(209) is generated by microprocessor 121 and input into the one-shot reset input, thereby disabling the write_enable_signal 315 to the EEPROM 127.
- the reset signal 317(209) functions as a variable window for the write_enable_signal 315 which is adjusted to fit the length of data block written to the EEPROM
- the reset signal 317(209) may be generated in response to problem in the radiotelephone 101, thereby cancelling the remainder of the write cyde to avoid any further damage to the EEPROM 127.
- the reset signal 317(209) is triggered in response to an attempted read or an additional chip select executed by the microprocessor 121. These signals indicate that the microprocessor 121 may be executing the wrong code.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
On décrit un appareil de protection d'écriture qui relie un dispositif (121) fournissant des données à l'entrée de données d'un dispositif à mémoire (127). Celui-ci engendre un premier signal (211) qui fait apparaître un deuxième signal (215), actif pendant une première période prédéterminée, envoyé à l'entrée du dispositif à mémoire (127). A tout moment pendant la première période prédéterminée, on peut engendrer un troisième signal (209) qui désactive le deuxième signal. Plusieurs évènements peuvent déclencher ce troisième signal (209), y compris: l'arrivée d'un signal de lecture ou d'un signal de sélection de circuit ou l'indication qu'on est arrivé au terme des données à écrire dans le dispositif à mémoire (127).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US76989691A | 1991-10-01 | 1991-10-01 | |
US769,896 | 1991-10-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1993007565A1 true WO1993007565A1 (fr) | 1993-04-15 |
Family
ID=25086828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1992/006455 WO1993007565A1 (fr) | 1991-10-01 | 1992-08-03 | Procede et appareil concernant la protection d'ecriture en memoire |
Country Status (5)
Country | Link |
---|---|
CA (1) | CA2097308A1 (fr) |
FR (1) | FR2681965A1 (fr) |
IT (1) | IT1258856B (fr) |
MX (1) | MX9205634A (fr) |
WO (1) | WO1993007565A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2320778A (en) * | 1996-12-25 | 1998-07-01 | Fujitsu Ltd | Semiconductor memory device |
GB2356952A (en) * | 1996-12-25 | 2001-06-06 | Fujitsu Ltd | Semiconductor memory device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6026293A (en) * | 1996-09-05 | 2000-02-15 | Ericsson Inc. | System for preventing electronic memory tampering |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4245344A (en) * | 1979-04-02 | 1981-01-13 | Rockwell International Corporation | Processing system with dual buses |
US4707809A (en) * | 1984-07-12 | 1987-11-17 | Nec Corporation | Semiconductor memory device with shortened time period of word line selection |
US4816654A (en) * | 1986-05-16 | 1989-03-28 | American Telephone And Telegraph Company | Improved security system for a portable data carrier |
US4860341A (en) * | 1987-06-02 | 1989-08-22 | Motorola, Inc. | Radiotelephone credit card call approval synchronization |
US4891791A (en) * | 1987-04-30 | 1990-01-02 | Kabushiki Kaisha Toshiba | Data writing system for EEPROM |
US4907257A (en) * | 1988-07-18 | 1990-03-06 | Tamura Electric Works, Ltd. | Public telephone set |
US4970692A (en) * | 1987-09-01 | 1990-11-13 | Waferscale Integration, Inc. | Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin |
US5001670A (en) * | 1987-02-06 | 1991-03-19 | Tektronix, Inc. | Nonvolatile memory protection |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4493031A (en) * | 1982-08-25 | 1985-01-08 | At&T Bell Laboratories | Memory write protection using timers |
US4742469A (en) * | 1985-10-31 | 1988-05-03 | F.M.E. Corporation | Electronic meter circuitry |
US4843385A (en) * | 1986-07-02 | 1989-06-27 | Motorola, Inc. | Electronic lock system for a two-way radio |
FR2608803B1 (fr) * | 1986-12-19 | 1991-10-25 | Eurotechnique Sa | Dispositif de protection d'une memoire morte effacable et reprogrammable |
FI86922C (fi) * | 1990-01-05 | 1992-10-26 | Raha Automaattiyhdistys | Foerfarande och anordning foer kontrollering av inskrivning i ett minne |
-
1992
- 1992-08-03 CA CA002097308A patent/CA2097308A1/fr not_active Abandoned
- 1992-08-03 WO PCT/US1992/006455 patent/WO1993007565A1/fr active Application Filing
- 1992-09-28 IT ITRM920707A patent/IT1258856B/it active IP Right Grant
- 1992-10-01 FR FR9211978A patent/FR2681965A1/fr active Pending
- 1992-10-01 MX MX9205634A patent/MX9205634A/es unknown
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4245344A (en) * | 1979-04-02 | 1981-01-13 | Rockwell International Corporation | Processing system with dual buses |
US4707809A (en) * | 1984-07-12 | 1987-11-17 | Nec Corporation | Semiconductor memory device with shortened time period of word line selection |
US4816654A (en) * | 1986-05-16 | 1989-03-28 | American Telephone And Telegraph Company | Improved security system for a portable data carrier |
US5001670A (en) * | 1987-02-06 | 1991-03-19 | Tektronix, Inc. | Nonvolatile memory protection |
US4891791A (en) * | 1987-04-30 | 1990-01-02 | Kabushiki Kaisha Toshiba | Data writing system for EEPROM |
US4860341A (en) * | 1987-06-02 | 1989-08-22 | Motorola, Inc. | Radiotelephone credit card call approval synchronization |
US4970692A (en) * | 1987-09-01 | 1990-11-13 | Waferscale Integration, Inc. | Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin |
US4907257A (en) * | 1988-07-18 | 1990-03-06 | Tamura Electric Works, Ltd. | Public telephone set |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2320778A (en) * | 1996-12-25 | 1998-07-01 | Fujitsu Ltd | Semiconductor memory device |
US6154405A (en) * | 1996-12-25 | 2000-11-28 | Fujitsu Limited | Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data |
GB2356952A (en) * | 1996-12-25 | 2001-06-06 | Fujitsu Ltd | Semiconductor memory device |
GB2320778B (en) * | 1996-12-25 | 2001-06-27 | Fujitsu Ltd | Semiconductor memory device |
GB2356952B (en) * | 1996-12-25 | 2001-07-25 | Fujitsu Ltd | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
ITRM920707A1 (it) | 1994-03-28 |
CA2097308A1 (fr) | 1993-04-02 |
ITRM920707A0 (it) | 1992-09-28 |
FR2681965A1 (fr) | 1993-04-02 |
IT1258856B (it) | 1996-03-01 |
MX9205634A (es) | 1993-04-01 |
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