WO1992017876A1

WO1992017876A1 - Color palette circuit

Info

Publication number: WO1992017876A1
Application number: PCT/EP1992/000593
Authority: WO
Inventors: André Henri GROUWSTRA
Original assignee: Music Semiconductors N.V.
Priority date: 1991-03-26
Filing date: 1992-03-17
Publication date: 1992-10-15
Also published as: NL9100540A; TW199219B

Abstract

The present invention provides a circuit for driving three digital/analog converters for three electron guns to provide a picture for a screen (or monitor), said picture comprising color picture-elements (pixels), said circuit comprising: a memory part provided with a look-up table (LUT) in which digital numbers for the digital/analog converters are included at a number of address locations; a bus for supplying a number suitable as address to said memory part; a circuit part in which two or more numbers supplied through said bus are combined into a number having a number of bits that is higher than the bits-capacity of the bus; a multiplexer or switching means connected to the outputs of the memory part and to the outputs of said circuit part; and control means for controlling said multiplexer such that either the content of an address location of said LUT is passed to said digital/analog converters or said number having the higher number of bits is passed.

Description

COLOR PALETTE CIRCUIT

With currently known microcomputers (personal compu¬ ters, work stations and the like) , in addition to the dis¬ playing of characters on a screen or monitor, graphic display options are becoming of increasingly greater impor- tance. Known under the names of VGA (Video Graphics Adap¬ ter) , EGA (Enhanced Graphics Adapter) , XGA (Extended Graphics Adapter) and the like are systems with which the color of a picture element (pixel) of the picture is selected. In these known systems a selection is for instance made using 8 bits from a "pallet" of 256 colors in a look-up table, wherein the pixels are scanned sequentially from left to right and from top to bottom on the screen. Situated at each location of this look-up table are 18 bits which are carried in groups of 6 bits to the digital/analog converters (DACs) for control of the colors red, green and blue respectively.

So-called low-end PC's are usually provided with a look-up table (LUT) for displaying 256 different colors on the screen. High-end PC's or work stations can provide for more different colors by using a bit map memory, e.g. 18 bits for each pixel. The costs of the Graphics Adapter I.e. are, however, substantially determined by the number of memory cells included therein. An Adapter I.C. for a workstation can be five to ten times as expensive as a low- end PC circuit.

US-A-4,808,989 discloses a display control apparatus using both a LUT and a bit map memory.

US-A-2,218,881 descibes graphics control planes requiring plural mapped memories. The present invention provides a circuit for driving three digital/analog converters for three electron guns to provide a picture for a screen (or monitor) , said picture comprising color picture-elements (pixels) , said circuit comprising:

- a memory part provided with a look-up table (LUT) in which digital numbers for the digital/analog converters are included at a number of address locations;

- a bus for supplying a number suitable as address to said memory part;

- a circuit part in which two or more numbers supplied through said bus are combined into a number having a number of bits that is higher than the bits-capacity of the bus;

- a multiplexer or switching means connected to the outputs of the memory part and to the outputs of said circuit part; and - control means for controlling said multiplexer such that either the content of an address location of said LUT is passed to said digital/analog converters or said number having the higher number of bits is passed.

With the circuit according to the present invention it becomes possible to drive the digital/analog converters directly from a video memory, wherein the look-up table is bypassed. Using the information from the video memory the multiplexer can then be controlled during a scanning of a picture line on the screen, whereby either the colors are indirectly specified through a look-up table or the colors are specified directly from the video memory. Many more different colors can be displayed herewith for showing photographs for instance than the maximum 256 from the look¬ up table. If two (or three or more) 8 bits address words are combined to determine the color, this has the result that two (or three or more) adjacently located pixels will obtain the same color.

The control means for controlling the multiplexer preferably make use of the inverted "blank" signal for the monitor, with which the light spot on the screen is suppressed as the electron beam flies back. Control thus becomes simple and the circuit is returned to the "normal" situation at each new picture line. Further advantages, features and details of the pre¬ sent invention will become apparent in the light of the following description of a preferred embodiment thereof with reference to the annexed drawing, wherein: fig. 1 shows a block diagram of a microcomputer provided with a graphic control making use of a preferred embodiment of a circuit according to the present invention; and fig. 2 shows a diagram of the circuit of fig. 1; and fig. 3 shows a diagram of a second preferred embodiment of the circuit of fig. 1.

A microcomputer comprises in known manner a central processing unit 1 (fig. 1) which is coupled via a data bus 2 and an address bus 3 to a graphic control unit 4, in the present embodiment a VGA control unit. This control unit 4 is connected through an address bus 5 and a pixel data bus 6 to a video memory 7 in which, for the present embodiment, 8 bits data are stored per pixel. The pixel data are carried sequentially by the control unit 4 from the video memory 7 to a circuit 8, called for instance color palette chip, and therefrom to the electron guns for the screen, as indicated with R, G and B (Red, Green and Blue) .

It can be seen in more detail that the circuit 8 (fig. 2) comprises a bus 9 along which the 8 bits words are carried in the circuit. The 8 bits words are carried either to a memory part 10 wherein a look-up table is included for looking up the color associated with each pixel, or to a circuit part 11 wherein two 8 bits words are combined and supplied directly via a multiplexer or switching means 12 to the three digital/analog converters 13, 14, 15 for the electron guns for the screen for the colors red, green and blue.

Stored at each address location of the look-up table are 18 bits which specify 6 bits for each of the digital/analog converters.

In the circuit part 11, 15 bits are used of two se¬ quentially supplied 8 bits words - after the first 8 bits word is delayed - for the direct color specification, three zeros are added thereto and the 16th bit of the two words is fed back to the control means for controlling the multiplexer 12. Included between data bus 9 and the memory part 10 and the circuit part 11 is a multiplexer 16 which in a simplified design (not shown) may be omitted.

The control line 17 of the multiplexer 12 is connected to the output of a flip-flop 18, the set (s) input of which is coupled to a circuit part 19 for recognition of an access code, while the reset (r) input is coupled to an OR-gate 20 of which a first input is connected via an inver¬ ter 21 to the blank signal of the part likewise coupled to a reset input of a divider by two 22 (or by three in case of combining three bytes) .

When a particular 8 bits word (access code) is recog- nized via the bus 9 in circuit part 19, the flip-flop 18 is triggered and the multiplexer 12 is switched, after which color specification for the digital/analog converters 13, 14, 15 takes place via the circuit part 11. A first 8 bits word is delayed in a circuit part 11 while a second 8 bits word is added thereto and the zeros are added. Using one bit (the 16th) , which is therefore controllable from the video memory, the multiplexer 12 can once again be switched via the OR-gate 20 and the flip-flop 18. During scanning of a picture line it is therefore possible to return to the "normal" situation ("on the fly") .

When starting a program, a key sequence of words is written from that program into a register 23, wherein, using a code, the circuit indicates to the program by means of a 'Direct Color Code' in a manner not shown that it is possible with this circuit to specify the color in two ways. The circuit part 24 is connected to the E(nable)-input of the flip-flop 18, thus enabling switching of the multiplexer 12. Circuit part 25 comprises eight AND-gates for using the register 23 also as a mask register for masking one or more of the bits for the LUT. In the shown embodiment the register for the key sequence is also used as mask register. In another, not shown embodiment a different register would be used for the key sequence. As will be apparent from the circuit diagram of fig. 2 the blank signal causes a switching of the multiplexer 12, i.e. at the beginning of each picture line color specifica¬ tion takes place from the look-up table 10. The blank signal is connected to a reset (r)-input of a divider by two 22 for the clock signal, while the output is connected to the E(nable)-input of the access code recognizing means 19. In the present embodiment, switching of the multiplexer can take place every two pixels, this being realized by the divider by two. In the case of for instance three (or more) bits, dividers by three (or more) would be necessary.

In a second preferred embodiment according to the present invention a circuit 8 ' comprises the bus 9 which divides into three parallelbuses 9',9' ',9'''. Bus 9' leads through a circuit part 35 provided with eight AND-gates and connected to a mask register 33 to memory part 30 in which a look-up-table (LUT) is included. The 18 bits wide output bus of the circuit part 30 leads to a multiplexer 42. Buses 9'' and 9*'' lead to registers 37 and 38 respectively. The output buses of the registers 37 and 38 combine into a 16 bits wide bus 39, which leads to a circuit part 41 in which two zeros are added to the 16 bits and of which the output leads to the multiplexer 42. Bus 39 also leads to a circuit part 40 for access to and exit from the 'direct color mode' and which is connected to a flip-flop 48 that controls the multiplexer 42. The circuit part 40 is also connected to a special or additional address of memory part 30. The "blank"-signal is supplied to the reset input of the flip-flop 48.

The "blank"-signal is also connected to the reset input of a divider by two 44 for dividing the clock-pulses CL. The outputs of the divider by two 44 are connected to registers 37 and 38 resp. Eight bits words alternate between registers 37 and 38 by means of the divider by two 44. When circuit part 40 recognizes a particular 8 (or 16) bits word the color for the next two pixels is defined by the special address in the look-up-table, such that a junction appears between the screen part defined from the look-up-table and the screen part directly defined from the video-memory. Therefore' switching back and forth between the two modes for the digital/analog-convertors 13, 14 and 15 resp. is controlled through circuit part 40.

The second preferred embodiment of the present invention has the further advantage relative to the first embodiment of using 16 bits (viz. one bit more) for directly defining the color from the video memory, defining 64.000 in stead of 32.000 colors.

The circuits according to the present invention are compatible with known color palette circuits. The BIOS (Binary Input/Output System) of a personal computer can remain unchanged.

As it is now preferred with the circuit according to the present invention to automatically turn off the select option for the direct color specification when the power supply is cut, the BIOS of laptop computers should however perhaps be slightly modified. It is the case with at least some types that the power supply for the video adapter (and the screen) is occasionally switched off automatically in order to save energy supply.

In the shown embodiment the divider is reset by the inverted "blank"-signal.

A synchronization through the access (and exit) code recognition would also be possible.

An actual embodiment being designed may differ from the embodiments shown and described; timing requirements may necessitate one or more delay stages to be included into the circuit diagram.

It is further contemplated to use the divided pixel clock for controlling the DACs-Com and and other registers are readily available in certain parts of a video adapter circuit board. Even a 'key sequence cicuit' (see page 4 of the description) may be available on such board.

Claims

1. A circuit for driving three digital/analog converters for a picture for a monitor, said picture comprising picture-elements (pixels) , said circuit comprising: - a memory part provided with a look-up table (LUT) in which digital numbers for the digital/analog converters are included at a number of address locations;

- a bus for supplying a number suitable as address to said memory part; - a circuit part in which two or more numbers supplied through said bus are combined into a number having a number of bits that is higher than the bits-capacity of the bus;

- a multiplexer or switching means connected to the outputs of the memory part and to the outputs of said circuit part; and

- control means for controlling said multiplexer such that either the content of an address location of said LUT is passed to said digital/analog converters or said number having the higher number of bits is passed.

2. A circuit as claimed in claim 1, wherein said look-up table comprises 256 locations and a bus is 8 bits wide.

3. A circuit as claimed in claim 1 or 2, wherein the circuit part in which said higher number is shaped comprises delay means for providing the number to the multiplexer at the correct time.

4. A circuit as claimed in claim 1, 2 or 3, wherein the control means for controlling the multiplexer are con- nected to a line for the blank signal of the monitor.

5. A circuit as claimed in claim 4, wherein the blank line is connected to the select input of the multiplexer through a flip-flop.

6. A circuit as claimed in any of the foregoing clai¬ ms, wherein a bit of the number having the higher number of bits is fed back and is combined with the blank signal in a logic element.