WO1991013392A2 - Easily configurable fully differential fast logic circuit - Google Patents

Easily configurable fully differential fast logic circuit Download PDF

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Publication number
WO1991013392A2
WO1991013392A2 PCT/US1991/000987 US9100987W WO9113392A2 WO 1991013392 A2 WO1991013392 A2 WO 1991013392A2 US 9100987 W US9100987 W US 9100987W WO 9113392 A2 WO9113392 A2 WO 9113392A2
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signal
tied
input
output
complement
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PCT/US1991/000987
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French (fr)
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WO1991013392A3 (en
Inventor
James Hesson
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Micron Technology, Inc.
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Publication of WO1991013392A2 publication Critical patent/WO1991013392A2/en
Publication of WO1991013392A3 publication Critical patent/WO1991013392A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Definitions

  • This invention relates to fully differential fast logic circuitry such as used in digital electronic data processors and, more particularly, to high-speed circuits of a universal nature, which are easily configurable to provide a variety of digital logic functions.
  • a differential signal requires two wires, one to carry a true form of the signal, and another to carry a complement form of the signal. This contrasts with normal logic, where a single wire carries a single signal, which may be a logic one or zero.
  • Circuitry that is fully differential, that is, having all inputs and outputs differential, offer speed and design advantages, particularly in CMOS implementations. Signal noise is more easily overcome, and inversion is accomplished merely by reversing wires.
  • the invention utilizes tristatable inverters (also referred to as buffers) to construct an improved, high- speed, fully differential CMOS logic circuit.
  • This improved circuit is capable of propagation delays that are as low as that for a single transistor.
  • the improved logic circuit includes four tristatable buffers which are interconnected in such a way as to provide three differential inputs and one differential output. Different configurations of the output and inputs provide different logic functions.
  • three of these logic circuits are combined to make a fully differential 3- bit full adder, generating sum and carry outputs within two transistor propagation delays.
  • Figure 1 is a functional block diagram of a tristatable buffer, which is known in the art and is used as a repeating element of the new, easily-configurable, fully-differential fast logic circuit;
  • Figure 2 is a circuit diagram for the tristatable buffer of Figure l;
  • Figure 3 is a logic diagram of the easily- configurable, fully-differential fast logic circuit
  • Figure 4 shows the fast logic circuit configured as a fully differential NAND gate; and Figure 5 depicts a 3-bit full adder comprising a trio of the fast logic circuits.
  • a tristatable inverter (also referred to as a tristatable buffer) is depicted.
  • This particular tristatable inverter which is used as a building block for the easily-configurable, fully- differential fast logic circuit that is the focus of this invention is well known in the art.
  • the tri-statable inverter has a primary input I, an inverted output O, a first enabling input FI, and a second enabling input SI.
  • the signals fed to first and second enabling inputs FI and SI are always complementary.
  • the combinational input of a pair of complementary signals to the appropriate enabling inputs of a tristatable buffer acts to enable the buffer, it is known in the art that the enable inputs of a tristatable buffer may also be used for logic data input.
  • an easily-configurable, fully-differential fat logic circuit is constructed from four tristatable buffers which are identical to the one depicted in Figures 1 and 2,
  • Line W is the primary signal input to buffer Al
  • X is the primary signal input to buffer A2
  • Y is the primary signal input to buffer A3
  • Z is the primary signal input to buffer A4.
  • Buffer Al output 01 is tied to buffer A2 output 02, resulting in a first tied output TI.
  • Buffer A3 output 03 is tied to buffer A4 output 04, resulting in a second tied output T2.
  • outputs TI and T2 are differential.
  • An enable signal E is fed to the first enabling inputs of buffers Al and A3, (FI1 and FI3, respectively) , and to the second enabling inputs of buffers A2 and A4 (SI2 and SI4, respectively).
  • enable signal E, E* is fed to the first enabling inputs of buffers A2 and A4 (FI2 and FI4, respectively) , and to the second enabling inputs of buffers Al and A3 (SI1 and SI3, respectively) .
  • Table 1 designates the proper assignment of signals A, A*, B, and B* to inputs W, X, Y, Z, E, and E* that will result in the logical operations of A XOR B, A XNOR B, A AND B, A and B*, A NAND B, A OR B, A OR B*, A* OR B, AND A NOR B, respectively.
  • the signal pair A/A* is a differential input, as is the pair B/B*.
  • buffers Al and A3 are active, outputting A* to node 1 and A to node 3.
  • Buffers A2 and A4 are tristated, putting no output to nodes 2 and 4. 01 and 02 therefore receive A* and A, respectively.
  • buffers A2 and A4 are active, outputting B* to node 2 and B to node 4.
  • Buffers Al and A3 are tristated, putting no output to nodes 1 and 3. 01 and 02 therefore receive B* and B, respectively.
  • Table 2 This is summarized in Table 2 below. "-" indicates a tristate (high impedance) condition. - -
  • NAND configuration above may be changed to AND simply by interchanging Ol and 02.
  • a logical AND may also be performed by configuring the invention as indicated on the third line of Table 3.
  • Block 52 is also referred to herein as the first circuit or building block, block SO as the second circuit or building block, and block 51 as the third circuit or building block.
  • Blocks 50 and 51 are configured, with reference to Table 1, as XOR gates.
  • Block 50 receives data operand signals A, A*, B, and B* on its /Z, X/Y, E, and E* inputs, respectively.
  • Sum generator block 51 receives carry-in signal CIN and its complement CIN* on its E and E* inputs, respectively, the TI output of block 50 on its W/Z input, and the T2 output of block 50 on its X/Y input, generating both sum output signal SUM on its T2 output, and complement bum output signal SUM* on its TI output.
  • Carry generator block 52 differentially receives carry-in signal CIN on its W input, complement carry-in signal CIN* on its Y input, data operand signal A on its X input, data operand signal A* on its Z input, the TI output of block 50 on its E input, and the T2 output of block 50 on its E* input. In response to these inputs, carry generator block 52 generates carry-out signal COUT on its T2 output and complement carry-out signal COUT* on its TI output. Signals SUM/SUM* and COUT/COUT* are generated within only two transistor delays.
  • OR circuit for example, might be claimed below, OR variations are intended to be also circumscribed, such as the inversion of inputs or outputs (i.e. A OR B, A* OR B, A OR B*, A* OR B*, A NOR B are all variations of OR) .
  • noninverting buffers having operational speed equivalent to that of the inverting buffers may also be used to construct the primary embodiment of the invention.
  • the employed buffers must be tristatable. Therefore, although tristate means are claimed, this term is meant to apply to both inverting and noninverting buffer means, as well.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)

Abstract

Fast CMOS fully differential logic circuitry, using only tristatable buffers, and capable of as low as a single transistor propagation delay. The preferred embodiment of the invention includes four tristatable buffers (A1, A2, A3, and A4) connected together in such a way as to have multiple differential inputs and one differential output. Different configurations of the output and inputs make different logic functions available. An alternate embodiment combines three of these logic circuits to make a fully differential 3-input full adder, generating sum (SUM/SUM*) and carry outputs (COUT/COUT*) within two transistor delays.

Description

EASILY CONFIGURABLE FULLY DIFFERENTIAL FAST LOGIC CIRCUIT
Field of the Invention
This invention relates to fully differential fast logic circuitry such as used in digital electronic data processors and, more particularly, to high-speed circuits of a universal nature, which are easily configurable to provide a variety of digital logic functions.
Background of the Invention
Digital logic functions, such as AND, OR, XOR, NAND, NOR, and XNOR, are well known in the digital electronic arts, and differential logic is often used. A differential signal requires two wires, one to carry a true form of the signal, and another to carry a complement form of the signal. This contrasts with normal logic, where a single wire carries a single signal, which may be a logic one or zero.
Circuitry that is fully differential, that is, having all inputs and outputs differential, offer speed and design advantages, particularly in CMOS implementations. Signal noise is more easily overcome, and inversion is accomplished merely by reversing wires.
It is an object of the present invention to provide an easily configurable, fast, fully differential logic circuit which can easily be configured for logic functions such as AND, OR, XOR, NAND, NOR, XNOR, and carry generation.
Summary of the Invention
The invention utilizes tristatable inverters (also referred to as buffers) to construct an improved, high- speed, fully differential CMOS logic circuit. This improved circuit is capable of propagation delays that are as low as that for a single transistor.
In a preferred embodiment of the invention, the improved logic circuit includes four tristatable buffers which are interconnected in such a way as to provide three differential inputs and one differential output. Different configurations of the output and inputs provide different logic functions.
In another embodiment of the invention, three of these logic circuits are combined to make a fully differential 3- bit full adder, generating sum and carry outputs within two transistor propagation delays.
Brief Description of the Drawings
Figure 1 is a functional block diagram of a tristatable buffer, which is known in the art and is used as a repeating element of the new, easily-configurable, fully-differential fast logic circuit;
Figure 2 is a circuit diagram for the tristatable buffer of Figure l;
Figure 3 is a logic diagram of the easily- configurable, fully-differential fast logic circuit;
Figure 4 shows the fast logic circuit configured as a fully differential NAND gate; and Figure 5 depicts a 3-bit full adder comprising a trio of the fast logic circuits.
Preferred Embodiment of the Invention
Referring now to Figure 1, a tristatable inverter (also referred to as a tristatable buffer) is depicted. This particular tristatable inverter, which is used as a building block for the easily-configurable, fully- differential fast logic circuit that is the focus of this invention is well known in the art. The tri-statable inverter has a primary input I, an inverted output O, a first enabling input FI, and a second enabling input SI. The signals fed to first and second enabling inputs FI and SI are always complementary.
Referring now to Figure 2, which is the actual circuit diagram of the tristatable inverter depicted in Figure 1,
P-channel transistors QI and Q2 and N-channel transistors
Q3 and Q4 are connected as shown. It is readily shown that when the signal to first enabling input FI is high and the signal to second enabling input SI is low, the complement of a signal at primary input I will result at inverted output O. However, when the signals input to first enabling input FI and second enabling input SI are reversed, the inverter will be in a tristate condition.
Although the combinational input of a pair of complementary signals to the appropriate enabling inputs of a tristatable buffer acts to enable the buffer, it is known in the art that the enable inputs of a tristatable buffer may also be used for logic data input.
Referring now to Figure 3, a primary embodiment of the invention, an easily-configurable, fully-differential fat logic circuit is constructed from four tristatable buffers which are identical to the one depicted in Figures 1 and 2,
SUBSTITUTE SHEET τ£> A namely Al, A2, A3 and A4. Line W is the primary signal input to buffer Al, X is the primary signal input to buffer A2, Y is the primary signal input to buffer A3, and Z is the primary signal input to buffer A4. Buffer Al output 01 is tied to buffer A2 output 02, resulting in a first tied output TI. Buffer A3 output 03 is tied to buffer A4 output 04, resulting in a second tied output T2. For the preferred embodiment configuration shown, outputs TI and T2 are differential. An enable signal E is fed to the first enabling inputs of buffers Al and A3, (FI1 and FI3, respectively) , and to the second enabling inputs of buffers A2 and A4 (SI2 and SI4, respectively). The complement of enable signal E, E*, is fed to the first enabling inputs of buffers A2 and A4 (FI2 and FI4, respectively) , and to the second enabling inputs of buffers Al and A3 (SI1 and SI3, respectively) .
Table 1, which follows, designates the proper assignment of signals A, A*, B, and B* to inputs W, X, Y, Z, E, and E* that will result in the logical operations of A XOR B, A XNOR B, A AND B, A and B*, A NAND B, A OR B, A OR B*, A* OR B, AND A NOR B, respectively.
TABLE 1
FUNCTION X Y Z E E*
A XOR B A A* A* A B B*
A XNOR B A* A A A* B B*
A AND B A* B* A B B B*
A AND B* B A* B* A B B*
A* AND B A B* A* B B B*
A NAND B A B A* B* B B*
A OR B B* A* B A B B*
A OR B* A* B A B* B B*
A* OR B B* A B A* B B*
A NOR B B A B* A* B B*
Referring now to the example of Figure 4, the invention is configured as a fully differential NAND gate, in accordance with the sixth line of Table 1 above. The signal pair A/A* is a differential input, as is the pair B/B*. When B is high and B* is low, buffers Al and A3 are active, outputting A* to node 1 and A to node 3. Buffers A2 and A4 are tristated, putting no output to nodes 2 and 4. 01 and 02 therefore receive A* and A, respectively. When B is low and B* is high, buffers A2 and A4 are active, outputting B* to node 2 and B to node 4. Buffers Al and A3 are tristated, putting no output to nodes 1 and 3. 01 and 02 therefore receive B* and B, respectively. This is summarized in Table 2 below. "-" indicates a tristate (high impedance) condition. - -
TABLE 2
A/A* B/B* 1 2 3 4 01/02
0/1 0/1 - 1 - 0 1/0
0/1 1/0 1 - 0 - 1/0
1/0 0/1 - 1 - 0 1/0
1/0 1/0 0 - 1 - 0/1
It is recognized that more than one configuration may correspond to a given function. For example, the NAND configuration above may be changed to AND simply by interchanging Ol and 02. A logical AND may also be performed by configuring the invention as indicated on the third line of Table 3.
Referring to Figure 5, a secondary embodiment of the invention is depicted. A fast, fully-differential 3-input full adder has been constructed by using three of the first embodiment circuits, depicted in Figure 3, as building blocks. Block 52 is also referred to herein as the first circuit or building block, block SO as the second circuit or building block, and block 51 as the third circuit or building block. Blocks 50 and 51 are configured, with reference to Table 1, as XOR gates. Block 50 receives data operand signals A, A*, B, and B* on its /Z, X/Y, E, and E* inputs, respectively. Sum generator block 51 receives carry-in signal CIN and its complement CIN* on its E and E* inputs, respectively, the TI output of block 50 on its W/Z input, and the T2 output of block 50 on its X/Y input, generating both sum output signal SUM on its T2 output, and complement bum output signal SUM* on its TI output. Carry generator block 52 differentially receives carry-in signal CIN on its W input, complement carry-in signal CIN* on its Y input, data operand signal A on its X input, data operand signal A* on its Z input, the TI output of block 50 on its E input, and the T2 output of block 50 on its E* input. In response to these inputs, carry generator block 52 generates carry-out signal COUT on its T2 output and complement carry-out signal COUT* on its TI output. Signals SUM/SUM* and COUT/COUT* are generated within only two transistor delays.
Clearly, other functions besides those disclosed may be generated simply by reconfiguring inputs of the basic inventive circuit. Even though an OR circuit, for example, might be claimed below, OR variations are intended to be also circumscribed, such as the inversion of inputs or outputs (i.e. A OR B, A* OR B, A OR B*, A* OR B*, A NOR B are all variations of OR) . In addition, noninverting buffers having operational speed equivalent to that of the inverting buffers may also be used to construct the primary embodiment of the invention. In any case, the employed buffers must be tristatable. Therefore, although tristate means are claimed, this term is meant to apply to both inverting and noninverting buffer means, as well.

Claims

Claims :
1. An easily-configurable, fast fully-differential logic circuit, comprising:
first, second, third, and fourth tristatable buffers (Al, A2, A3, and A4, respectively), each of said buffers having as a primary input (W, X, Y, and Z, respectively) , each of said buffers also having a first enabling input (FI1, FI2, FI3, and FI4, respectively), a second enabling input (SI1, SI2, SI3, and SI4, respectively), and an output (01, 02, 03, and 04, respectively);
the first enabling inputs of said first and third buffers (FI1 and FI3, respectively), and the second enabling inputs of said second and fourth buffers (SI2 and SI4, respectively) being tied to an enabling signal E, and the first enabling inputs of said second and fourth buffers (FI2 and FI4, respectively), and the secondary enabling inputs of said first and third buffers (SI1 and SI3, respectively) being tied to an enabling signal E* (the complement of enable signal E) ;
the outputs of said first and second buffers (01 and 02, respectively) being tied together to provide a first tied output (TI) , and the outputs of said third and fourth buffers (03 and 04, respectively) being tied together to provide a second tied output (T2) ; said first tristatable buffer (Al) and said third tristatable buffer (A3) being tristated when enable signal E is in a first binary state and signal E is in a second binary state, and said second tristatable buffer (A2) and said fourth tristatable buffer being tristated when enable signal (E) is in a second state and its complement (E ) is in a first state.
2. The logic circuit of Claim 1 configured to provide an XOR function of operand signals A and B on second tied output (T2) and an XNOR function of operand signals A and B on first tied output (TI) , wherein inputs W and Z are both tied to signal A, inputs X and Y are both tied to signal A* (the complement of signal A) , enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B* (the complement of signal B) .
3. The logic circuit of Claim 1 configured to provide an XNOR function of operand signals A and B on second tied output (T2) and an XOR function of operand signals A and B on first tied output (TI) , wherein said inputs X and Y are both tied to signal A, inputs W and Z are both tied to signal A* (the complement of signal A) , enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B* (the complement of signal B) .
4. The logic circuit of Claim 1 configured to provide an AND function of operand signals A and B on second tied output (T2) and a NAND function of operand signals A and B on first tied output (TI) , wherein said input Y is tied to signal A, input Z is tied to signal B, input W is tied to signal A* (the complement of signal A) , input X is tied to signal B* (the complement of signal B) , enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
5. The logic circuit of Claim 1 configured to provide a NAND function of operand signals A and B on second tied output (T2) and an AND function of operand signals A and B on first tied output (TI) , wherein said input W is tied to signal A, input X is tied to signal B, input Y is tied to signal A* (the complement of signal A) , input Z is tied to signal B* (the complement of signal B) , enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
6. The logic circuit of Claim 1 configured to provide an AND function of operand signals A and B* (the complement of B) on second tied output (T2) and a NAND function of operand signals A and B* on first tied output (TI) , wherein said input W is tied to signal B, input X is tied to signal A* (the complement of signal A) , input Y is tied to signal B*, input Z is tied to signal A, enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
7. The logic circuit of Claim 1 configured to provide an AND function of operand signals A* (the complement of signal A) and B on second tied output (T2) and a NAND function of operand signals A* and B on first tied output
(TI) , wherein said input W is tied to signal A, input X is tied to signal B* (the complement of signal B) , input Y is tied to signal A*, input Z is tied to signal B, enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
8. The logic circuit of Claim 1 configured to provide an OR function of operand signals A and B on second tied output (T2) and a NOR function of operand signals A and B on first tied output (TI) , wherein said input W is tied to signal B* (the complement of signal B) , input X is tied to signal A* (the complement of signal A) , input Y is tied to signal B, input Z is tied to signal A, enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
9. The logic circuit of Claim 1 configured to provide a NOR function of operand signals A and B on second tied output (T2) and an OR function of operand signals A and B on first tied output (TI) , wherein said input W is tied to signal B, input X is tied to signal A, input Y is tied to signal B* (the complement of signal B) , input Z is tied to signal A* (the complement of signal A) , enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
10. The logic circuit of Claim 1 configured to provide an OR function of operand signals A and B* (the complement of signal B) on second tied output (T2) and a NOR function of operand signals A and B* on first tied output (TI) , wherein said input W is tied to signal A* (the complement of signal A) , input X is tied to signal B, input Y is tied to signal A, and input Z is tied to signal B*, enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
11. The logic circuit of Claim 1 configured to provide an OR function of operand signals A* (the complement of signal A) and B on second tied output (T2) and a NOR function of operand signals A* and B on first tied output (TI) , wherein said input W is tied to signal B* (the complement of signal B) , input X is tied to signal A, input Y is tied to signal B, and input Z is tied to signal A*, enable signal E corresponds to signal B, and complementary enable signal E* corresponds to signal B*.
12. The logic circuit of Claim 1, wherein each of said buffers is an inverter.
13. The logic circuit of Claim 1, which further comprises second and third additional circuits of the same type configured to provide OR/NOR functions, all three circuits functioning as a fast, fully-differential three-input adder circuit.
14. The logic circuit of Claim 13, wherein said second circuit (50) receives data operand signals A, A*, B, and B* on its W/Z, X/Y, E, and E* inputs, respectively; said third circuit (51) , which functions as a sum generator block, receives carry-in signal CIN and its complement CIN* on its E and E* inputs, respectively, the TI output of second circuit (50) on its W/Z input, and the T2 output of second circuit (50) on its X/Y input, generating both sum output signal SUM on its T2 output, and sum complement output signal SUM* on its TI output; and first circuit (52) , which functions as a carry generator block, receives carry-in signal CIN on its W input, carry-in complement signal CIN* on its Y input, data operand signal A on its X input, data operand signal A* on its Z input, the TI output of second circuit (50) on its E input, and the T2 output of second circuit (50) on its E* input, said first circuit generating in response a carry-out signal COUT on its T2 output and carry-out complement signal COUT* on its TI output.
PCT/US1991/000987 1990-02-12 1991-02-12 Easily configurable fully differential fast logic circuit WO1991013392A2 (en)

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US478,906 1983-03-25
US47890690A 1990-02-12 1990-02-12

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

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