WO1991010286A1

WO1991010286A1 - Phase shifter

Info

Publication number: WO1991010286A1
Application number: PCT/EP1989/001614
Authority: WO
Inventors: Joannes Mathilda Josephus Sevenhans; Erik Maurice René VANDEN ABEELE
Original assignee: Alcatel N.V.; Bell Telephone Manufacturing Company, Naamloze Vennootschap
Priority date: 1989-12-27
Filing date: 1989-12-27
Publication date: 1991-07-11
Also published as: AU642686B2; AU6812290A

Abstract

In this phase shifter from an input signal (IN) two intermediate signals (V1, V2) are derived with a mutual phase shift of about 90 degrees. These signals (V1, V2) are then converted in two other signals (V3, V4) with equal amplitudes and from the latter signals (V3, V4) sum (V5) and difference (V6) signals are then generated and converted again in two signals (OUT1, OUT2) with equal amplitudes. These signals constitute the output signals.

Description

PHASE SHIFTER The present invention relates to a phase shifter able to derive from an input signal two signals intended to be mutually phase- shifted by ninety degrees. Such a phase shifter is already known in the art, e.g. from the article "GHz-Band Monolithic Modem IC's" by Hiroyuki Kikuchi et al. published in IEEE Transactions on microwave theory and techniques, vol. MTT-35, No 12, December 1987, pp. 1278 to 1279. This phase shifter makes use of resistance/capacitance circuits, a part of the capacitance being the variable capacitance of the p-n junction of diodes. This variable capacitance, and therefore the phase-shift of the output signals of this Phase shifter may be adjusted to 90 degrees by regulating the voltage across the above diodes. This regulation is required to compensate for the inaccuracy of the other capacitances and of the resistors of the RC circuits. In a commonly used integrated circuit technology this inaccuracy is of the order of 20 percent, while in a commonly used integrated circuit technology operating at low voltages e.g. 5 Volts, the regulating range of the capacitance of diodes is limited to 10 percent, and this is insufficient compared to the above 20 percent. It is therefore a drawback of this known phase shifter that it has to be built with discrete components or in a special costly integrated circuit technology with higher accuracy of components, with adjustable components or with a higher operating voltage.

A general object of the present invention is to provide a phase shifter of the above type but which does not present this drawback, is insensitive to component tolerances and operates without regulation and at different frequencies.

According to the invention, this object is achieved due to the fact that it includes a first phase shifting circuit which derives from said input signal two first intermediate signals having a phase shift greater than 0 degrees and smaller than 180 degrees, an equalising circuit which converts said two first intermediate signals to two second intermediate signals with equal amplitudes and a second phase shifting circuit which generates a sum and a difference signal of said second intermediate signals, said sum and difference signals being mutually phase shifted by ninety degrees.

In this way, in analogy to the geometric principle that the sum and the difference of two vectors of equal length are orthogonal, the sum and difference signals are accurately shifted 90 degrees in phase.

The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein :

Fig. 1 is a schematic diagram of a phase shifter according to the invention.

Fig. 2 shows a vector diagram of the signals V3 to V6 of the phase shifter of Fig. 1,

Fig. 3 is a detailed circuit diagram of a differential embodiment of the phase shifter of Fig..l.

The phase shifter is for instance used in a quadrature modulator circuit of a mobile radio communication system. It operates in the gigahertz range. The phase shifter of Fig. 1 has an input IN, two outputs OUTl and 0UT2 and comprises four circuits Cl, C2, C3 and C4. IN is coupled to an integrator circuit A with output VI and to a differentiator circuit B with output V2, both A and B constituting a first phase shifting circuit Cl. VI and V2 are coupled to an equaliser EQ1 with an output V3 and to an equaliser EQ2 with an output V4 respectively, EQ1 and EQ2 forming together a first equalizing circuit C2. V3 and V are both coupled to a summing circuit SUM with output V5 and to a subtractor circuit SUB with output V6, both SUM and SUB constituting a second phase shifting circuit C3. Finally, V5 and V6 are coupled to an equaliser EQ3 with output OUTl and an equaliser EQ4 with output 0UT2 respectively, EQ3 and EQ together forming a second equalizing circuit C4.

All above mentioned inputs and outputs are supposed to carry like named signals.

The integrator circuit A produces an intermediate signal VI having a phase shift of approximately -45 degrees with respect to an input signal IN for a given frequency. Likewise, the differentiator circuit B generates an intermediate signal V2 with a phase shift of approximately +45 degrees with respect to the input signal IN for the given frequency. The first intermediate signals VI and V2 are consequently mutually shifted in phase over approximately 90 degrees in the phase shifting circuit Cl . They are then converted in respective equalisers EQ1 and EQ2 of the equalizing circuit C2 to two second intermediate signals V3 and V of equal amplitude. These signals V3 and V4 are processed in the circuit C3 : they are added in the adder SUM which produces a sum signal V5 and also subtracted in a subtractor SUB which provides a difference signal V6. As will be explained below, V5 and V6 remain orthogonal independent from the phase shift of the two first intermediate signals VI and V2 and of the frequency of input signal IN. V5 and V6 are then converted by respective equalisers E 3 and EQ4 of the equalizing circuit C to two signals of equal amplitude. These constitute the output signals OUTl and 0UT2. The latter have the frequency of the input signal IN and have very accurately the same amplitude and a phase shift very accurately equal to 90 degrees. Indeed, the operation of the phase shifting circuit C3 is based on the insight that the sum and difference vectors of two arbitrary vectors of equal length are orthogonal and that this principle is applicable to electrical signals whose amplitudes define the lengths of the vectors and the phase shift of which is the angle between these vectors. This principle is illustrated in Fig. 2 : from the two signals V3 and V , with equal amplitudes due to the equalisation in C2 (EQl, EQ2), and with a phase shift approximately equal to 90 degrees are derived a sum signal V5 and a difference signal V6, and these signals are orthogonal according to the above geometrical principle. The amplitudes of V5 and V6 are not necessarily equal, and that is why a second equalisation (EQ3, EQ ) has to be performed in C .

Reference is now made to Fig. 3 which shows a diffential embodiment of the phase shifter of Fig. 1 in detail. This phase shifter operates on differential signals (IN+/IN-, V1+/V1- to V6+/V6-, 0UT1+/0UT1-,

0UT2+/0UT2-) provided on like named terminals and comprises circuits Cl, C2» C3 and C4 described above and operating between V and G (ground).

Phase shifting circuit Cl has a differential input IN+ and IN-, and differential outputs V1+, V1-, and V2+,

V2-. For simplicity reasons IN+ and IN-, is represented at three different locations of Fig. 3. The integrator, circuit A is constituted by a series resistor Rl between IN- and V1-, another series resistor R2 between IN+ and V1+, and a common shunt capacitor Cl interconnecting V1+ and V1-. The differentiator circuit B is constituted by a series capacitor C2 between IN- and V2-, another series capacitor C3 between IN+ and V2+, and a common shunt resistance constituted by the series connection of two resistors R3 and Rή connected between V2- and V2+. The circuit Cl further includes bias resistors R5, connected between IN- and the tapping point of R3/R4 and R6, connected between IN+ and this same tapping point. R5 and R6 supply a suitable bias voltage for the bases of transistors T3 and T described below.

The equalizing circuit C2 comprises two amplifiers EQl and EQ2. EQl is constituted by a pair of transistors Tl and T2 whose emitters are connected to a common emitter resistor R7 the other of which is connected to ground terminal G. The bases of transistors Tl and T2 are connected to VI- and V1+ respectively, whilst their collectors constitute terminals V3+ and V3-. The second amplifier EQ2 is idential to EQl. It is constituted by a pair of transistors T3 and T4 whose emitters are connected to common emitter resistor R8 the other end of which is also connected to ground terminal G. The collectors of T3 and T4 constitute terminals V + and V4- respectively and the bases of these transistors are connected to V2- and V2+ respectively. The phase shifting circuit C3 includes four pairs of transistors T4/T5, T6/T7, T8/T9, TlO/Tll,^' each pair having commoned emitters connected to terminals V +, V4-, V3+ and V3- respectively. The summing circuit SUM and the difference circuit SUB of Fig. 1 cannot clearly be distinguished in this figure. Indeed, the summing of signals is obtained by connecting the collector of T4 to that of T9 and to V5+ and by connecting the collector of T7 to that of T10 and to V5-. The subtraction of signals is realised by connecting the collector of T6 to that of T8 and to V6+, and by connecting the collector of T5 to that of Til and to V6-. The bases of all above transistor pairs of C3 are connected to the one ends of bias resistors R9, RIO, Rll, R12 whose other ends are connected to the collectors of T4, T7, T6 and T5 respectively. The equalizing circuit 4 comprises two identical amplifiers EQ3 and EQ"-*. EQ3 includes a pair of transistors T12/T13 whose emitters are connected in common to the tapping point of resistors R13 and R14. The other ends of R13 and R14 are connected to IN- and IN+ respectively. The bases of T12 and T13 are respectively connected to V5+ and V5-, and to load resistors R15 and R16 respectively. With their other ends R15 and R16 are connected in common to bias resistor R17 whose other end is connected to the supply voltage terminal V. The collectors of T12 and T13 constitute the output terminals OUTl- and 0UT1+, and are connected to the respective load resistors R18 and R19. The other ends of R18 and R19 are connected to the tapping point of R15/R16/R17.

Likewise, amplifier EQ4 includes a pair of transistors T14/T15 with emitters connected in common to the tapping point of resistors R20 and R21. The other end of R20 and R21 are connected to IN- and IN+ respectively. The bases of T14 and T15 are connected to V6+ and V6-, and to load resistors R22 and R23 respectively. The other ends of R22, R23 are connected to the supply voltage terminal V via resistor R24. The collectors of T14 and T15 are connected to the output terminals 0UT2- and 0UT2+, and to the load resistors R25 and R26 respectively. The other ends of these resistors are connected to the tapping point of R22/R23/R24.

The operation of the circuit of Fig. 3 is described now.

A differential signal having a predetermined very high frequency e.g. 1GHz is applied across input terminals IN- and IN+. The values of Rl, R2 and Cl constituting the integrator circuit A are so chosen that for this frequency a phase shift of -45 degrees is obtained between the signals IN+, IN- and V1+, V1-. Similarly, the values of Cl, C2, R3 and R4» constituting the differentiator circuit B are so chosen that a phase shift of +45 degrees is obtained between the signals IN+, IN- and V2+, V2-. Thus a phase difference of 90 degrees is created between the signal V1+/V1- and the signal V2+/V2-. However, since the circuit is built in Integrated Circuit technology wherein the absolute accuracy of components is very poor, the figure of 90 degrees is far from exact. To obtain an accurate phase shift of 90 degrees, the geometric principle described above is applied. Firstly, two signals of equal amplitude are derived fro the signals V1+/V1- and V2+/V2-. This is done by the above described circuits EQl and EQ2.

EQl for instance operates as follows : as soon as the input signal V1+/V1- is positive, i.e. when V1+ is positive with respect to V1-, the current II trough the emitter resistor R7 flows completely through transistor T2. In the opposite case, when V1+ is negative with respect to V1-, the complete current II flows through transistor Tl. EQl thus operates as a comparator circuit which outputs a constant current II through V3+ if V1+ > V1-, or through V3- if V1+ < V1-. It is a limiting amplifier which corrects the signal amplitude of IN+/IN- to a value determined by the current II.

Likewise, amplifier EQ2, described above, outputs an equal current II through V4+ if V2+ > V2-, and through V4- if V2+ < V2-. The result is two equalised differential signals V3+/V3- and V +/V4- with a square wave shape on terminals V3+/V3- and V4+/V4-.

These equalised signals are then added and subtracted in phase shifting circuit C3. The above mentioned currents II possibly flowing through V3+, V3-, V + and V4- are each split in two equal parts 11/2. For instance, if II flows through transistor Tl, 11/2 flows through each of the transistors T8 and T9. Likewise, the currents through V3-, V4+ and V4- are respectively split by transistor pairs TlO/Tll, T4/T5 and T6/T7. To be noted that transistors T /T5, T6/T7, T8/T9, TlO/Tll are in a cascode configuration with transistors T3, T4, Tl and T2 respectively, and have their bases connected together and biased by resistors R9 to R12.

The current through T9 is added to that through T4 because the collectors of these transistors are connected together to a common load R15 of circuit CA. Thereby a sum signal V5+ proportional to (V3+) + (V +) is obtained. Because the collectors of T7 and T10 are connected together to R16 this gives rise to a sum signal V5- proportional to (V3-) + (V4-). V5+ and V5- together constitute the differential sum signal.

Likewise, by connecting the collectors of T6 and T8 to R22, a signal V6+ proportional to (V3+) + (V4-) is obtained, which can also be written as (V3+) - (V4+) since V4+ is the opposite of V4-. Thus V6+ is the difference signal, together with V6-, obtained from the connection of collectors T5 and Til to R23, and proportional to (V3-) + (V4+), which can also be written as (V3-) - (V4-). The differential difference signal is V6+, V6-. The above sum and difference signals are now already orthogonal and accurately shifted 90 degrees in phase, but they do not necessarily have the same amplitude. Therefore these signals are equalised in the equalising circuit C which comprises amplifiers EQ3 and EQ4. EQ3 for instance includes an emitter coupled pair of transistors, with two equal resistances R13 and R14 respectively connected to IN- and IN+. This configuration of emitter resistances is equivalent to a single resistor connected to a point at a fixed DC level, but has the advantage of saving power since resistors R13 and R14 at the same time constitute a load for the signal IN+/ IN-. Through the common emitter path flows a current 12. Similar to the case of EQl and EQ2, EQ3 works in comparator mode, so that the current 12 flows either completely through transistor T12 when V5+ > V5-, or through transistor T13 in the opposite case. The current of T12 flows through resistor R18, and that of T13 through R19, thereby generating the respective components OUTl- and 0UT1+ of a differential output voltage signal. Resistor R17 serves for limiting the voltage swing of 0UT1+ and 0UT1-. Amplifier EQ4 operates in a way identical to EQ3> and produces from V6+ and V6- a signal 0UT2+/0UT2- having an amplitude equal to that of 0UT1+/0UT2-, since the common emitter currents are both equal to 12. While signals 0UT1+/0UT1- and 0UT1+/OUT2- would have square wave shapes at low frequencies due to the comparator function, they have sinusoidal shapes in the frequency range of mobile radio systems, due to the filtering action of the transistors of circuit C4 by parasitic capacitances.

To be noted that although in the above description the circuit Cl produces two signals which have a phase shift of about 90 degrees, this is not absolutely necessary. This phase shift could have any value greater than 0 degrees and smaller than 180 degrees. Providing however the phase shift of circuit Cl close to 90 degrees improves the accuracy of the phase shifter.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims

1. Phase shifter able to derive from an input signal (IN) two signals (V5, V6) intended to be mutually phase- shifted by ninety degrees, characterized in that it includes a first phase shifting circuit (Cl) which derives from said input signal (IN) two first intermediate signals (VI, V2) having a phase shift greater than 0 degrees and smaller than 180 degrees, an equalising circuit (C2) which converts said two first intermediate signals (VI, V2) to two second intermediate signals (V3, V4) with equal amplitudes and a second phase shifting circuit (C3) which generates a sum (V5) and a difference (V6) signal of said second intermediate signals, said sum and difference signals being mutually phase shifted by ninety degrees.

2. Phase shifter according to claim 1, characterized in that it further includes a second equalizing circuit (CA) which converts said sum (V5) and difference (V6) signal to two output signals (OUTl, 0UT2) with equal amplitudes.

3. Phase shifter according to claim 1, characterized in that said first phase shifting circuit (Cl) produces said first intermediate signals (VI, V2) with a phase shift of about ninety degrees.

4. Phase shifter according to claim 1, characterized in that said first phase shifting circuit (Cl) includes an integrator circuit (A) which acomplishes a negative phase shift between said input signal (IN) and a first (VI) of said first intermediate signals (VI, V2), and a differentiator circuit (B) which acomplishes a positive phase shift between said input signal (IN) and a second (V2) of said first intermediate signals (VI, V2).

5. Phase shifter according to claim 2, characterized in that all said signals (IN, OUTl, 0UT2, VI, V2, V3, V4, V5, V6) are differential signals (IN+/IN-, 0UT1+/0UT1-, 0UT2+/0UT2-, V1+/V1-, V2+/V2-, V3+/V3-, V4+/V4-, V5+/V5-, V6+/V6-) .

6. Phase shifter according to claims 1 and 5, characterized in that said equalising circuit (C2) comprises identical first (EQl) and second (EQ2) comparator differential amplifiers having inputs to which first (V1+/V1-) and second (V2+/V2-) of said first intermediate signals are differentially applied respectively and having outputs on which first (V3+/V3-) and second (V4+/V4-) of said second intermediate signals are differentially generated respectively.

7. Phase shifter according to claim 6, characterized in that said first (EQl) and second (EQ2) comparator differential amplifiers include first (Tl, T2) and second (T3, T4) pairs of transistors respectively, the emitter electrodes of which are connected in common to identical first (R7) and second (R8) emitter impedances respectively, to the base electrodes of which are differentially applied said first and second of said first intermediate signals respectively and on the collectors of which are differentially generated said first and said second of said second intermediate signals respectively.

8. Phase shifter according to claim 7, characterized in that said second phase shifting circuit (C3) includes third (T8, T9), fourth (T10, Til), fifth (T4, T5) and sixth (T6, T7) pairs of transistors, whose emitter electrodes are connected in common two by two in a cascode configuration with the collector electrodes of a first (Tl) and a second (T2) of said first pair of transistors and of a first (T3) and a second (T4) of said second pair of transistors respectively, the base electrodes of said third, fourth, fifth and sixth transistor pairs being commoned, that said sum signal is differentially generated across on the one hand the junction point of a collector electrode of said third pair and a collector electrode of said fifth pair and on the other hand the junction point of a collector electrode of said fourth pair and a collector electrode of said sixth pair, and that said difference signal is differentially generated across on one hand the junction point of another collector electrode of said third pair and another collector electrode of said sixth pair and on the other end the junction point of another collector electrode of said fourth pair and another collector electrode of said fifth pair.

9. Phase shifter according to claim 2 and 5, characterized in that said second equalizing circuit (C4) includes third (EQ3) and fourth (EQ4) comparator differential amplifiers having inputs to which said sum signal (V5+/V5-) and said difference signal (V6+/V6-) are differentially applied respectively and having outputs on which said two output signals (0UT1+/0UT1-, 0UT2+/0UT2-) are differentially generated respectively.

10. Phase shifter according to claim 9, characterized in that said third (EQ3) and fourth (EQ ) comparator differential amplifiers include seventh (T12, T13) and eighth (T14, T15) pairs of transistors respectively, the emitter electrodes of which are connected in common to equal first (R13, R14) and second (R20, R21) emitter impedances respectively, the collector electrodes of which are individually connected to respective equal load impedances (R18, R19, R25, R26), and on the collector electrodes of which said output signals (0UT1+/0UT1-, 0UT2+/0UT2-) are differentially generated.

11. Phase shifter according to claim 1, characterized in that it is integrated on a chip,