WO1990010267A1

WO1990010267A1 - Distributed pipeline control for a computer

Info

Publication number: WO1990010267A1
Application number: PCT/US1990/000938
Authority: WO
Inventors: Harold L. Mcfarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John Gregory Favor; Dale R. Greenley; Robert A. Cargnoni
Original assignee: Nexgen Microsystems
Priority date: 1989-02-24
Filing date: 1990-02-21
Publication date: 1990-09-07
Also published as: JP3153906B2

Abstract

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Description

DISTRIBUTED PIPELINE CONTROL FOR A COMPUTER

BACKGROUND OF THE INVENTION

The present invention relates generally to computers, and more particularly to techniques for efficient pipeline control thereof.

A single cycle implementation of a complex instruction set computer (CISC) architecture requires a deep pipeline. When combined with the complex privilege and protection ch_cks and powerful memory management systems directly supported by a CISC architecture, conventional pipeline control techniques become very complicated. In current technology, the

to include the effects of multiple chip boundary crossings. In attempting to eliminate as many of these crossings as possible, high levels of VLSI integration are chosen. With a relatively small^' number of devices in the system, there aren't enough signal pins to run dedicated buses for every purpose. This means that the buses must be used for multiple purposes, greatly complicating the process of designing a centralized control and scheduling mechanism.

SUMMARY OF THE INVENTION The present invention implements a pipeline control system that is distributed over the functional units in a processor. Each unit defines its own interlocks and pipeline timing. That timing does not have to be precisely mirrored in a centralized controller. The functional units are autonomous, so they do not need to know the precise details of how all other units handle each instruction. The need for complex simulations of pipeline timing is greatly reduced. The invention supports distributed control of the pipeline, by making it possible to back out of modifications to the machine state which should not have been allowed to occur. The invention uses generalized' techniques rather than complex special case pipeline control logic, thereby making correct operation of the pipeline more probable. The distributed control combined with the ability to back out of any unwanted change allows significant performance advantages in the area of out-of-order execution, overlap of penalty cycles, and parallel processing of instructions within and between functional units. The additional cost and complexity to implement these capabilities is very slight.

More particularly, decoder logic issues pseudo-operations (p-ops), each with an associated tag, to a plurality of functional units, which are capable of independently executing p-ops. Up to n p-ops are allowed to be outstanding at a given time. Tags are issued sequentially in a manner that allows the relative age of two outstanding p-ops to be determined. In a specific embodiment the tags are issued over a range of at least 2n and then recycled. This range is sufficient to allow the relative age to be determined by simple subtraction. In a present implementation, 16 tags are issued and 7 p-ops are allowed to be outstanding.

Outstanding p-ops are retired in the order they were issued. A p-op may be retired only when it has completed, i.e., when it has been terminated normally by all concerned functional units.

In some cases, a completed p-op otherwise eligible for retirement will be kept outstanding until one or more adjacent younger p-ops have also completed. The tag of the oldest outstanding p-op is communicated to the functional units so that each unit can determine when it can irrevocably modify the state of the machine. An outstanding p-op is aborted if it is terminated abnormally by a functional unit In such a case, all younger outstanding p-ops are also aborted. Older outstanding p-ops may also have to be aborted if their retirement is contingent on the successful completion of the abnormally terminating p-op. The tag of the oldest outstanding p-op to be aborted is communicated to the functional units. This allows execution to be aborted in the case of unanticipated program diversion and the machine backed up to the point of diversion.

For an instruction set architecture where there are m programmer-visible (virtual) registers, and up to n register-modifying p-ops are allowed to be outstanding, there are provided at least (m+n) physical registers. A mechanism provides for mapping the virtual registers into physical registers. The mapping is modified to employ a previously unused physical register as the destination of each p-op that will modify a virtual register, allowing the old virtual register's value to be retained in the physical register to which it was previously mapped. There are enough physical registers to assure that if the physical registers that are replaced in the mapping are re-used in order, then by the time a physical register must be re-used, any p-op for which it was mapped to a virtual register will have been retired or aborted. The set of pointers defining the virtual-to-physical mapping and a list of available registers are maintained for each of the n most recently issued p-ops, making it possible to abort any outstanding p-ops and return the virtual registers to their previous values without moving data between registers.

A further technique for allowing the state of the processor to be backed up entails the use of write queues. A write reservation queue buffers writes to memory or data cache for at least the period of time during which the originating p-op (the p-op that generates the address and data) is outstanding. Only when processing has passed the point at which it could become necessary to back out of the memory write, is the write reservation queue entry output to the memory. If the originating p-op is aborted, the queue entry is deleted from the queue. In the event that a younger read p-op seeks to access the memory location to be written into by an outstanding write p-op, the data stored in the write reservation queue is provided to the read p-op. If the write p-op retires, the read p-op has acquired the correct data without having to wait for the retirement Conversely, if the write p-op is aborted, the younger read p-op is also aborted, and the machine state is successfully backed up to a point prior to the write. A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS * Fig. 1 is a block diagram of a computer system incorporating the present invention;

Fig. 2 is a high-level block diagram of the decoder (DEC);

Figs. 3A-C are detailed block diagrams of the DE

Figs. 4A-D are block diagrams showing the tracking of a particular sequence;

Fig. 5 is a schematic illustrating register reassignments; Fig. 6 is a block diagram of the memory and cache controller (MCC); and

Fig. 7 is a block diagram of the integer execution unit (IEU).

BRIEF DESCRIPTION OF THE TABLES

Table 1 shows the p-op bus format; Table 2 shows the physical address bus (PAdrBus) format;

Table 3 shows the data cache bus (DIOBus) format;

Table 4 shows the data exchange bus (DXBus) format;

Table 5 shows the IEU termination bus format;

Table 6 shows the AP termination bus format; and Table 7 shows a sequence of p-op issuances and terminations.

DESCRIPTION OF A SPECIFIC EMBODIMENT System Overview

Fig. 1 is a block diagram of a CPU 10 incorporating the present invention. The CPU, sometimes referred to as the F86, is designed to execute an instruction set (macro-instructions) compatible with that of the Intel 80386, as described in the Intel 80386 Programmer's Reference Manual published by Intel Corporation, Santa Clara, California, 1986. Each block in the diagram corresponds generally to a separate integrated circuit chip or group of chips in a current embodiment The CPU communicates with external devices such as memory controllers, I/O devices, and possibly other CPU's via a system bus 11. References below to functional units will normally be understood to mean elements within CPU 10, not such external devices.

An Instruction Decoder (DEC) 12 performs instruction fetch, instruction decode, and pipeline control. DEC 12 optionally interleaves instruction prefetch of up to three simultaneous instruction streams. DEC 12 contains a fully associative Branch Prediction Cache (BPC) 13. The BPC is an integrated structure which contains dynamic branch history data, a physical branch target address, and a branch target buffer for each cache entry. As branch instructions are decoded, the BPC is consulted for information about that branch. Independent of the direction predicted, branches are executed in a single cycle and do not cause pipeline bubbles. On each cycle, a macro-instruction is selected from one of the three instruction buffers or a branch target buffer in the BPC. The macro-instruction is decoded, assembled into an internal 96-bit decoded instruction word, referred to as a pseudo-op (p-op) or sometimes as an instruction or operation, and dispatched to the various functional units. Instruction decode generally proceeds at a single cycle rate. Each p-op issued by DEC 12 is given a tag which uniquely identifies each p-op currently outstanding in the machine. Tags are issued in increasing order, allowing easy determination of relative age of any two outstanding tags. Bus transactions between chips include the tag of the originating p-op. Functional units pair up p-op, addresses, and operands with these tags.

DEC 12 is also responsible for tracking the status of outstanding p-op, pipeline control, and for invoking exception processing when needed.

An address Preparation Unit (AP) 15 calculates effective addresses, performs segment relocation, and implements a demand paged memory management system. It contains a translation lookaside buffer (TLB).

An Integer Execution Unit (IEU) 17 performs single cycle execution of most integer instructions. It contains an 8 x 32 multiplier and accumulator array, as well as microcode for multiply and divide instructions. The pipeline control architecture allows the IEU to perform parallel and/or out-of-order execution of integer instructions.

A Numerics Processor (NP) 20 may optionally be included in the CPU. It is a high performance implementation of the IEEE floating point standard. The NP is integrated into the pipeline and does not incur any special overhead for the transfer of instructions and operands.

Integer (IEU) and floating point (NP) instructions execute concurrently.

A Memory and Cache Controller (MCC) 25 is responsible for controlling the instruction and data caches and implements the cache coherency protocol. The MCC controls the interface to the system bus 11, supporting high speed single and block mode transfers between cache and memory. As described below, the MCC also contains write reservation tables for integer, floating point, and system writes, and includes read after write short circuit paths.

An instruction cache subsystem includes a tag RAM chip (ITag) 27 and cache RAM chips (ICache) 30. Each entry in ITag 27 contains the address tag, a Valid bit, and an Attention bit for a corresponding line in ICache 30. The Attention bit indicates that the DEC chip may also have data from this line cached in the BPC ITag 27 also includes a set of instruction stream address registers

31, each of which contains a fetch address associated with a respective one of three possibly outstanding streams.

A data cache subsystem includes a tag RAM chip (DTag) 32 and cache RAM chips (ICache) 35. DTag 32 contains the address tag and line state bits for each line in DCache 35. The possible line states are Absent, Shared Read, Owned Clean, and Owned Dirty, supporting a writeback multiprocessor cache coherency protocol (modified write once). The tag RAM is dual ported to allow both CPU and bus snooping cache lookups in a single cycle. A Data Cache Interface (DCI) chip 37 interfaces DCache 35 to system bus 11. Each functional unit chip is packaged in a custom ceramic PGA which contains power and ground planes and associated decoupling capacitors. Roughly 25% of the pins are dedicated to power and ground. For 0.8 micron to 1.2 micron processes, I/O delays are comparable to on-chip critical paths. Inter-chip I/O is incorporated into the pipeline, and thus does not add to the machine cycle time. ICache 30 and DCache 35 use conventional static RAMs.

Communications between the various functional units are carried out over a number of internal buses. These include: a 64-bit IFETCH_DATA bus 50 for instruction fetches; a 104-bit p-op bus 52 for communicating issued p-ops to the AP, the IEU, the MCC, and the NP; a 5-bit tag status bus 53 for communicating outstanding p-op information to the AP, the IEU, the MCC and the NP; a 32-bit physical address bus (PAdrBus) 55 for communicating physical addresses; a 64-bit (32 bits in each direction) data cache bus (DIOBus) 57 for data cache transfers; a 32-bit data exchange bus (DXBus) 58 for inter-chip exchange; a 64-bit bus for cache/memory updates; and a number of termination buses, namely an AP termination bus 60, an IEU termination bus 62, an NP termination bus 63, and an MCC termination bus 65 from the functional units to DEC 12. Some of these buses are full width and some half-width (time multiplexed). Interactions between functional units are generally limited to well defined transactions on the internal processor buses.

A number of these buses are described in more detail below. References to usage of the standard CMOS-style time-multiplexed I/O imply that the transfers occur on the boundaries between Phase 1 (#1) and Phase 2 (≠2) of the system clock. A $2 transfer requires the transmitting chip to set up valid data to its I/O driver before the end of 1; valid data is provided by the I/O receiver of the receiving chip during the following #2. A ≠l transfer has just the opposite timing. .

Tables 1-6 show the bus formats for p-op bus 52, PAdrBus 55, DIOBus 57, DXBus 58, IEU termination bus 62, and AP termination bus 60, respectively.

Pipeline Control System Overview

Pipeline control of the processor is distributed across the functional units mentioned above. No centralized scheduling or score boarding of the pipeline is performed. DEC 12 does observe certain overall resource constraints in the architecture and will occasionally hold off on issuing a p-op which would violate resource limitations. Each functional unit is responsible for scheduling its own internal operations. Interlock checking is performed at a local level.

In a deeply pipelined machine, exception detection at various stages in the pipeline creates significant control difficulties. Each stage must be careful to hold off modification of state while any other stage may yet detect an exception on a previous instruction. Special purpose control logic is common, and careful pipeline simulations must be performed. The processor deals with this complexify using a few techniques which are simple, general, and powerful. DEC 12 issues decoded instructions (p-ops) and the functional units process addresses and operands without regard for the consequences of exceptions detected by other functional units. As noted above, each p-op is assigned a tag by DEC 12 when it is issued, and the DEC uses this tag to track the p-op. DEC 12 is responsible for determining when execution has proceeded beyond the point of an exception. Using techniques described below, the DEC will restore the state of the machine to the point immediately preceding (fault exceptions) or following (trap exceptions) the p-op causing the exception. As noted above, each functional unit has a termination bus back to DEC 12. Signals on these buses indicate (by tag) when p-ops have been completed and what exceptions (if any) were detected by that unit The DEC uses this information to keep track of what p-ops are outstanding in the machine, to track resource constraints, and to decide when exception processing must be initiated. In response to abnormal terminations, DEC 12 will back up the state of the machine to the point of the exception, and begin issuing either a different instruction stream or a sequence of micro-instructions to invoke an exception handler. The processor uses one or more of five general mechanisms to permit the machine to be backed up to a particular state as part of DEC'S response to abnormal terminations. These are issuing abort cycles, reassigning registers, using write reservation tables, using history stacks, and functional unit serialization. Abort cycles are issued by DEC 12 when instructions which have been issued by the DEC must be flushed from the machine. During an abort cycle all functional units are provided a tag which identifies the boundary between instructions which should be allowed to complete and instructions which must be purged from the machine.

Register reassignment is used to restore the state of the general register files and the segment register file, flushing any modifications made for instructions which must be aborted. The functional units have more registers physically available than the instruction set specifies. DEC 12 maintains a set of pointers which map the programmer visible (or virtual) registers onto the physical registers. In assembling decoded instructions, the DEC will substitute the appropriate physical register numbers into the register specification fields. When a virtual register is to be modified, the DEC will first allocate a new physical register, modify the pointer set, and use the allocated register number as a destination register. Following execution of the instruction, the old physical register still contains the original value of the virtual register, while the new physical register contains the modified value of the virtual register. To back out of the register modification, the DEC must restore the pointer set to its value prior to issue of the instruction.

As physical registers are freed up, they are placed at the end of a free list which is sufficiently long to guarantee that a physical register will not appear at the head of the free list until after its contents are no longer required. The DEC maintains a history stack of pointer values, as is described below. Write reservation tables are used in MCC 25 to queue up data writes until it is known that the writes will not have to be aborted. The MCC receives addresses and operands on the internal data buses, matches them up by tag, and performs the irreversible write when it is safe to do so. s ory s ac s are use or sav ng an res o ng m sce aneous mac ne s a e, suc as e register reassignment pointers, flags register, and program counter.

For machine state which is rarely modified, the cost of a history stack of values is not justified. For these cases, the functional unit which is to perform the modification (and only that unit) halts processing, and the tag of the oldest outstanding instruction in the machine (as provided by the DEC) is examined on each cycle to determine when all older instructions in the machine have been successfully completed. At this point there is no longer any need to preserve the old value of the machine state and the functional unit makes an irreversible change to the machine state.

The distributed pipeline control scheme, combined with the ability to back out of any state modification, allows a number of performance optimizations.

Each functional unit may receive all p-ops, but deals only with p-ops which actually require processing in that unit This is in contrast to conventional pipelines in which instructions flow through all stages in the pipeline, whether the stage has useful work to do or not.

Furthermore, each unit performs an operation as soon as all input operands are available. P-ops that are not ready for immediate execution are stored in that unit's p-op queue. When complete, the result is passed to the next stage for further processing, and the next operation is examined. A stage only stops execution when it has nothing available for execution.

This behavior allows out-of-order execution between functional units. For a memory write which has an address generate interlock, for example, the AP will not be able to compute the memory address. The IEU, however, is able to provide the data and does so immediately, after which it continues on to the next instruction. The AP's interlock does not need to create a pipeline bubble in any other pipeline stage. Later on, the IEU may be held up performing a multiply, or waiting for a memory operand. At this time, the AP has a chance to catch-up with the IEU.

From the viewpoint of a particular functional unit, this isn't a complicated concept The functional unit makes a local decision, completely unaware that it might cause instructions to be completed out-of-order. The pipeline control mechanisms guarantee that any modifications made by an instruction executed out-of-order can be purged. The functional unit makes no special checks.

Out-of-order execution between functional units happens for free ≥s a result of the distributed decision making within the processor. Even within a functional unit, instructions could be safely executed out of order. IEU 17 provides an example of internal out of order execution. The

IEU examines the instruαion at the head of it's instruction queue to see if it is ready to execute. If a data interlock prevents immediate execution, the IEU will examine the next younger instruction to see if it is ready to execute. This process can continue until an instruction is found which can execute. The IEU will only pay a data interlock penalty if there is no instruction available which is ready to execute.

Note that even if the IEU pays an interlock penalty, that doesn't mean that the processor as a whole loses a cycle. The IEU may have been running ahead of other functional units at the time. Even if the IEU falls behind, it may be able to catch up later when an instruction is issued which does not require the IEU. Finally, the penalty cycle(s) may be overlapped with penalty cycle(s) from AP 15.

A special case of a functional unit choosing to execute instructions out-of-order is parallel execution of instructions within the functional unit In particular, this concept is applied to instructions which take multiple cycles. Parallel execution of other single cycle instructions allows the multi-cycle instruction to have an effective throughput of one cycle.

DCache misses would normally stop the pipeline for a full cache miss penalty. To the extent that the functional units can continue to find operations that can be executed without the cache data, the cache miss penalty is reduced. The same is true for misses in the AP chip's TLB. These cases are different from the others in that the number of penalty cycles is usually fairly high, making it difficult to fully overlap them with useful work.

Pseudo-Op Bus Format

Table 1 shows the format of p-op bus 52. The bus is a 52-bit wide, time-multiplexed bus. DEC 12 alone drives this bus to issue p-ops to AP, IEU, and NP. The bus uses the standard CMOS- style time-multiplexed I/O.

Typically, one 386387 macro-instruction is transformed by DEC to one p-op issued to the relevant functional units. In some cases one macro-instruction will result in a sequence of issued p-ops. Such p-op issue sequences are atomic, i.e., the issue of p-ops for one macro-instruction is not interleaved with the issue of p-ops for another macro-instruction (or exception processing sequence).

For a typical macro-instruction one p-op contains enough information to enable all relevant functional units to perform the requisite operations for the macro-instruction. This includes specifying memory operand address calculation and segmentation, source and destination operand registers, ALU operation, operand size, operand routing, status flag modification, and p-op tag, as well as any associated displacement and/or immediate data values. NP p-ops also specify a micro-address.

Most p-ops are transferred over the p-op bus in one clock cycle using both clock phases (#1 and Φ2). #1 is used for transferring almost all of the control information contained in a p-op, while #2 is used to transfer displacements and/or immediate values (along with a few sundry extra bits of control information). In certain cases of p-ops containing both a displacement and an immediate value, which cannot be packed together in 52 bits, a second clock cycle is used to transfer the immediate value. This second cycle always immediately follows the first clock cycle. The displacement is transferred on the first #2 and the immediate value on the second +2.

DEC 12 drives the p-op bus during all clock cycles. Usually this will be a normal p-op, but during cycles in which DEC is not ready or able to issue a normal p-op, DEC instead sends out a null p-op.

The philosophy of encoding information in a p-op is foremost based on providing control information as early as possible in a clock cycle and in an unencoded or quickly decodable form. This is particularly true with respect to initiating speed critical operations in each functional unit, and with respect to extracting displacement and immediate values and deriving the appropriate address and data operands. Only less critical control information is transferred during Φ2 while generally the intention is that during $2 each functional unit is assembling/fetching operands both from registers and from the p-op; on the following *1 each functional unit should be able start internal calculations and the like. As noted above, most macro-instructions are converted to a single p-op; this includes some of the more complex macro-instructions for which the complexity must be dealt with via microcode in one of the functional units (e.g. multiply in IEU, POPA in AP). Where possible though, complex macro-instructions are converted to p-op sequences which are independently executed by the functional units without awareness of the overall sequence. In some cases a p-op sequence is inherently necessary due to the amount or nature of control information that needs to be communicated, e.g. multiple register reassignments (of which only one per p-op is allowed), multiple p-op tags required by AP for proper memory request generation, or multiple register and status flag updates by AP to IEU.

For some complex macro-instructions a combination of the above can also occur, namely a sequence of p-ops is issued and one of the functional units goes into microcode to execute a core part or all of a macro-instruction in conjunction with following p-ops. For example, the first p-op of a sequence is handled by AP and IEU and additionally AP goes into microcode to perform further operations. These further operations correspond to the following p-ops that are issued. Conceptually the p-ops of the sequence are independently executed by the functional units, and in this case this is literally true for IEU. Due to the nature of the macro-instruction, though, AP needs to have a global awareness of the p-op sequence. Consequently, in this case, AP goes into microcode and simply sync's with the following p-ops. By external appearances AP is independently executing and terminating each p-op while internally AP only uses the p-op tag and one or two other fields of each p-op. There are two additional notes of a general nature to be made regarding the issuing and recognition of p-ops by the functional units. First, most p-ops are not queued by all functional units into their respective p-op input queues. As a result each functional unit will not see, deal with, or spend time on all p-ops. In the general case a p-op is recognized by AP and IEU or by AP and NP. Some p-ops need to only be seen by AP, and one or two are recognized by all three functional units. Only AP sees all p-ops.

Second, when there is some reason for DEC to enter exception processing, it will do so and. begin issuing the associated p-ops even while there are still outstanding preceding _^ops which may require aborting the more recent exception processing related p-ops. In general DEC performs the minimum necessary self-restraint in issuing p-ops so as to insure proper operation from a macro- instruction viewpoint

The relevant point is that from a microscopic viewpoint (i.e. at the level of individual p-ops) there are very few apparent constraints on the p-op sequences that can be issued by DEC or on the timing of their issue, and thus few assumptions that can be made by functional units. This statement also particularly applies to the fact that few assumptions can be made regarding the abortion of p-ops. Only the most basic of constraints are apparent such as the maximum overall number of outstanding p-ops allowed and maximum number of outstanding NP p-ops allowed, and the guarantees about what p-op tags can be active/outstanding at any instant

With regard to ensuring proper macroscopic instruction execution, there is one aspect worth briefly mentioning. Some p-ops modify programmer visible state for which the F86 micro¬ architecture does not support the ability to back out of after modification by the p-op. Conceptually this requires some degree of quiescing the functional units so DEC can ensure that the p-op is to permanently be executed before it is executed at all. This is not done in the gross manner of DEC holding up issue of the p-op (and all following p-ops) until all the functional units have reached a quiescent state. Instead quiescing is done on a localized (functional unit) basis only by each of the units for which quiescing is necessary for the given p-op. DEC is able to issue this and following p-ops while the necessary degree of quiescing is performed by the relevant functional units. Further, units not involved in the quiescing can fully continue to execute the following p-ops.

DEC Overview. Pseudo-Op Tracking, and Issue Control

As each pseudo-op (p-op) is issued by the DEC over the P-Op Bus, it is queued by the appropriate functional units (AP, IEU, NP). Each functional unit then processes its p-op stream in loosely coupled manner with respect to other units, and signals a termination to DEC 12 as each p-op is completed. Fig. 2 is a block diagram of DEC 12, which comprises a Frontend 100, a Decoder 102, and a Backend 105. Fig. 3A shows the DEC Frontend, Fig. 3B shows the DEC Decoder, and Fig. 3C shows the DEC Backend.

DEC Frontend 100 is responsible for fetching and supplying instruction bytes to the Decoder. Instructions are supplied either from BPC 13 or one of three instruction buffers fed by IFETCH_DATA bus 50. Instruαion bytes are supplied (24 bytes at a time) to rotate/shift logic 110 which aligns the instruction on the basis of information from a PC (program counter) register 112.

Eight bytes are provided to Decoder 102, which determines the instruction length and communicates it to PC logic 112. In the event that the instruαion is longer than 8 bytes, 8 bytes are communicated in one cycle and up to 8 instruction bytes on the next

Frontend control logic 115 controls a stream stack 117, and provides stream addresses to ITag 27. There may be up to two outstanding branches and therefore up to three outstanding streams. The control logic issues instruction requests to instruαion stream address registers 31 in ITag 30 specifying what stream to fetch, and receives valid bits qualifying the stream. When the ITag provides an address, it increments the appropriate address register. Control logic 115 also receives signals from PAdrBus monitoring logic 120, which detects writes into the instruction stream for self- modifying code.

DEC Decoder 102 is responsible for decoding macro-instructions and issuing all p-op sequences over p-op bus 52. The Decoder receives instruction bytes (maCTO-instruαions) from Frontend 100, which are loaded into an instruαion register 130, The macro-instruction is decoded by decode logic 132, p-op type decode logic 135 transmits information regarding the p-op type to the Frontend and Backend while instruction length decode logic 137 communicates with PC logic 112 in the Frontend.

Decoder p-op assembly logic 140 receives p-ops from decode logic 132 and modifies them according to register assignment information from the Backend. The p-ops are loaded into a p-op output queue 142 whence they are driven onto p-op bus 52. Issuance is held up by issue hold logic

145 based on control signals from the Backend.

Decoder 102 contains a sequencer 147 to control issuance where multiple p-ops arise out of a single macro-instruction. Decode hold logic 150 prevents processing where no valid instruction bytes are incoming from the Frontend. Associated with issuing the p-op, Decoder 102 assigns a tag. Although the tags are issued in a cyclical sequence, and are therefore reused, at any given time only one p-op is associated with that tag. The range of tags must be sufficiently great relative to the number of p-ops that are allowed to be outstanding so that relative age can be determined. A range of at least twice the maximum number of outstanding p-op allows such a determination by simple subtraαion. Backend 105 keeps track of all outstanding p-ops as they float around through the CPU.

It is necessary to appropriately control the issue of p-ops so as to ensure reliable operation (in the context of the CPU's tagging scheme to control p-op, address, and data processing); and to arbitrate over abnormal conditions signaled by funαional unit terminations, and then initiate appropriate actions. As the Decoder issues a p-op it also passes along information about the p-op to the Backend. This is used to identify the correα actions necessary to perform the above tasks.

The Backend includes tracking logic 160 to keep track of all outstanding p-ops, and hold condition logic 165, responsive to the outstanding p-ops, to control the issue of subsequent p-ops by Decoder 102 so as to continuously satisfy a variety of constraints (to be discussed below) which are required for correα, reliable CPU operation. Tracking logic 160 provides information for tag status bus 53, including the tag of the oldest outstanding p-op (OOTag). The Backend also includes abort logic 170 to handle aborting of p-ops, register reassignment logic 175 which maintains a pointer set array 177 and a free list array 178, to be discussed in detail below, and tag generation logic 179 to control tag status bus 53.

Backend termination bus logic 180 receives termination information from each of the funαional units, making it possible for tracking logic 160 and abort logic 170 to maintain the status of each outstanding p-op. Some are accumulated until some future point in time. During normal operation this tracking primarily influences the issue of following p-ops. But, to the extent that abnormalities are signaled by the funαional units via corresponding terminations, the Backend resolves multiple abnormal terminations of any given p-op, and then initiates the appropriate response. This can include sending an abort cycle out to all the other functional units (including also

MCC) so as to back up the state of the CPU to some prior state of p-op processing.

Tracking logic 160 and abort logic 170 include registers for storing particular information concerning all outstanding p-ops. The registers are organized as eight identical register sets, numbered 0-7 corresponding to the three least significant bits of the tags of outstanding p-ops. Since at most seven p-ops can be outstanding, and since tap are issued sequentially, relative age can be determined on the basis of position number. Tracking logic 160 includes eight each of state registers 190, termination registers 192, and p-op information registers 193, with associated logic Abort logic 170 contains eight each of response seleαion registers 195, priority logic registers 197, and termination storage registers 198, with associated logic

Each state register 190 stores a single state bit that is set if a p-op having a tag corresponding to that position is outstanding. Each termination register 192 stores one termination bit per functional unit; the bit is set when the functional unit terminates the p-op, or if there is no aαion required by that funαional unit with respeα to the p-op. Each p-op information register 193 stores eight bits relating to the associated p-op.

These include the most significant bit of the p-op's tag, which functional units operate on the p-op, the type of p-op (e.g., floating point, branch), branch prediction information, and an abort group bit The abort group bit, when set, signifies that the p-op is the final member of an abort group. Thus, a "0" signifies that the p-op is not the final member, and therefore cannot retire alone, while a "1" signifies that the p-op cannot be aborted without aborting adjacent older p-ops with "0" in their abort group bits.

The collection of state bits allows an identification of the oldest outstanding p-op. The p-op's position provides the three least significant bits of the tag, and the information register provides the most significant bit The state bit and bits in p-op information register 193 allow hold condition computation logic 165 to determine hold conditions, as will be discussed below.

Each response selection register 195 provide information for the Frontend as to what response is necessary. Each priority logic register 197 specifies the appropriate aαion to be taken in response to multiple abnormal terminations on a given p-op. Each termination storage register 198 maintains detailed termination information from the funαional units operating on the associated p- op, including the particulars of any abnormal termination.

For the most part, the funαional units are not concerned with the status of outstanding p-ops, except when an abort occurs. The primary exception to this is MCC 25 which needs to know when it is safe to aαually perform memory and I O writes into the cache and/or out to the rest of the system. In special cases the AP and IEU also need to know when it is safe to execute certain p-ops. All these needs are satisfied by the Backend through the continual issue every clock cycle of information over tag status bus 53, which reflects the OOTag and signals aborts.

Tag Status Bus

Tag status bus 53 is a 5-bit bus whose signals are only defined on *1. When bit <5> is 0, which is the case for most cycles, bits <4..0> indicate OOTag, the tag of the oldest outstanding p-op. When bit <5> is 1, an abort is indicated, and bits <4..0> indicate the tag of a p-op to abort back to. This is called an abort tag (ATag). During an abort cycle Backend 105 overrides the Decoder's issue of its next p-op and forces the issue of one of two types of null p-ops. When the tag status bus indicates the p-op with tag=i is the oldest outstanding p-op this means that all older p-ops (i.e. with tag<i based on 4-bit two's complement arithmetic) are no longer outstanding and are considered retired. All younger issued p-ops, including p-op(i), (Le., p-ops with tag≥i), are outstanding. This of course excludes p-ops issued and subsequently aborted. A p-op's being considered as outstanding means that it is still abortable, and this is in faα the operative definition used by Backend 105 in deciding when to retire p-ops. It generally retires p-ops as soon as possible after they have been completed by all necessary functional units (based on their terminations). There are a variety of constraints, though, which affeα when p-ops may aαually be retired. Some details of this are described below. When the oldest outstanding p-op is retired the tag status bus will reflect this by advancing from indicating OOTag=i to OOtag=i+l. Each and every clock cycle the oldest outstanding tag may advance. It is also possible for an advance to jump from OOTag=i to OOTag=i+n (where l<n<7), effectively retiring several p-ops in one clock cycle. If there are no outstanding p-ops the tag status bus will indicate the next tag to be issued as the oldest outstanding. An abort to p-op with tag=i (p-op(i)) means that all p-ops with tag≥ϊ (based on 4-bit signed two's complement arithmetic) should be flushed and the state of the CPU rolled back to the state as it existed between p-op(i-l) and p-op(i). This includes the next p-op tag to be issued. In other words the abort should flush p-op(i) and all younger p-ops and restore the CPU to a state where these p-ops were apparently never issued. An abort to tag=i can occur at any time, and is not necessarily delayed until p-op(i) is the oldest outstanding p-op. Also, such an abort may occur when no p-ops with tag≥i exist; it is still guaranteed, though, that the abort tag and the tags of all outstanding p-ops are such that all tag comparisons for relative age are still reliable. (As a side note: if, for example, there are seven outstanding p-ops and this case occurs, then the abort tag must be one greater than the tag of the seventh (i.e. youngest) p-op.)

This flushing and rolling back of state must be performed by each functional unit during (roughly) the cycle that the abort is signaled. This is necessary since Decoder 102 may start issuing new p-ops the very next clock cycle. This is particularly true in association with transfer-of-control macro-instructions whose direction or type (for far transfer controls) is misprediαed. In summary, each funαional unit must clean itself up in one cycle and return to a normal state of processing by the end of that cycle.

In general, during the cycle following an abort cycle either another abort cycle can occur, a p-op can be issued (with more on subsequent cycles), or a simple null p-op can be issued (because the Decoder does not yet have the next p-op ready to issue). Following an abort cycle, assuming the next cycle is not another abort cycle, the p-op tag indicated as oldest outstanding may be the same as it was prior to the abort cycle, or may have advanced some number of tags up to as far as the tag that was aborted back to. This last case would occur when, after the abort, all preceding (older) p-ops are retired and of course all younger outstanding p-ops no longer exist Tag Issue

The following discussion relates to p-op tags, a summary of what they are and how DEC 12 issues them. All tags originate from DEC through being part of all issued p-ops. Each p-op tag is then used by functional units to tag addresses and data associated with each p-op. Given that up to seven outstanding p-ops are allowed, at least a 3-bit tag is required. This is extended with one more significant bit to αeate a 4-bit tag which simplifies the comparison of p-op tags for relative age. Specifically, with tags assigned in the manner described below, a 4-bit two's complement signed comparison reliably indicates the relative age of two tags. Note that, at any point in time, only the three least significant bits are necessary to unambiguously identify p-ops. Relative to the order of maαo-instructions, all p-ops stemming from such instructions are issued in order; tags are also assigned in order. All sixteen tag values are considered valid tags, with tag order defined as next_tag := (current_tag+l) mod 16. Consequently, the above comparison for relative age reliably works.

During instruαion processing without aborts the above is straightforward. When an abort occurs back to tag=i, and CPU state is rolled back to just before p-op(i), tag assignment is also reset back to tag=i. To continue to ensure the reliability of relative age comparison, DEC must issue new p-ops from this point starting with tag=i. Effectively, the tap of p-ops which were aborted are reissued with the new p-ops. This means, for example, that an abort back to a point earlier than a prior abort has the same effect as if only the second abort had occurred. More generally, a virtually unlimited set of scenarios, with regard to abort cycles and p-op tag issue, can occur. For example: p-ops(3-7) are outstanding, then abort to p-op(5), issue tap 5-8, abort to p-op(6), abort to p-op(4), issue tap 4-5, abort to p-op(3), issue more p-ops, etc Although this scenario may or may not be possible, given CPU operation and DEC funαional behavior, the point is that very little past the above tag issue behavior should be assumed about the relationship between issuance and abortion of p-ops. As explained in the previous subseαion, with each abort each functional unit should just clean up quickly, get back into a normal state of operation, and forget about the abort.

Pseudo-Op Retirement As p-ops are processed by each functional unit, terminations are signaled to DEC on the units' termination buses, indicating the completion of the p-op by the functional unit These are monitored and tracked by the Backend to control when p-ops are retired. Though there may be special-case internal reasons why the Backend may delay the retirement of a p-op, generally there are two issues which govern when a p-op is retired: ensuring proper CPU behavior in normal circumstances and ensuring proper abortability of macro-iπstruαions (and also exception processing sequences).

Most fundamentally a p-op cannot be retired until all concerned funαional units have signaled a (generally normal) termination of the p-op. As the Decoder of DEC issues a p-op, it also passes information to the Backend about the type of p-op. This includes the funαional units which w be processing the p-op and thus wh ch to expeα a termination from. Based on this information, the Backend will retire a p-op as soon as possible after it has been fully terminated, Le., completed, subjeα to any other constraints.

For single and short p-op sequence macro-instructions the DEC must handle aborting the entire instruαion (i.e. all its p-ops) if a fault exception is deteαed on any of the p-ops. This requires that the Backend not retire any of the p-ops until all of them have completed (with normal terminations). Once they all have successfully completed, they will all simultaneously be retired.

Note that for p-op sequences which approach the limit of maximum seven p-ops outstanding, this approach to instruction abort becomes undesirable. For example, assuming a seven p-op sequence for an instruαion, a DEC quiesce effectively occurs after the seventh p-op is issued while DEC waits to receive full termination on all seven p-ops before issuing any more p-ops. For p-op sequences which are longer than seven pops in length a different approach is absolutely necessary in supporting proper instruction abort.

In some cases this can be handled through a combination of allowing certain memory writes by the instruction to actually occur anyway. In some cases it is also possible/acceptable to use one or more extra p-ops at the beginning of the p-op sequence to do certain extra checks which will detect any exception faults that would otherwise not be detected until one of the later p-ops in the sequence. The intention is that between these extra up-front checks plus checks done by the first p-op (or so) of the real p-op sequence, only one of these early p-ops can lead to an instruction abort; all the later p-ops are then guaranteed to execute without exception fault

With these approaches to supporting instruction abort, only the early p-ops need to be held outstanding until they have all successfully completed. Specifically it is indicated with such sequences that only the first so many p-ops of the sequence need to be handled in this manner by DEC (namely by the Backend), and that the rest of the p-ops are not so constrained. Inside DEC information to this effeα is passed from the Decoder to the Backend as each pop is issued. In many cases where extra up-front p-ops, in combination with just the first p-op of the real sequence, are sufficient to catch all exception faults, it is alright to allow even the early p-ops to be retired as soon as they are each completed. This would be acceptable if the extra p-ops don't significantly affeα backing out of the instruαion (Le they don't modify programmer-visible state). The last general consideration in retiring p-ops is that, even though all the p-ops of a sequence for a maαo-instruαion may have completed, if an earlier p-op has not yet completed, then the completed, later p-ops cannot be retired. This is essentially another way to view the fact that p-ops must be retired in order. Once the older p-op completes and can be retired, though, both it and these later p-ops will all be retired simultaneously. Table 7 illustrates a sequence of tag issuances and terminations. Four points in the sequence, designated A, B, C and D are indicated and define the boundaries of four intervals. Fip. 4A-D illustrate the information that is stored in the registers of tracking logic 160 and abort logic 170 at sequence points A-D, respectively. Single p-ops or groups of p-ops are designated as belonging to abort groups. An abort group consists of one or more p-ops that must all complete for any to complete Put another way, if it is necessary to abort one of the p-ops in the abort group, it is necessary to abort all the p-ops in the abort group.

During the first interval p-ops(3,4,5) are issued with p-ops(4,5) belonging to an abort group (AG). Fig. 4A shows the information that is in the tracking and abort logic registers. More particularly, as the p-ops are issued, p-op information is stored in locations corresponding to the tap numbers, the state registers for p-ops(3,4,5) are set, designating the p-ops as having been issued. The abort bits for p-ops(3,5) are set, indicating that p-ops(4,5) belong to an abort group while p-op(3) is the sole member of an abort group.

During the second interval p-op(6) is issued and AP signifies a normal termination of p-op(3). As can be seen in Fig. 4B, the state bit for p-op(6) is set in state register 190(6), the AP termination bit for p-op(3) is set in termination register 192(3), and the normal AP termination is written into termination storage register 198(3).

During the third interval, p-ops(7,8,9) are issued, with p-ops(7,8) belonging to an abort group. During this interval, IEU indicates that p-op(3) terminated normally, AP indicates that p-op(4) terminated normally, and IEU indicates that p-op(6) terminated normally. Fig. 4C shows that state bits for p-ops(7,8,9) are set in state registers 190(7), 190(0), and 190(1), the IEU termination bits are set in termination registers 192(3) and 192(6), and the AP termination bit is set in termination register 192(4). Corresponding normal terminations are written into termination storage registers 198(3), 198(6), and 198(4). Also note that p-op(3) was allowed to retire, whereupon the state bit in state register 190(3) is negated.

During the fourth interval, no additional p-ops are issued since there are seven outstanding p-ops, which is the maximum number allowed to be outstanding. During this interval, the AP indicates that p-ops(5,6,7) have terminated normally and IEU indicates that p-ops(4,5,9) have terminated normally. However, AP then indicates that p-op(8) has terminated abnormally (for example, a page fault), after which IEU indicates that p-op(7) has terminated normally. The result is that p-ops(4,5,6) can be retired, whereupon they are no longer indicated as outstanding p-ops. However, the abnormal termination of p-op(8) requires that p-op(7), which is a member of p-op(8)'s abort group, and p-op(9), which was issued after p-op(8), must also be aborted. Thus, abort logic 170 issues an ATag of 7 to be sent out on the tag status bus to signify to the functional units (in this case AP and IEU) that they must back up as if p-ops(7,8,9) had not been issued.

Pseudo-Op Issue Constraints

As the Backend tracks outstanding p-ops and each functional unit's p-op terminations, hold condition logic 165 in the Backend also uses the status of outstanding p-ops to control the issue of additional p-ops. To ensure correct overall CPU operation and functioning of specific blocks of logic in specific functional units (particularly DEC, AP, and NP), the Backend continuously imposes a variety of constraints about the maximum number of various types of outstanding p-ops. As the limits imposed by these constraints are reached during operation, the Backend generates hold condition signals to the Decoder to control whether the p-op to be issued the next cycle must be delayed.

The Backend generates roughly half a dozen hold condition signals to the Decoder to potentially hold up the next p-op. The Decoder uses these signals to produce the aαual p-op decode/issue hold based on the p-op currently being decoded/assembled and whether signaled hold conditions apply to it Each hold condition corresponds to one or more (similar) constraints. For a given constraint, when the Backend determines that the maximum number are outstanding and that one of these p-ops was not just fully terminated, the corresponding hold condition signal will be asserted. For many constraints it is guaranteed that the oldest outstanding p-op of the relevant type will be the first one to be fully terminated. Also, for some constraints the hold condition is based on outstanding, not fully terminated p-ops, instead of being based on simply all outstanding (Le., not retired) p-ops. Once a p-op is fully terminated, even though it may remain outstanding for several more cycles, it is no longer relevant to some of the constraints associated with hardware limitations of specific functional units.

While the Backend is one of the principal generators of hold conditions to the Decoder, there are several other sources of hold conditions. Such a hold condition signals a limitation which may or may not apply to the current p-op about to be issued. To be completely general about p-op issue control it can be stated that each clock cycle the Pseudo-Op Bus is driven with either a valid p-op or a null p-op, the latter possibly in conjunction with an abort aαion. From the Decoder's viewpoint it will always issue a valid p-op unless any of the following occur:

1) Abort override from Backend;

2) Hold from the Backend;

3) Hold from the BPQ 4) Hold from the VIB (virtual instruction buffer);

5) Decoded only prefixes; and

6) Sending 2nd half of a 2-cycle p-op

Of these, nos. 5 and 6 are generated by the Decoder, and nos. 4 and 5 are only applicable to the first p-ops of maαo-instruction sequences. "Hold from the BPC occurs when the Decoder is attempting to decode the next macro- instruαion and finds a transfer-of-control instruction which may be cached in the BPC (Some types of transfer control instructions will not be cached.) For such an instruction the Decoder at least needs an attempted BPC access to the prediction information of an entry (versus the entry's target stream). The BPC access for this transfer-of-control instruction occurs during the decoding of the instruαion; if this BPC access cycle wasn't available for the Decoder, a BPC hold is generated. If access was available to the BPC for prediction information and a miss occurs, the Decoder can proceed accordingly even though BPC target stream access was not available If a hit occurs and access to both parts of the BPC was not available, then a BPC hold will be generated; otherwise the Decoder can proceed with the prediαion information while the BPC entry's target stream is dumped into the new instruαion queue allocated for this transfer control instruction.

"Hold from the VIB" occurs when the Decoder is attempting to decode the next macro- instruαion but has not received all required instruction bytes (with respect to the instruαion length). The Decoder, past any detected valid prefix bytes, must have at least a valid opcode byte or a VIB hold is forced. If a mod r/m byte is required, based on preliminary decode of the opcode byte, then this must also be present or a VIB hold is again forced. Further, if an s-i-b byte is required, based on preliminary decode of a mod r/m byte, then the same also applies for the s-i-b byte. Given the validity of these bytes, the final instruction byte (actually the VIB word containing it) is checked (and implicitly also all intermediate bytes) - if it is not valid (Le. "Bad" or Empty") a VIB hold is generated.

"Decoded only prefixes" occurs when the Decoder is attempting to decode the next macro- instruction but it has thus far only decoded prefixes, and currently has decoded two more prefixes. The case of one prefix and a second Empty byte may be treated either as a "Hold from the VIB" until the second byte becomes non-Empty, or as a "Decoded only prefixes" with the one prefix byte being consumed and the VIB advanced.

"Sending 2nd half..." occurs when the Decoder just issued the first cycle of a 2-cycle p-op. During this cycle a special null p-op is sent with the additional p-op information while the decode and generation of the next p-op is delayed. "Hold from the Backend" occurs when, for the type of p-op about to be issued, the

Decoder realizes, based on the Backend's signals, that it is not "safe" to issue the p-op immediately. The following lists all the outstanding p-op constraints enforced by the Backend:

1) 7 total p-ops;

2) 2 transfer-of-control p-ops; 3) 1 abort group of p-ops in single-stepping mode;

4) 2 p-ops with segment register reassignments; and

5) 0 more 1st p-ops after a DECquiesce p-op.

The maximum of 7 total outstanding p-ops applies to all unretired p-ops. In general, and thus for this constraint, p-ops are not fully terminated in order. The Backend, though, may only retire p-ops in order.

The maximum of 2 outstanding transfer-of-control pops applies to all such pops, though more correctly the constraint is actually on transfer-of-control maαo-instructions and the 1st p-ops of their p-op sequences. For this constraint transfer-of-control p-ops are counted only while they are outstanding and not fully terminated. When such a p-op is fully terminated, but not yet retired, it is no longer significant with regards to hardware limitations. Depending on when instruαion fetch page αoss requests are generated and how they are handled, the Backend may signal this hold condition even though two transfer control p-ops are not outstanding. But for all cases of there being outstanding instruαion fetch doubleword requests for relatively old sequential instruαion streams there is no impaα with respeα to this constraint Note that IEU is required to terminate transfer- of-control p-ops (ones involving IEU) in order.

When p-op single-stepping is enabled (for hardware debug purposes), p-ops are issued one abort group at a time, fully terminated, and retired before the next one is issued.

Due to the reassignment scheme used for segment registers there can only be two outstanding p-ops which contain segment register reassignments for the data segment registers (Le.

DS, ES, FS, GS). P-ops which only read a segment register or which store into CS and/or SS do not apply towards this constraint, the purpose of which is to ensure abortability past any and all segment register store p-ops. It is not necessary to include stores to CS and SS since APquiesce behavior is applied to CS SS store p-ops already. When a DECquiesce p-op is issued, the Decoder may continue to issue further p-ops in a sequence, but must hold up decoding the next maαo-instruction until certain updated control bit information has been received by the Backend from AP. These control bits are various bits of EFlap which affeα the Decoder's maαo-instruction decoding and p-op assembly process. A p-op which can result in one or more of the EFlap bits' being modified, that the Decoder is dependent on, must be treated as a DECquiesce p-op. This ensures that DEC'S copy of these bits is updated before further macro-instruction decode occurs. Until the expected update is received from AP, the Backend will generate a hold condition to inhibit further maαo-instruction decode and 1st p-op issue

With the exception of an Abort override, all Decoder hold conditions are determined early enough to enable the Decoder to determine its next state of operation by the time the next decode cycle must start (specifically in time to set up the control, etc to advance the currently active instruαion queue, to access the newly active queue and produce new VIB contents, and to perform pre-decode). An abort override is not, and need not be, generated until later since the p-op generated by the Decoder will be discarded and replaced by a null p-op. Simultaneously the Decoder will be jammed and vectored by the Backend to a new p-op sequence to be generated. (Note: there is more than one type of jam and vector with respeα to timing and the vector destination.)

As explained above, for normal hold conditions signaled by the various (DEC internal) units the Decoder interacts with, the Decoder does not receive actual hold signals from each unit Instead each unit sends hold condition signals which are combined (ANDed) with state signals reflecting the type of p-op being generated, to produce aαual hold signals. These, along with additional hold's generated by the Decoder, are combined (ORed) together to produce an overall Decoder Hold which not only controls the p-op issue and Decoder state sequencing, but also is sent to the other units to affeα their state sequencing insofar as their interaαions with the Decoder.

Funαional Unit Quiescing As functional units process p-ops, they must ensure the ability to abort or back out of modifications to most programmer-visible and related state This includes all commonly modified, performance-critical state: general purpose registers, floating point registers, and most segment registers, PC's, and status flap. Other thinp, Le, special state that is seldom modified, are not backed up via a history stack or using register reassignment These are instead handled by limiting when they can be modified by the owning functional unit(s). This process is termed quiescing.

Essentially, for a given special register, the owner(s) delays performing the modification until the associated pop is the oldest outstanding pop. At this point there is no possibility of the pop being aborted due to another (earlier) pop. Further, any possible reasons stemming from this pop which would lead to its being aborted have presumably already been checked. Thus, it is now considered safe to perform the modification. (If the owning/modifying funαional unit can subsequently deteα a reason for backing out of the pop, it must do whatever is necessary so as to be able to undo the modification.) If a pop is processed by other functional units besides AP and requires this kind of handling, only the owning funαional unit is able to signal an abnormal termination. All such pops are defined written such that the other funαional units will always signal a normal termination. If two functional units both own a special register, they will each modify their own copy and the pop will be such that both units will always signal a normal termination. In any given case only the funαional units which are dependent on the special state to be modified by a pop are involved with quiescing. All other functional units which process the p-op will behave normally. In essence quiescing of a pop occurs on a localized basis and only where necessary. As much of the CPU as is possible continues normal processing while only the pop processing by the quiescing functional unit(s) is possibly slowed down. Insofar as AP owns most special registers, most quiescing pops require quiescing by AP only. Many of these are AP only pops, while the rest are AP IEU pops. Quiesces by NP (all on AP/NP pops) are for modifications to the three control registers it possesses. The case of a dual funαional unit quiesce is presently limited to AP and IEU. This occurs when a pop modifies the Direαion Flag of the EFlap register. Since AP and IEU both maintain up-to-date copies, AP and IEU perform parallel but independent quiesces.

Even though a functional unit quiesces when processing a given pop, this does not necessarily mean that the unit quiesces right before beginning processing of the pop. Particularly in the case of AP quiesces it is possible for part of the processing of the pop to be performed before quiescing. It is only necessary for AP to quiesce at the point where the special register is to be modified. After quiescing is completed AP can perform the modification and continue processing.

DEC can also perform a quiesce, but this is only somewhat similar to the quiescing performed by other functional units. Following the issue of a DECquiesce pop, DEC delays the assembly and issue of certain pops. This delay occurs until a Control Bit Update is received by DEC from AP. For further explanation of DEC quiescing see the previous sub-section. For description of Control Bit Update see the section below describing the AP termination bus.

In DEC quiesce cases, as well as in other cases in which DEC receives a Control Bit Update from AP, DEC copies of certain special control bits are updated. This occurs in conjunαion with modification by AP of its own copy of these control bits. The copies held by DEC are not viewed as master copies owned by DEC, but instead as secondary copies maintained in DEC by AP. DEC does not possess the ability to back out of updates to these control bits. This is not a problem, though, since AP must also modify its master copy of these bits and it will not send Control Bit Update before modifying its own copy. This requires an APquiesce and thus the update of DEC'S control bit copies will effectively be delayed by AP until the associated pop is oldest outstanding.

Abnormal Termination Handling

As described above, the Backend monitors each funαional unit's terminations of pops and accumulates status about all outstanding pops. Based on this information the Backend controls the retirement of pops (generally after having been normally terminated by all concerned units, versus abnormally terminated) and influences when new pops are issued by the Decoder. When pops are completed and have received one or more abnormal terminations, the Backend is also responsible for determining the appropriate response and then initiating it at the appropriate time

As the Backend receives terminations for a given pop, including abnormal terminations, it generally just accumulates them until all expected terminations have been received. Then, if there were any abnormal terminations the pop will not be allowed to retire. At this time the Backend will then initiate the appropriate response. If there were multiple abnormal terminations the Backend will also prioritize and select the abnormal termination to respond to. Both of these aspects of abnormal termination handling are discussed below.

This waiting before initiating a response is done to minimize the design complications of handing interaαion cases stemming from abnormal termination responses being nested/superseded by earlier/older pop abnormal termination responses which are detected and initiated later. Also, given that only abnormal termination cases which result in the initiation exception processing are handled this way, there is no significant performance penalty for waiting.

The specific response initiated by the Backend is dependent on the abnormal termination in question and on whether older pops are outstanding. It is not explicitly dependent on the pop in question, and particularly not explicitly on the opcode of the pop. Often the response will Include sending out an abort cycle with an appropriate tag (which isn't necessarily the tag of the abnormally terminated pop). During the abort cycle, or during a cycle with a null pop being issued without a concurrent abort, the Backend will jam and veαor the Decoder to a state from which it will continue decode and pop issue operation. For cases where exception processing must be initiated, the

Decoder is veαored to an appropriate pop sequence which it will assemble and issue before returning to maαo-instruction processing. Depending on the type of exception being initiated, the abnormally terminated pop may be included in an abort or may be retired in a normal fashion.

For most cases in which the abnormal termination to be responded to does not result in exception processing, there is immediate response initiation once the pop is fully terminated. For a few special abnormal terminations a response occurs immediately after the termination is received by the Backend. These terminations are not considered normal terminations but are more of an informative nature Further, these terminations are not true terminations in that a subsequent termination is still expected and required from the functional unit generating the special abnormal termination.

The responses for these cases are similar to those above which involve initiating exception processing, and also include the possibility of not only veαoring to some appropriate pop sequence, but also instead veαoring back to the macro -instruαion stream. In other words, the later pops in a pop sequence would be aborted and the Decoder would then continue decoding the maαo-instruction stream starting with the next instruαion (from the current or a different instruαion queue). Also, for a few of the abnormal terminations the response may not direαly affeα the Decoder and/or would involve other actions internal to DEC being initiated.

IEU Termination Bus

Table 5 shows the format of 5-bit IEU termination bus 62. The bus uses the standard CMOS-style time-multiplexed I/O, and signals normal terminations of pops and two types of abnormal terminations (exceptions and mispredicted branch directions). On *2 the bus provides a 3- bit p-op Tag and a 2-bit Termination Id.

Due to the timing of DEC'S decode and pop assembly pipeline, if an IEU termination code and associated pop tag is sent time-multiplexed on 2-_#l (Le. everything one phase earlier), it is possible for DEC to respond immediately with an abort cycle followed by the correα next pop (from the correα next maαo-instruαion or from the appropriate exception processing pop sequence). In general IEU may and will terminate pops outoforder (with respeα to order of issue by

DEC). There are certain pop specific cases where relative serialization between two pops of the same type must be maintained by IEU insofar as the order in which pops are processed/executed. Generally for these cases execution order is crucial, not termination order. Transferof-control pops, of which IEU only sees conditional (near) transferof-control pops, are required to be terminated in relative serial order by IEU; it is not absolutely necessary, from DEC'S viewpoint, for these pop's to be processed in order.

As IEU processes pops, there are two cases of when they may be terminated: 1) for pops not requiring a DXBus transfer after execution, the pop may be terminated once the correα termination is known; 2) for pops requiring such a transfer after execution, the pop may be terminated once it is known that the transfer is definitely about to occur or is aαually occurring. In either case the termination may occur later than these points in time. In other words, for case no. 1, a pop can be terminated during its ALU operation if the termination is unconditionally normal, or just after the ALU operation is completed if the termination is dependent on the ALU operation. For case no. 2, a pop can be terminated once IEU knows that it won DXBus arbitration for the transfer.

Currently, based on general IEU pipeline and output queue timing and interaction, in conjunction with the timing of IEUTerm ( e, #2-_#l), the following aαual termination behavior is expected of IEU. For pops not needing to transfer a result over the DXBus, the termination will start during the ALU operation cycle. For most pops this is unconditionally a normal termination; for transfer control pops the correα termination is determined during the first part of the alu cycle (this also applies to the INTO instruction pop). Occasionally this termination, not able to go out onto the termination bus, will be queued and will be signaled to DEC later (but of course fairly soon). For pops which need to transfer a result over the DXBus, the termination will start during the transfer cycle and again, if the termination is not able to go out immediately, it will be queued and sent later. •

For the pops associated with the BOUND and REPed string maαo-instructions which fall into case no. 1, and which can result in an abnormal termination and are dependent on the ALU operation, the above timing for case no. 1 pops does not work. For these cases the pops will be treated as if they need to send a result out on the DXBus.

There are two reasons for why terminations will be generated outoforder. First, ΣEU selects pops outoforder to be processed/executed. Second, relative to execution order, IEU may terminate pops further outoforder. Roughly speaking, IEU will terminate case no. 1 pops immediately while case no. 2 pops must first get onto the DXBus, possibly waiting in IEU's data output queue to do so. In the latter case, these pops will be terminated when they do aαually go out onto the DXBus. Additionally, given the queueing of (temporarily) excess case 1) and case 2) terminations, there is also the possiblity of certain high-priority terminations (e.g. transferof-control terminations) being signaled ahead of queued terminations. (Of course the relative serialization of transferof-control pops must be ensured.)

Regardless of outoforder termination, IEU must, in all cases, complete the processing of a pop before terminating it. This includes pops which result in a register update from AP to IEU, or which simply transfer a memory operand to a register. For both types of pops the source operand must be received before the pop is terminated. This is noted as contrast against AP's behavior: for various transfer and register update cases AP can terminate before receiving what effectively is a register update (even given that register result merging may be necessary).

After IEU signals an abnormal termination in response to a deteαed abnormality while processing a pop, it continues processing other pops as if the pop was normally terminated. IEU does not stop processing pops and in some manner wait for eventual response to the abnormal termination.

IEU Terminations

The following describes the terminations set out in Table 5.

No Termination must be signaled whenever there is not a real termination to signal. The termination bus is valid every clock cycle and must always indicate something.

Normal Termination is signaled when no abnormalities are realized during the processing of a pop. Mispredicted Branch Direction Termination is signaled on transferofoontrol pops (which must be conditional near control transfers) when the predicted branch direction is incorrect This is in place of a normal termination for a correctly prediαed branch direction.

The abnormal terminations are for exception reasons, each being used to signal the corresponding architeαurally defined exception. Divide error is used on the pops annotated with

EUabort in the pop sequences for DIV and IDIV maCTO-instruαions. Bounds Check and INTO Overflow are used on the EUabort pops for the BOUND and INTO instruαions respeαively. REPed Instruction Iteration Stop Termination is signaled on the pops of pop sequences for REP'ed string macro-instruαions, specifically on the pops which are annotated with EUabort If the test performed by the pop indicates that iteration of the string maαo-instruction should stop, this termination is signaled in place of a normal termination. This also applies if the pop test indicates that iterations of the string instruction should not even start (Le. perform zero iterations). If no exception is deteαed in these situations, a normal termination is signaled.

Though there is no possibility of the IEU's deteαing multiple abnormalities on one pop, and thus there is no issue of relative priority between IEU's abnormal terminations, there is a priority issue with respeα to other funαional units' terminations. Since there can only be one type of exception for a given pop type in the IEU, DEC'S abort logic can uniquely identify the type of exception based on the pop. IEU abnormal terminations are grouped into several groups based on their priority in being recognized by DEC relative to AP and NP abnormal terminations. Most of the abnormal terminations are grouped in a medium priority group, while the REP Stop termination has low priority.

The Misprediαed Branch Direαion termination is special in that it does not have a specific fixed priority relative to all AP terminations. Instead, the effeαive branch direαion (based on the prediαed direction and the correαness of the prediαion), in combination with AP's termination, determines the action initiated by DEC'S Backend.

AP Termination Bus

Table 6 shows the format of AP termination bus 60. The bus uses the standard CMOS- style time-multiplexed I/O and signals normal terminations and a variety of abnormal terminations of pops.

Due to the timing of DECs decode and pop assembly pipeline, if an AP termination code is sent time-multiplexed one phase earlier (#2-#l) then it is possible for DEC to respond immediately with an abort cycle followed by the correα next pop (from the next maαo-instruction or from the appropriate exception processing or other pop sequence). The encoding of the termination code is such that for the important cases DEC is able to provide ideal response time, either issuing another pop or aborting and issuing a correα next pop. For the other exception cases there will be an effeαive extra cycle in the response time; specifically there will be one cycle before an abort cycle occurs, followed by the correα next pop the next cycle

This extra cycle in handling most abnormal terminations is split between DECs Backend figuring out what's happening and what to do, and DECs Decoder being jammed and veαored, and starting decode for the correct next pop. For the quick terminations the Backend has a limited handling situation. Aiding this quick handling is the faα that the Backend can anticipate the pop tag which the next termination is associated with, because the AP always terminates pops in order. Quick terminations are provided for these situations: normal termination of a pop; control bit update (from AP to DEC), optionally also indicating misprediαed address andor D-bit. For a normal termination the Backend, with the pop tag and information about the type of pop in hand, principally need to refleα this termination in hold condition signals to the Decoder and to the branch control logic For a control bit update without misprediαed address and/or D-bit, the termination bus transfer provides updated values for the control bits in question, after which the Decoder can be allowed to continue decoding the maαo-instruction stream. If misprediαed address andor D-bit is also indicated, the timing of this termination effeαively becomes like all the other non-quick terminations.

As mentioned above, AP must terminate pops in order (with respeα to their order of issue by DEC). This is independent of the order in which AP processes pops, though for other reasons there are constraints on the order in which AP may process pops. In all cases a pop may be terminated any time after it is fully completed. Additionally though, and somewhat similar to the situation for IEU, there are two cases as to the earliest time when pops may be terminated. In case no. 1, for pops not requiring a DXBus transfer after execution, the pop may be terminated once the correα termination is known. In case no. 2, for pop's which do require such a transfer, the pop may be terminated once it is known that the transfer is definitely about to occur. In other words, for case no. 1, a pop can be terminated just after all system memory references and necessary checks (relating to abnormal terminations) have been completed. For case no. 2, a pop can be terminated once AP knows that it won DXBus or PAdrBus arbitration for the transfer and that the transfer will definitely occur. This includes the case of a PAdrBus memory address reference transfer being aborted due to a

TLB miss; the termination cannot occur before knowing whether the transfer will actually complete

Any additional restrictions/ requirements by DEC, specific to certain terminations, are described below.

Note that AP can terminate pops which have been processed, except for receiving a general-purpose register update from IEU, NP, or memory, before the update is received. The update essentially requires no further processing and simply needs to be stored into the appropriate register and register interlock control updated to refleα this. AP is guaranteed to receive these updates by the time that the associated pop is fully terminated, and thus before it is retired. AP of course must still appropriately keep track of expeαed register updates with respeα to aborts occurring. After AP signals an abnormal termination in response to a deteαed abnormality while processing a pop, it appropriately finishes processing of that pop. Depending on the termination,

AP may then suspend processing of further pop's. This behavior occurs after abnormal terminations for which DECs response is to initiate exception processing. In all other cases AP will continue processing. After suspending processing AP will save and/or freeze any necessary internal state and wait for an eventual response to the abnormal termination. This response may never occur and more generally AP must coordinate with all responses which initiate exception processing.

AP Terminations

The following describes the terminations set out in Table 6. Note that, for all the abnormal terminations indicating exceptions on pops, bits <3..0> of the Termination Id directly corresponds to the interrupt number of the exception for which processing should be initiated. The two exceptions to this are the alternative Debug and General Protection fault codes (i.e., 1111 010X) used for special cases. The Shutdown abnormal termination (code = 1111 1001) is also special in that exception processing will not occur, instead DEC will shutdown.

No Termination must be signaled whenever there is not a real termination to signal. The termination bus is valid every clock cycle and must always indicate something. Normal Termination is signaled when no abnormalities are realized during the processing of a pop. Control Bit Update is used in conjunαion with all DECquiesce pops. These are pops which directly or indireαly affeα the state of the IF, D, and/or B bits (found in EFlap and various segment descriptors). When AP has determined the new value(s) of the bit(s) affeαed, this termination is used to send the updated values to DEC

Note that this is not a true termination, and in particular does not terminate the pop causing the control bit change(s). The usual pop termination is still required, and must occur after the control bit update. (The control bit update must follow the termination of the preceding pop as well.) Also note that DEC will continue pop issue once the Control Bit Update termination is received, independent of termination of the pop whenever afterwards. The general idea is that as soon as AP knows the new values of the affected control bits, during the processing of the pop, AP will send the update to DEC and continue with processing of the pop.

Since the above control bits represent programmer-visible bits, AP and DEC must potentially be able to back out of modifications to these bits. To avoid this (with no significant performance impaα), AP modifies its master copy of these bits when it signals a Control Bit Update (as opposed to sometime afterwards), and delays both these actions until the associated pop is the oldest outstanding pop. In essence, the need to signal a Control Bit Update implies an AP quiesce before signaling the update

A second form of Control Bit Update is similar to the first form but also indicates Misprediαed Address and/or D-bit on the bus transfer of the update This is used on transfer control pops for which DEC has predicted the target address (and assumed the D-bit isn't changing). If the (physical) target address prediαed by DEC for a transfer control pop is incorrect (Le., different from the (physical) address generated by AP), then AP must signal this as well as send an updated value for the D-bit AP, of course, must also send out an address update (namely the correα target address) to the instruαion cache tap.

AP does all this by sending out the correα target address over the PAdrBus and concurrently signaling Control Bit Update Termination with Misprediαed address and/or D-bit (The concurrency is required.) The update is similar to the first form above with respeα to sending updated control bit values. In addition, DEC will modify certain internal state appropriately to reflect the misprediction, and will restart instruction fetching and decoding with the correα address and D-bit As above, it is inherently guaranteed that the Decoder will receive updated control bits before it is able to do the next valid maαo-instruction decode.

Unlike the first Control Bit Update, this is a true termination, and in particular terminates the associated transfer control pop. Given the timing of when AP sends out the correct target address and signals the update, AP is able to avoid signaling Control Bit Update Termination if another abnormality was detected (Le, an exception). Thus, AP will either send out the address and signal the update termination, or will signal an abnormal termination (along with an invalidated address).

For a page αoss which results in an abnormality, a PAdrBus transfer does not occur. This can be either because of a segment overrun (which should result in a General Protection fault), a page fault, or both. AP signals an abnormal termination to indicate that a fault occurred. Exception processing will be initiated later if instruction execution truly needs to αoss the page boundary. From AP's viewpoint the processing and termination of a page αoss request is independent of surrounding pops; DEC takes care of appropriately prioritizing an exception on a page αoss with respect to the pop stream and pop exceptions. Each of the abnormal terminations for exception is used to signal the corresponding architeαurally defined exception. In two cases (e.g., General Protection fault) there is a pair of Termination Id's for signaling the exception. One is to be used generally while the other of the pah- is used in certain exception circumstances which need to be distinguished insofar as having different priority relative to abnormal terminations by other functional units (i.e., IEU and NP). It should be noted that some of these abnormal terminations relate to specific maαo- instructions. In particular the 387 Not Available, Invalid Opcode, and General Protection (code = 1111 0100 terminations are signaled on the 1st pops of relevant pop sequences. Further, some of these abnormal terminations, while not relating to specific maαo-instructions, do relate to maαo- instruction boundaries. The General Protection termination (code = 1111 0100 and the Debug termination (code = 1111 0101, for debug faults) are signaled on the 1st pops of macro-instruction pop sequences. The Debug termination (code = 1111 0001, for debug traps) is signaled on the last pop of maαo-instruction and task switch pop sequences.

MCC Termination Bus MCC 25 termination bus 65 is a 1-bit bus that uses the standard CMOS-style time- multiplexed I/O. The actual signal transfer occurs on the #l-#2 boundary (Le, MCC Term is a 2 transfer); the transfer on the other phase boundary is undefined. This bus is used to signal termination of normal memory writes directly resulting from pops. No termination is generated for memory reads, system memory references, and other references (such as I/O). MCC receives memory reference addresses from AP in order (relative to the issue order of pops which result in the memory references). MCC must also terminate memory write references in this order. Because of this, no explicit transfer of a pop tag is necessary for termination signaling. Based on the in order termination of writes, the Backend of DEC which is monitoring the termination buses, will anticipate which pop tag the next termination from MCC is associated with.

The termination of a memory write is signaled when the address is received from AP and is put into the appropriate write reservation queue. This is independent of when the associated data is received by MCC and when the write exits the queue. Writes of read-modify-write operations by a pop are also terminated. For pops which result in a misaligned or greater than four byte memory write, it is necessary for AP to generate more than one word-aligned address. The termination of the write for such a pop is signaled once the last address is put into a reservation queue.

Regardless of MCC terminating pops which result in a memory write, AP generates its own termination of such pops. This occurs when it transfers the last of one or more word-aligned addresses over the PAdrBus to MCC Since MCC is usually able to put the address(es) into a queue immediately, it would not normally be necessary for MCC to indicate the reception of memory write addresses. For cases, though, in which MCC is not immediately able to put an address into the appropriate write reservation queue (due to the queue being full or an overlap with a previous (older) write in one of the queues), a termination by MCC is necessary. In these latter cases the termination would be delayed to thus prevent DEC from advancing pop issue. If MCC did not have a termination of its own which it could delay, then the following could occur. Once AP terminates the pop, DEC would believe that the pop generating the write is completed and safely in a write reservation queue It would proceed to issue seven or more pop tap past the tag associated with this write address. MCC would then have problems handling aborts, matching data with addresses, handling overlapping memory reads, and eventually performing writes to the cache

Consequently, MCC will have the ability to delay putting addresses with overlap problems into a queue (and of course also the ability to hold up AP from sending any more addresses). While MCC delays an address (and assuming this is the last address for one pops write), the termination of the write by MCC will be similarly deferred. Concurrent with the address finally being put into the appropriate queue, MCC will then signal termination.

While a pop, for which a termination from MCC is expeαed, is fully terminated by all expected functional units except MCC DEC will continue to consider the pop outstanding. Essentially, DEC treats MCCs termination of a pop on equal terms with other funαional units' terminations insofar as when a pop may be retired. Insofar as MCC only signals normal terminations, there is no direct interaction with abnormal terminations by other functional units (AP,IEU,NP). Indirectly, though, it will not always be possible for MCC to terminate a pop for which an MCC termination is expeαed. For cases in which AP abnormally terminates a pop and does not generate all the addresses for an associated memory write (and may not be able to), DEC will behave accordingly. Specifically, DEC will recognize these cases, not delay processing of the abnormal termination for MCC's termination, and maintain proper tracking of the pop tap of outstanding memory writes.

There are also special situations where AP will normally terminate a pop but will not generate an associated memory write. In these cases AP will signal Normal Termination, But No Write to indicate to DEC that the write was not issued and consequently not to expert a termination from MCC

NP Termination Bus

The NP termination bus, roughly speaking, is a 2-bit bus (presuming inordet pop termination) and just signals floating point math exceptions. Provision is made in the CPU logic for including the optional NP, but it will not be detailed here

Register Reassignment

As noted above, one of the mechanisms that is used for backing up the state of the CPU in the event that it is necessary to flush instruαions is register reassignment. This technique' entails mapping a set of programmer visible (Le., virtual) registers into a larger set of physical registers. The number of physical registers exceeds the number of virtual registers by at least the maximum number of pops that are allowed to be outstanding and that can modify a register. The technique is applied to both the general register file and the segment register file The particular maαo-instruction architecture (80386) provides eight virtual general registers, designated VR0-VR7, and six virtual segment registers. As noted above, at most seven pops total and at most two pops that change a segment register are allowed to be outstanding. In line with this, AP 15 includes a set of fifteen physical general registers, designated PR1-PR15, and eight physical segment registers, while IEU 17 includes fifteen physical general registers. Although a physical register PRO exists in the IEU, it is used for other purposes.

Fig. 5 is a schematic illustrating the mapping of virtual registers VR0-VR7 to physical registers PR1-PR15. Each of the physical registers has an associated valid bit, indicated schematically as "V." The valid bits are used by the functional unit as described below. In order to support the general register reassignment, Backend register reassignment logic 175 maintains pointer set array 177 and free list array 178. The pointer set array and the free list array each provides storage for eight lists, each list having a 3-bit index corresponding to the 3 least significant bits of the tap of outstanding pops. Each pointer set and each free list is represented by a column in the figure

The pointer set and free list for a given index maintain the state immediately prior to the issuance of a pop whose tag corresponds to the index. The pointer set contains eight entries, corresponding to virtual registers VR0-VR7, each entry containing a pointer to one*of the physical registers. The free list contains seven entries, containing pointers to the physical registers that are not pointed to by members of the pointer set

Assume an initial state before the issuance of a pop with tag-0. In this initial state VR0 maps to PR8, VR1 to PR7, VR2 to PR6, ... , and VR7 to PR1; and the free list includes pointers to PR9 through PR15, with PR9 at the head and PR15 at the tail of the list This state is stored in the column of entries headed by tag=0.

Consider now, the following representative series of three pops with tap 0, 1, and 2: tag=0: VRO = VRO + VR3 tag=l: VR3 = VR3 + VR5 tag=2: VR4 = VRO + VR3

Since VRO was previously mapped onto PR8, pop(0) cannot be allowed to modify PR8 until it is established that pop(0) will be allowed to complete. Accordingly, the mapping that existed before the start of pop(0) must be modified so that VRO maps onto a physical register in the free list PR9 is at the head of the free list and so VRO is mapped onto PR9. PR8 is put at the tail of the free list since it will not come to the head until eight pops have been issued, whereupon pop(0) is guaranteed to have been retired. Each other item in the free list advances toward the head. Thus, the aαual pop that is issued with tag=0 will be PR9=PR8+PR5.

The next pop, namely pop(l), seeks to modify VR3. In order to allow backing out of this pop, VR3 is mapped onto the physical register that is at the head of the free list, namely PR10.

PR5 is put at the tail of the free list and PRll advances to the head of the free list The aαual pop that is issued with tag=l is PR10=PR5+PR3.

Pop(2) seeks to modify VR4. Accordingly, VR4 is mapped to physical register PRll, and PR(4) is put at the tail of the free list The aαual pop that is issued with tag=2 is PR11=PR9+PR10.

When a pop that modifies a physical register arrives at the functional unit, the physical register's valid bit is cleared (signifying invalid), and is only set (signifying valid) when that pop terminates. This is necessary to ensure that the correα data is present for a later pop that seeks to read the physical register. In the specific example, pop(0) modifies PR9 and Pop(l) modifies PR10. Since pop(2) requires the contents of PR9 and PR10, it must have valid source registers (PR9 and

PR10) before it can execute. This will occur only when pop(0) and pop(l) have terminated. Note that pop(0) and pop(l) don't have to retire, since if either is flushed, pop(2) will also be flushed.

Write Queues in the Data Cache Subsystem Fig. 6 is a block diagram of MCC 25, which provides control for the data cache subsystem.

Its job includes: mating write addresses produced by AP 15 and delivered via PAdrBus 55 with corresponding data produced by any of several chips and delivered via DXBus 58; byte-alignment of write data (which is produced right-justified in 32-bit DWords) with the byte addresses specified by the AP; checking for memory data dependencies between writes and subsequent reads to the same addresses and short-circuiting data as soon as they are available; and maintaining coherence of execution by aging write operations until it is assured that the pops that produced them have been successfully terminated, allowing write operations to be aborted when necessary without modifying main memory or cache, per se. e data cache subsystem deals with three categories of data operations. ormal data accesses are the programmer-specified data accesses, exclusive of those performed by NP 20, if any. The other two categories are system accesses and NP accesses. Data read from memory in each category must refleα writes made by earlier pops of any category, but different categories of writes can be processed asynchronously; that is, it is assumed that nearby writes (in respeα to order of execution) of different categories will not modify the same addresses or that if they do the effeα of asynchrony of writes between categories will be benign.

MCC 25 includes a number of queue structures, including a write reservation queue (WRESQ) 300 with assodated write buffer 302 and multiplexer 303, a system write queue (SYSWQ) 305 with associated system buffer 307, and an NP write queue (NPWQ) 310 with associated NP buffer

312 and multiplexer 313.

WRESQ 300 serves only normal data accesses. It performs all of the functions listed above, including alignment of each write datum, which may be a single byte, a 16-bit Word, or a 32-bit DWord but which always arrives from the execution unit right-justified in a single 32-bit DWord, as direαed by the corresponding address(es) which may specify alignment in memory on arbitrary byte boundaries and checking for memory data dependencies between writes and subsequent reads of any category to the same addresses.

SYSWQ 305 buffers up system writes until the pops that produced them have been successfully terminated and they have been written to memory. It provides for at most four outstanding system writes. System accesses are accesses performed by the AP to access the hidden system struαures: page directory entries, page table entries, segment descriptors, and task state segment data. All system writes occur as single-DWord read-modify-write operations that set Accessed or Busy bits. It is guaranteed that all system accesses will occur in order, since the AP does not perform outoforder execution. Furthermore since system writes result from read-modify-write operations, the address must arrive at MCC before the write data.

NPWQ 310 buffers up to eight NP write address (sufficient to hold the results of at least two NP pops. NP data accesses, those direαed to, and from the NP, differ from normal data accesses in three prindpal ways: single NP pop can read and/or write up to ten bytes of data, whereas a normal pop can access at most four bytes of data; hence the NP may perform multiple DWord transfers to perform a write operation specified by a single pop. Data for NP pops always arrives at the MCC in sequence, Le, it arrives in the same sequence as the address arrive.

Since WRESQ 300 is the most complicated write queue and illustrates the handling of pop terminations and aborts, it will be described in detail. WRESQ consists of a complex data and instruction buffer accommodating eight entries. Each entry includes a 30-bit wide content-addressable memory (CAM) register for DWord addresses (where a DWord is 32 bits of data), a special-purpose four-bit Tag CAM which includes numeric comparison logic and a Last bit and a Released bit, and a four byte-wide data register with associated control logic including Valid bits for each data byte and a Present bit for the entire data register. The WRESQ receives memory addresses for data accesses from a FIFO buffer called the Physical Address Bus Queue (PAdrQ) 320, where they are buffered as they arrive from the AP. Each such address is accompanied by the type of access to be performed (read, write, or read-modify-write), the tag of the pop that produced it, a four-bit byte-enable mask indicating the bytes of the DWord to be transferred to and/or from the addressed DWord, and a Last bit that indicates whether the address is the last to be produced by its pop.

Each address received from the PAdrQ for a write or read-modify-write access is assodatively compared to all addresses previously entered into the WRESQ that have Valid bits set in any of the byte positions indicated by the byte-enable bits accompanying the address. If any is found, indicating that an overlapping write is already present in the WRESQ, the processing of new addresses into WRESQ must be suspended until the overlapping write has been written to memory and removed from WRESQ.

In this case, the MCC must suspend accepting more addresses for any write queue until the location has been written to memory. This is referred to as a pipeline stall, in which case the MCC allows addresses to back up in the PAdrQ and if this structure threatens to overflow the MCC locks the PAdrBus, preventing the AP from issuing more addresses. Otherwise, if no pipeline stall is required or after any such stall has been resolved by removing the overlapping entry, the new address is assigned a location in the WRESQ.

Locations in WRESQ 310 are selected for assignment by an assignment counter in round- robin fashion. If the seleαed location is free the address is copied into the Address CAM, the tag and the Last bit are copied into the Tag CAM, the four Present bits and the Released bit are set to zero, and the four Valid bits are set corresponding to the byte-enable bits specifying the bytes of the DWord that are to be written. If, on the other hand, the WRESQ location is still in use when it comes up for re-assignment, as is indicated by one or more Valid bits being set in the location, the MCC must suspend accepting more addresses (stall the pipeline) until the location has been written to memory.

At or after the clock period in which a new entry is written into the WRESQ, data is written into the data bytes for which Valid bits are set There is no guarantee that the AP will transmit the address before the executing unit provides the data to be written, nor is there any guarantee that MCC itself can process addresses as fast as they arrive Therefore, the data may already have been sent to MCC before the WRESQ entry for it has been established. Eight-entry WBuf 302 accommodates this. The WBuf is located between the DXBus (the bus on which write data is delivered to MCC) and the input to WRESQ itself. Data arriving on DXBus is identified by the type of operation it represents (normal memory write if destined to the WRESQ) and the tag of the pop that produced it

As normal memory write data arrives on DXBus it is stored in the 32-bit WBuf entry addressed by the least-significant three bits of its 4-bit pop Tag, the most-significant bit of the pop Tag is stored with the entry, and (unless a Tag CAM hit occurs as described below) a Present bit is set for the entry. Simultaneously, its tag is also looked up in the Tag CAM of WRESQ. If a location (or two adjacent locations) for the data is found in WRESQ, including One location having its Last bit set, the data is immediately written into that location (or locations) and in this case the

WBuf entry's Present bit is not set Similarly, as an address having its Last bit set is entered into

WRESQ, the WBuf entry corresponding to the tag of the pop that produced the address is interrogated and if its Present bit is set the data is copied out of the WBuf entry, the WRESQ

Present bit is set, and the WBuf Present bit is cleared.

By the above two mechanisms, regardless of whether the data or address arrives first or they arrive simultaneously, when both the data and address are present the address and data are both entered into the WRESQ, the Present bit of the WBuf entry for the pop is cleared, and the Present bit(s) of the WRESQ entry(ies) are set. At this time, the WBuf location is free for re-use. Since the data may arrive outoforder with respect to addresses, in order to allow processing to occur as fast as possible two independent paths into data registers and Present bits of WRESQ are provided. One, sourced from the WBuf, can write into the location to which the associated address is simultaneously being written (as selected by the round-robin counter). The other, directly from the DXBus interface can write into the location(s) identified by the Tag CAM. This allows a newly arrived address to be paired up with data from WBuf and written into a new entry in the same clock cycle that a newly arrived datum from the DXBus is written into a previously established WRESQ entry.

Data that is entered into WRESQ passes through a rotator which byte-aligns it into the same byte positions it will occupy in memory. A separate rotator is provided for each of the two data paths into WRESQ. The number of contiguous Valid bits having a value of zero, counting from the least-significant byte position of the (first) WRESQ entry (of, possibly, two adjacent entries), indicates the number of byte positions to the left that the data must be rotated for alignment before the data write occurs into WRESQ. Logic assodated with the Valid bits provides this data to barrel-shifting logic by gating out the Valid bits of a location if and only if the preceding WRESQ location does not also contain an address for the same pop tag.

Whenever data is written into a location in the WRESQ it is also written intd any adjacent location having the same tag value (if addressed by the Tag CAM) or adjacent in the direction of earlier entry assignment and having its Last bit negated (if addressed by the new entry assignment counter). Thus, since the data being written is at most four bytes wide, byte-wise rotating the data to match the byte positions for one DWord and then writing both DWords writes all four bytes into the appropriate positions in both DWords simultaneously for a non-aligned write operation that straddles a DWord boundary in memory.

Whenever a normal-category address that has its Last bit asserted is extracted from the

PArdQ the MCC asserts an MCC Termination signal to the DEC Since addresses are processed in- order (Le, in the same order as the pops that generated them issued from DEC) and DEC is aware of which pops will generate a normal memory access, DEC can unambiguously assodate an MCC termination with a given pop even though the termination does not explidtly contain the tag of the pop for which the address(es) has been processed. The termination from MCC allows DEC to insure that no more than eight WBuf locations are needed in the worst case to accommodate the data from all pops for which WRESQ entries have not yet been established, and that irrelevant data and addresses can be properly flushed from queues in case of an abort DEC insures this because it does not issue more than seven pops beyond the oldest that produces a normal access and has not yet been terminated by MCC As addresses are extracted from the PAdrQ, each is assodatively compared to all addresses previously entered into WRESQ (and also the other two write queues), in the manner described above for write addresses. As previously described, any overlap of an incoming write address with an existing WRESQ entry results in a pipeline stall until the earlier entry has been written to memory and removed from the write queue. However, nonoverlapping writes, even if modifying (different parts of) the same DWord, may be entered into the queues. Addresses for read- and read-modify- write operations (read addresses) are also assodatively compared to write queue entries. As with writes, this comparison is performed on a byte-by-byte basis, as determined by the conjunαion of the read address' byte-enable bits and the corresponding Valid bits of the queue entries.

If no WRESQ entry addresses a byte spedfied by the read address, or if each entry that addresses a byte spedfied by the read address (a write-queue hit) has its Present bit asserted, then the

MCC signals DCI 37 to perform a normal cache look-up for the address. (Any cache access may result in a delay in case of a cache miss, necessitating a main memory operation to retrieve the requested data.)

If, on the other hand, the read address hits in one or more write-queue entries that do not have their Present bits asserted, then processing of addresses from PAdrQ must be suspended (the pipeline stalled) until data has been received for all such entries. Once any such stall has been resolved and cache data is available, the MCC directs the DCI to gate out onto DIOBus 57 only those bytes for which no write queue hit has its Valid bit asserted. The other bytes, seleαed by the Valid bits of all write-queue entries that hit the address, are driven out of the write queue and onto the DIOBus by the MCC Thus, write data that has not yet been posted to memory can be "short- drcuited" to later reads. Since the pipeline is stalled whenever a second write is received for a byte for which a write already is pending in a write queue, there can be no more than one entry that addresses a given byte of data; however, there may be several entries that supply different bytes of the same DWord read. The write queues merge the Valid bytes from all such entries to seleα data to drive out onto the DIOBus.

Like other units of the CPU, the MCC must track the tag status provided to it by DEC via the tag status bus. Each clock cycle, DEC transmits one of two message types on the tag status bus, either an advisory of the oldest outstanding pop tag (OOTag) or an abort tag (ATag). The WRESQ maintains a pointer to its oldest entry called the Oldest Entry Pointer (OEP). An entry remains ineligible to be written to memory until it is becomes older than the OOTag. Each cycle in which an

OOTag is received, the OOTag is compared to the tag CAM contents of each write queue entry having one or more Valid bits set that does not already have its Released bit set Tag comparison is performed by subtracting the four-bit OOTag from the entry's four-bit Tag using four-bit two's- complement arithmetic Tap are issued in binary counting sequence (0000, 0001, 0010, ... 1110, 1111, 0000, ...) and no more than seven tap are outstanding at any time, so that the value of OOTag can jump by at most eight from one cycle to the next (if all seven outstanding pops are retired and a new pop is issued in the same cycle). Therefore, if the value of the most significant bit of the difference formed by subtraαing OOTag from an entry's tag is "1" it indicates that the entry's tag, is between one and eight pops older than the OOTag, since it cannot be eight or more younger than the OOTag.

For each entry that is thus found to be younger than the OOTag, the entry's Released bit is set. The entry can be written to cache and/or main memory when and only when the entry pointed to by the OEP has its Released bit set, its Present bit set, and one or more Valid bits set. When the write occurs, the entry's Valid bits are cleared and the OEP is advanced to the next sequentia e^try that has one or more Valid bits set, if any exist

When the DEC signals an abort, the ATag is checked against the pop tag fields in all queues, including the PAdrQ, the WRESQ, and the other two write queues. The check is performed in the same manner as the check to determine when an entry can be released, Le. by subtracting the provided ATag from the tag field spedfied in the queue. If the tag field of the queue entry is strictly greater than (older than) the ATag, the entry remains in the queue, and otherwise its Valid bit(s) are cleared. Depending on the control logic implementation of the queue, pointers may also have to be adjusted. For the WRESQ, if entries are deleted the assignment pointer is moved back to the earhest deleted entry and, if this would move it past the OEP, the OEP is moved to the entry preceding the assignment pointer. A similar check is made for the entries of the WBuf associated with the WRESQ and similar structures elsewhere that are addressed by tag value, but since the address of the entry in WBuf is simply the lower three bits of its tag, only the most significant bit (MSB) of the entry's tag is stored in the entry itself; it suffices to reset the Valid bits of all entries that have 3-bit addresses equal to or greater than the lower three bits of ATag and which have a stored MSB equal to that of the ATag, or which have addresses less than the three least significant bits of ATag and have MSBs opposite to that of the ATag.

As for all functional units of the CPU, the MCC disregards data present on internal busses during an abort cycle and re-transmits any data it was sending that is still appropriate after the abort. Thus, in a single cycle, the MCC (and the rest of the CPU) resets itself to the state it would have been in had the pops bearing tap greater than or equal to the ATag never been issued.

Pseudo-Op Handling In the IEU

Fig. 7 is a block diagram of IEU 17. The IEU implements two data paths, a single-cycle data path 400 and a multi-cycle data path 405. The single-cycle data path executes all integer instructions that can be completed in one cycle, such as addition, subtraction, and shift. The multi¬ cycle data path executes all integer pops that require multiple cycles, such as multiplication, division, and ASCII and dedmal arithmetic The two data paths utilize a common register file 410, which contains the physical registers into which the virtual registers are mapped, as discussed above in connection with register reassignment. Each of the data paths includes elements coupled to a common set of buses 412, with a bus coupler 415 providing isolation between the two data paths. The single-cycle data path includes a general purpose ALU 420, a barrel shifter 422, and spedal logic 425 for sign propagation, leading zero and one detection, and the like. The multi-cycle data path includes multiply/divide circuitry 430 (8x32 multiplier array) and circuitry 435 for ASCII and decimal adjust

Input pops are received from pop bus 52, and direαed to a pop queue 450. A multiplexer 452 selects which pop in the queue to execute, and the pop to be executed is communicated to single-cycle control logic 455 (implemented as PLA's). For a single-cycle pop, control logic 455 controls the single-cycle data path elements. For a multi-cycle pop, it controls the multi-cycle elements for the first cycle of the pop and provides an address to a microcode ROM 460, which along with multi-cycle control logic 462 (PLA's) provides control for subsequent cycles of the p- op.

In the case of ALU pops, where the result is stored in a register, a termination is immediately entered into a termination queue 470 whose contents are put out on the IEU termination bus. With respeα to a memory write, the result either goes directly to the DXBus, in which case a termination is entered into the termination queue, or the output is placed in a DXBus output queue 475 for subsequent output. Once the bus is available, the termination is entered into the termination queue.

Pop queue 450 is eight (8) deep. The pop queue has multiple read ports and a single write port. Queue control logic 480 controls the queue to funαion normally like a FIFO (first in first out) but it also supports out of order reads. The queue control logic also indicates if the queue has entries or doesn't have an entry. The queue control logic also identifies the position of the pop in the queue.

If the pop queue receives a pop when the queue is empty, then the pop is immediately decoded and appropriate control signals are generated. During the instance when the decoding of the pop is in progress, ready to execute checks are made. The checks involve data operands and flag operand dependency and some spedal execution criteria, such as inorder execution and functional unit serialization. If the pop fails the ready to execute checks then some or all the control signals are disabled. If the pop is not executed then the pop is placed in the queue. If there are entries in the queue then the queue funαions like a FIFO. The pop at the head of the queue and the next younger pop in the queue are read. Ready-to-execute logic 482 checks for both the pops are made The ready-to-execute check for the pop at the head of the queue includes data operand dependendes. If the head of the queue passes the ready to execute checks then the pop is decoded and executed. If the pop cannot be executed then it is re-issued for checks in the next cycle of operation.

The ready-to-execute logic checks for the next younger pop in the queue includes data operands and flag dependendes, interlock with respeα to the pop at the head of the queue, and whether the pop is subjeα to a spedal execution criterion (such as inorder execution). For example, it checks that the valid bit is set in any source registers required by the pop. If the pop at the head of the queue fails to execute then the next younger pop in the queue will be decoded and executed if it passes through all the ready to execute checks. If both the head of the queue and the next younger pop in the queue can be successfully executed then the head of the queue is executed.

Multiple read pointers and a write pointer are kept to track the queue operation. If the next younger pop is executed then the corresponding read pointer is updated to point to the next entry in the queue. If the pop at the head of the queue is executed then the first read pointer gets the value of second read pointer and second read pointer is updated to point to the next entry in the queue. The write pointer is used for pointing to the first empty location in the queue. During an abort cycle all the pointers are compared with the abort tag and set to appropriate values based on the result

Queue control logic 480 has a status bit for each entry in the queue. The status bit is set to "valid" while loading a new pop in the queue. After the pop is successfully executed the status bit is set to "invalid". If the entries in the pop queue are to be flushed during abort cycles then the appropriate status bits are set to "invalid". The pop identified for execution is decoded. If the identified pop for execution is a single-cycle pop then the control signals for single-cycle data path

400 (register file, ALU, barrel shifter, and spedal logic) will be generated by control logic 455. The single-cycle pop is executed in a single clock cycle. Multi-cycle data path 405 doesn't perform any function during this time.

If the pop identified for execution is a multi-cycle pop then the first state control signals are generated by the single-cycle control logic The single-cycle control logic also activates microcode

ROM 460 . The control signals for the remaining states are generated from the microcode ROM and multi-cycle control logic 462. Multi-cycle data path 405 performs the operation during this time. The multi-cycle operation will use only register file 410 from the single cycle data path.

It is possible to perform concurrent (parallel) execution of pops. If the identified pop for execution is a multi-cycle pop then possible performance advantage is gained by executing the subsequent single cycle pop from the queue. It is then possible to execute single cycle pops using the single-cycle data path and multi-cycle pops using the multi-cycle data path. The multi-cycle control unit controls the concurrent execution of pops. The single cycle pop will not be executed if there is data or status flag dependency with respeα to multi-cycle pop. The single cycle pop will also not be executed during the time there is a resource confliα between a multi-cycle pop and the single-cycle pop (during writes to register files and status flag updates).

The multi-cycle control logic has a state machine which will identify the state of operation. The integer execution unit can be in one of four states: single-cycle, multi-cycle, concurrent, or idle The buses between the single-, and multi-cycle data paths are disconnected by bus coupler 415 during the concurrent operation. The buses are normally conneαed during the multi-cycle operation to allow data transfer from the register file and/or to use the result from an pop for the next pop.

After the pop is executed the result is stored into the register file or memory write operand queue (DXBus output queue 475). The flap are updated whereupon the pop is terminated. If a pop is identified to be executable then it is presented to the single-cycle and/or multi-cycle control logic If the funαional unit is found to be busy then the pop is not executed. This is signaled back to the pop queue control and ready to execute logic Appropriate adjustments to the multiple read pointers is made. The pop queue queue control logic, and ready to-execute logic will normally try to keep issuing pops based on resolving data operand interlocks and special execution criteria. The control logic of the various funαional units within the IEU (ALU, barrel shifter, special logic, multiply/divide circuitry) will resolve the hardware resource confliα and either perform a single-cycle, multi-cycle, or concurrent operation. If the issued p-op cannot be executed due to resource confliα signalled by a signal called QNEXT then it is requested to be re-issued by the pop queue control logic The flap are tracked using a flag stack 485.

Conclusion

While the above is a complete description of the preferred embodiment of the invention, various modifications, alternatives, and equivalents may be used. For example, while the embodiment described above is implemented with a separate chip for each funαional unit the basic architeαure with its distributed pipeline control would be equally effeαive and advantageous in a single-chip embodiment Similarly, while the spedfic embodiment executes a particular instruction set, other embodiments could be designed to execute other instruction sets. Additionally, while a particular mechanism for communicating tap to the funαional units

(tag status bus with OOTag or ATag using encoded tap) is described, there are other possibilities. One possibility, in a system where at most n pops can be outstanding at a given time, is to represent a tag as a single set bit in an N-bit veαor where N is equal to or greater than n. Such Tap are issued sequentially such that the colleαion of outstanding pops is represented by a contiguous (in a cyclical sense) group of set bits in an N-bit veαor. This veαor is communicated to the funαional units to signify status, while a similar type of veαor is communicated to signal aborts.

Therefore, the above description and illustrations should not be taken as limiting the scope of the invention which is defined by the appended claims.

Φaτ.τ,-R i - Pseudo-Ot? Bus Format

On first 1 On first Φ2

Bitfs Field Bit(sϊ Field

<51..48> SegReg <51..48> DestSegReg <47..45> <47> LastPop

<44..41> SrcAReg <46> (reserved)

<40..37> IndexReg <45> Lock

<36..33> EASpec <44..40> StatMod

<32> ASize <39..32> Imm8

<31> TwoCyc <31..16> ImmDispHi

<30..29> MemRef <15..0> ImmDispLo

<28..25> SrcBReg

<24..21> DestReg

<20> RegStore <19..17> OperSize <16..14> OperSpec <13..4> Opcode <3..0> PopTag

On second ώl On second ώ2

Bitfs) Field Bit(s) Field

<47..14> (undefined) <47..32> (undefined)

<13..4> Opcode <31..16> ImmHi

<3..0> (undefined) <15..0> ImmLo TABLE 2 - Physical Address Bus Format

On first ώl On first ό2

Bit(s) Field Bit(s) Field

<25> DTAGReq <25..23> Stream

<24> ITAGReq <22..20> Operation

<25> DecReq (3..0> InstrNu (=P-op Tag except for

<22> MCCHLd Stream 0)

<21> ARReq

On second όl On second ώ2

Bit(s) Field Bit(s) Field

<20> Lo <19> Val

<19> Trm <18..4> Physical Address <31..17>

<18..4> Physical Address <16. ,2>

<3..0> Byte Select

TABLE 3 - DIOBus Format

DIQCtl

On ώl On ώ2 Bit(s) Field Bit(s) Field <4> Last Operand <4> RdData Valid <3..0> Frame <3..0> P-op Tag

DIOBus

On ώl On 2

Bit(s) Field Bit(s) Field

<31..0> WrData <31. .0> <31..0> RdData <31. •0>

TABLE 4 - Data Exchange Bus Format

Cycle 1 ώ2 Bits Field <21> APReq <20> NPHLd <19> NPReq

Cycle 2 ώl

Bit(s. Field

<21..20> TT (transfer type)

<19..16> P-op Tag

<15..0> Data <15..0>

Cycle 2 ώ2 Bit(s) Field <18..16> MemOp <15..0> Data <31..16>

TΆT-T.T: 5 - IEU Termination Bus Format

On Φ2

Bit(sϊ Field

<4..2> Pseudo-Op Tag

<1..0> Termination Id

Pseudo-Op Tag Contains the 3 lsb's of the p-op tag of the p-op being terminated.

Termination Id Value Meaning

00 No Termination

01 Normal Termination

10 Mispredicted Branch Direction Termination

11 Abnormal Termination

TART/R 6 - AP Termination Bus Format

On ό2

Bit (s ι Field

<3> Termination Id, bit <7> <2> Id <6> <1> Control Bit B / Id <5>

<0> Control Bit D / Id <4>

On ώl (usually) Bitfsϊ Field

<3> Control Bit I / Id <3>

<2> Control Bit N / Id <2> <1> Control Bit H / Id <1>

<0> Control Bit S / Id <0>

Termination Id <7..0>

Value Meaning

OOXX XXXX No termination

01BD INHS Control bit update

10BD INHS Mispredicted Address/Control Bit update

110X XXXX Normal Termination

1110 0001 Debug

1111 0010 Hypercode

1111 0100 General Protection (Instruction Sensitivities

1111 0101 Debug (Breakpoint)

1111 0110 Invalid Opcode

1111 0111 387 Not Available

1111 1000 Double Fault

1111 1001 Shutdown

1111 1010 Invalid TSS

1111 1011 Segment Not Present

1111 1100 Stack Fault

1111 1101 General Protection (except instruction)

1111 1110 Page Fault TABLE 7

Exemplary Sequence Illustrating Pseudo-Op

Termination and Tracking

AP Term IEU Term

Tag Pseudo-Op Tag Value Tag Value

CHK AG

4 XFE

AG 5 XFE

DEC AG OK

B-

7 XFE OK

AG OK

8 XFE

9 DEC OK

5 OK 4 OK 5 OK

6 OK OK

7 OK

8 Page Fault

OK

Claims

WHAT IS CLAIMED IS:

1. A computer processor comprising: means for issuing a series of operations, each operation upon being issued achieving the status of an outstanding operation; a plurality of funαional units, each capable of executing at least some of the outstanding operations; means for assigning each outstanding operation a tag, said tag being a member of an ordered set of tap such that the relative age of two outstanding operations may be determined by inspeαion of their tap; means for determining when any given outstanding operation is complete; and means for limiting the number of outstanding operations so as to insure uniqueness of outstanding tap.

2. The computer processor of claim 1, wherein: said means for limiting allows at most n operations to be outstanding at any time; and tap are issued sequentially over a range greater than or equal to 2n; whereupon the relative age of two outstanding operations may be determined by signed comparison of their tap.

3. The computer processor of claim 1, wherein: at most n operations are outstanding at any time, and tap are represented as an N-bit veαor (where N is equal to or greater than n) in which at most one bit is set; and tap are issued such that the set of outstanding operations is represented by a contiguous group of bits in the N-bit veαor.

4. The computer processor of claim 3, and further comprising means, responsive to an abnormal condition and a determination that a set of outstanding operations is to be flushed, for communicating to said functional units an N-bit veαor representing that the set of outstanding operations is to be flushed.

5. The computer processor of claim 4 wherein said N-bit vector representing that the set is to be flushed has those bits set that correspond to the set of operations to be flushed.

6. The computer processor of claim 3, and further comprising means, responsive to the normal completion of at least the oldest outstanding operation and a determination that a set of outstanding operations is to be retired, for communicating to said funαional units an N-bit veαor representing that the set of outstanding operations is to be retired.

7. The computer processor of claim 6 wherein said N-bit vector representing that the set is to be retired has those bits set that correspond to the set of operations to be retired.

8. The computer processor of claim 1, wherein said functional units are embodied in a plurality of semiconductor chips.

9. The computer processor of claim 1, and further comprising: means, responsive to an abnormal condition, for flushing all outstanding operations having tags issued later than a given tag.

10. The computer processor of claim 9, and further comprising: means for grouping adjacent operations such that flushing of any operation in the group will cause flushing of all operations in the group.

11. The computer processor of claim 1 wherein at least some of said operations are branch operations, and further comprising: means for prediαing the outcome of outstanding branch operations; means for detecting incorrect predictions on outstanding branch operations; and means for flushing all outstanding operations which were issued as a result of incorrectly prediαed branch operations.

12. The computer processor of claim 1, and further comprising: means for determining the oldest outstanding operation; and means for signaling successful retirement of operations to at least some of said functional units by providing a tag which marks the boundary between outstanding and retired operations.

13. The computer processor of claim 12, and further comprising: means for grouping adjacent operations such that retirement of any operation in the group will be performed only when all operations in the group may be retired.

14. The computer processor of claim 12, and further comprising: means for buffering memory writes for at least the period of time during which their originating operations are outstanding but not retired; means for flushing buffered writes when their originating operation is flushed; and means for completing buffered writes to cache or memory when their originating operation is retired.

15. The computer processor of claim 14, and further comprising: means for returning buffered write data to subsequent read operations before the write data is flushed or placed in cache or memory.

16. The computer processor of claim 1 wherein said means for issuing is responsive to input instruαions having an instruαion set architeαure that includes m programmer-visible registers and at least some operations modify one of the registers, and further comprising: means for limiting the number of outstanding register-modifying operations to n; at least (m+n) physical registers; and means for mapping the programmer-visible registers to the physical registers.

17. The computer processor of claim 16, and further comprising: means for insuring that physical registers are not reused until after the operation which modified them has been successfully retired; and means for restoring the virtual to physical mapping to a previous state when an abnormal condition is detected, thus restoring the contents of the programmer visible registers.

18. The computer processor of claim 17 wherein: register modifications are permitted to occur out of the programmer spedfied order.

19. The computer processor of claim 17, and further comprising: a valid bit assodated with each physical register; means for examining the valid bits of all physical registers required as inputs to an operation; a means for holding up execution of operations which require at least one physical register whose valid bit is clear.

20. The computer processor of claim 1 wherein: when an interlock is required, only the particular funαional unit directly affected holds up execution of the interlocked operations.

21. The computer processor of claim 1, wherein: some or all funαional units signal terminations upon completing some or all operations; said terminations provide suffident information to determine the tag of the completed operation; and said terminations provide suffident information to determine the highest priority abnormal condition (if any) deteαed by the funαional unit while processing the operation.

22. The computer processor of claim 21, and further comprising: means for prioritizing all terminations signaled by funαional units for each outstanding operation; means for selecting the oldest abnormally terminated operation; means for determining the correα response to the highest priority termination on the oldest abnormally terminated operation.

23. The computer processor of claim 21 wherein: terminations from functional units may be signaled in a different order than the order in which the operations were issued.

24. A computer processor providing enhanced interlock avoidance and performance by providing: a plurality of write buffer queues, each queue being assigned to handle writes of a particular type; means for selecting the highest priority write for each write queue; and means for selecting the highest priority queue.

25. The computer processor of claim 24 wherein said writes are allowed to occur out of order.

26. A computer processor comprising: means, responsive to an input stream containing instructions, for converting instructions in said input stream to a series of operations; a plurality of functional units, each capable of executing at least some of said operations; means for communicating each of said operations to at least some of said functional units, an operation so communicated being designated an outstanding operation; means for assigning a tag to each outstanding operation, said tap being assigned in a sequential manner, means for maintaining, for each outstanding operation, information regarding termination of that operation by said functional units; means, assodated with each functional unit, for determining with respeα to each operation communicated to it when it has terminated it and whether the termination was normal, and for communicating such termination information to said maintaining means along with the tag of the operation; means for determining the oldest outstanding operation; means for communicating a representation of the oldest outstanding operation to said functional units; means, responsive to the termination information regarding at least the oldest outstanding operation, for allowing that operation to be retired only if the termination information for that operation indicates that all funαional units terminated that operation normally, and means, responsive to the retirement of at least the oldest outstanding operation, for updating said representation of the oldest outstanding operation to reflect that the operation so retired is no longer outstanding.

27. The computer processor of claim 26, and further comprising: means, responsive to information that a given outstanding operation terminated abnormally, for communicating an abort tag to said functional units, specifying a group of operations to be flushed; means, assodated with each functional unit, for flushing all outstanding operations specified by said abort tag; means for deleting the designations of outstanding operations for those operations specified by said abort tag; and means for causing said tag assigning means to commence assigning further tags starting at a value equal to the tag of the oldest operation flushed.

28. The computer processor of claim 27 wherein said abort tag is equal to the tag of the oldest operation that is to be flushed.

29. A computer processor comprising: means, responsive to an input stream containing instruαions, for converting instruαions in said input stream to a series of operations; a plurality of functional units, each capable of executing at least some of said operations; means for communicating each of said operations to at least some of said funαional units, an operation so communicated being designated an outstanding operation; means for limiting the number of outstanding operations to a predefined maximum; means for assigning a tag to each outstanding operation, said tap being assigned in a sequential manner, means for maintaining, for each outstanding operation, information regarding termination of that operation by said functional units; means, associated with each funαional unit, for determining with respeα to each operation communicated to it when it has terminated it and whether the termination was normal, and for communicating such termination information to said maintaining means along with the tag of the operation; means for communicating a representation of outstanding operations to said funαional units; means, responsive to termination information from said funαional units, for retiring normally terminated operations in order; means, responsive to information that a given outstanding operation terminated abnormally, for instructing said functional units to flush at least the given outstanding operation and all later outstanding operations; means, associated with said funαional units, for flushing all outstanding operations specified by said instructing means; and means for causing said tag assigning means to commence assigning further tap beginning with the tag that was assodated with the earliest outstanding operation that was flushed.

30. The computer processor of claim 29 wherein said representation of outstanding tap is the tag of the oldest outstanding operation.

31. A method of controlling pipelined operations in a computer processor which includes a plurality of functional units, each capable of executing at least some of the outstanding operations, comprising the steps of: assigning each outstanding operation a tag, said tag being a member of an oτdered set of tap such that the relative age of two outstanding operations may be determined by inspection of their tap; determining when any given outstanding operation is complete; and limiting the number of outstanding operations so as to insure uniqueness of outstanding tap.

32. The method of claim 31, wherein: said limiting step allows at most n operations to be outstanding at any time; and tap are issued sequentially over a range greater than or equal to 2n; whereupon the relative age of two outstanding operations may be determined by signed comparison of their tap.

33. The method of claim 31, and further comprising: the steps, performed by said functional units, of signifying any abnormal condition; and the step of flushing all outstanding operations having tap issued later than a given tag.

34. The method of claim 33 and further comprising the step of grouping adjacent operations such that flushing of any operation in the group will cause flushing of all operations in the group.

35. The method of claim 31 wherein at least some of the operations are branch operations, and further comprising the steps of: predicting the outcome of outstanding branch operations; deteαing incorrect predictions on outstanding branch operations; and flushing all outstanding operations which were issued as a result of incorrectly prediαed branch operations.

36. The method of claim 31, and further comprising the steps of: determining the oldest outstanding operation; and means for signaling successful retirement of operations to at least some of said funαional units by providing a tag which marks the boundary between outstanding and retired operations.

37. The method of claim 36, and further comprising the step of grouping adjacent operations such that retirement of any operation in the group will be performed only when all operations in the group may be retired.

38. The method of claim 36, and further comprising the steps of: buffering memory writes for at least the period of time during which their originating operations are outstanding but not retired; flushing buffered writes when their originating operation is flushed; and completing buffered writes to cache or memory when their originating operation is retired.

39. The method of claim 38, and further comprising the step of returning buffered write data to subsequent read operations before the write data is flushed or placed in cache or memory.

40. The method of claim 31 wherein said issuing step is responsive to input instruαions having an instruction set architeαure that includes m programmer-visible registers and at least some operations modify one of the registers, and further comprising the steps of: limiting the number of outstanding register-modifying operations to n; providing at least (m+n) physical registers; and mapping the programmer-visible registers to the physical registers.

41. The method of claim 40, and further comprising the steps of: insuring that physical registers are not reused until after the operation which modified them has been successfully retired; and restoring the virtual to physical mapping to a previous state when an abnormal condition is deteαed, thus restoring the contents of the programmer visible registers.