WO1990006633A1 - Modules de donnees hf microcommandes - Google Patents

Modules de donnees hf microcommandes Download PDF

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Publication number
WO1990006633A1
WO1990006633A1 PCT/US1989/005579 US8905579W WO9006633A1 WO 1990006633 A1 WO1990006633 A1 WO 1990006633A1 US 8905579 W US8905579 W US 8905579W WO 9006633 A1 WO9006633 A1 WO 9006633A1
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WO
WIPO (PCT)
Prior art keywords
data
frequency
module
memory
chip
Prior art date
Application number
PCT/US1989/005579
Other languages
English (en)
Inventor
Robert D. Lee
Donald R. Dias
Robert W. Mounger
Michael L. Bolan
John Patrick Heptig
Hal Kurkowski
Kevin M. Klughart
Original Assignee
Dallas Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/282,410 external-priority patent/US4897662A/en
Priority claimed from US07/283,426 external-priority patent/US4989261A/en
Priority claimed from US07/282,819 external-priority patent/US4955038A/en
Priority claimed from US07/282,008 external-priority patent/US4984291A/en
Priority claimed from US07/283,554 external-priority patent/US4967108A/en
Priority claimed from US07/282,406 external-priority patent/US5025486A/en
Application filed by Dallas Semiconductor Corporation filed Critical Dallas Semiconductor Corporation
Publication of WO1990006633A1 publication Critical patent/WO1990006633A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0212—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is master and terminal is slave
    • H04W52/0216—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is master and terminal is slave using a pre-established activity schedule, e.g. traffic indication frame
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H04W52/0229—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where the received signal is a wanted signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to wireless data interface systems, and to portable data modules for use within such a system, and to power- efficient integrated circuits.
  • Systems which can provide short-range wireless data communication between a base station and a portable low-power module have recently been the subject of development efforts by a number of groups. Such systems can be extremely useful in many contexts, such as control of personnel access to secure facilities, medical monitoring of inpatients, automated livestock management, automated manufacturing generally, inventory control, theft control, and others described below.
  • rechargeable batteries are not suitable for a power supply.
  • Rechargeable batteries not only impose a user burden (to perform recharging), but also tend to have electrical characteristics which may be dependent on the discharge/recharge history of the particular battery.
  • Many possible applications cannot tolerate such uncertainty, and require a degree of reliability which demands a very conservative approach to power supply design and rating.
  • Greater noise immunity can be achieved by using high transmitter power, by by using large, highly directional, and/or highly resonant antennas (which provide "antenna gain”), or by using narrow-bandwidth filtering (or more sophisticated signal processing operations) in the receiver (which provide "processing gain").
  • processing gain is most easily achieved by precise knowledge of the characteristics of the expected signal, and/or by extensive computing operations on the recovered signal. Precise knowledge of signal characteristics tends to require precise knowledge of time and/or frequency, and mainta ⁇ ing this knowledge also consumes power.
  • adding processing gain into a portable data module not only increases the capital cost, but also places an additional burden on the power budget.
  • successive engineering improvements can provide some increase in noise immunity, the room for improvement is inherently limited.
  • sensitivity must not be too low, and the immunity to electrical noise must be good, and the power consumption must be very low.
  • Such systems may sometimes need to operate in high-noise environments, and such environments may completely block the communications channels.
  • noise sources may sometimes provide an RF power level, at the receiver, within the reception band, which is comparable to the power level provided by the transmitter.
  • extremely high broad-band noise levels may be generated by arc welding (or arc furnaces), by plasma deposition processes, by large motors, or by digitally controlled actuators.
  • the size and weight of the portable module is an extremely sensitive issue.
  • a module which is merely transportable will not suffice.
  • pagers and portable radios have often had weights of 10 ounces or more, and volumes of 10 cubic inches or more. If modules of this size were used (for example) for patient identification in a hospitals, the patients would unload such cumbersome objects as quickly as possible, by any means possible.
  • such large modules could not be used for inventory control, since there would be no convenient place to put them, and they would easily be damaged (or personnel would learn to bypass them).
  • the portable module cannot afford the power to continually broadcast a beacon, but, even if the base station module broadcasts a beacon to ascertain the possible presence of receiver modules, the power requirements of listening for such a beacon are large.
  • a portable data module with non- rechargeable batteries, is desired to have a lifetime of at least 10 years, and to be able to perform at least 1,000,000 data transactions during its lifetime. (This is an extremely aggressive set of specifications, and is believed to be far beyond the capabilities of any system presently available.)
  • the available battery energy is 2000 Joules (1 milliAmpere for 190 hours at 3 Volts). Then the power dissipation in the standby mode must be no more than several millionths of a Watt, or all of the battery energy will be dissipated merely in waiting for the active communication transactions to begin, before the design lifetime has expired.
  • the present application discloses several novel teachings which are directed to this aspect of power conservation.
  • the power efficiency requirements of battery-powered modules can be extremely stringent. For best reliability, neither battery recharging nor user detection of imminent failure should be relied on. Therefore, to reliably meet the design battery lifetime of a module, extreme care must be taken to identify and control the worst-case battery-drain scenarios. Battery lifetime management can be particularly difficult where several complex integrated circuits are included in a battery-powered module. Where significant control interactions, or even data exchange, may occur, the demands of such transactions must also be allowed for.
  • Some previously proposed methods for implementing such wireless- access data systems have used passive components for RF detection, connected so that the RF power received from the base station can actually provide the necessary power to operate the remote module. Such systems require that the RF power level at the receiver must be far higher than would be needed merely for communication.
  • a systems which provides a wireless data-transfer interface to portable data modules has the potential for great flexibility.
  • the communications protocols often assign the base station to be the master station.
  • each base station (unless passwording prevents this) can query, read, and write data to any portable module which may happen to be in range, without any independent action at the remote module.
  • a large system of this kind presents issues of access collision. If a large number of modules are within a base station's range, the base station may receive responses from many portable modules when it broadcasts a query signal. Each module has a "name" by which it can be addressed separately, but the use of module identifiers does not remove all problems: if a large number of modules may be present in the total system, the time for a base station to query the possible module identifiers may be large. Modern semiconductor technology has provided solid-state memories with such low standby power requirements that a single coin-sized battery can power the memory for ten years of lifetime or more. Such memories are already commercially available.
  • Error-check-and-correct protocols are commonly used to preserve data integrity. However, in a wireless data communication system, which inherently has a high exposure to noise, one important class of error must be carefully avoided: if a write were to be directed to the wrong location in the module's memory, data integrity would be lost, even though the error checkbits for the data stream all indicated that no error had occurred.
  • multiport memories are a very useful basic tool.
  • a "multiport" memory is one in which different computer processes can independently access a common memory space, through hardware channels which are at least partly separate.
  • Multiport memories are generally useful for flexible buffering of data transfers. ' For example, they can be used to pass data between two processes which are independently clocked, or clocked at different frequencies.
  • the most straightforward way to achieve multiport functionality is by using memory chips which actually have independent data paths to each cell. (For example, a two-port SRAM of this type would have two pairs of pass transistors in each cell, and would be connected to two wordlines (one for each of the pass transistor pairs), and would also be connected to two bitline pairs. However, this approach does not scale well as the number of ports increases.
  • An alternative approach to multiport memory is to use a simple memory array (e.g. single-ported or dual-ported), with memory controller logic which arbitrates access to the array.
  • the memory controller logic may be on a separate integrated circuit, or may be integrated with the memory cells.
  • the closed-loop gain of an amplifer gain stage is normally adjusted using a resistor ratio. (That is, when a feedback resistor R F is interposed in the feedback path from the output terminal to the negative input terminal of a differential amplifier, and an input resistance R ⁇ is interposed between the negative input terminal signal and an incoming signal V ⁇ , the voltage gain V ⁇ /V j .. will be equal to the ratio of the resistances -Rp/R j .,.)
  • trimming resistor values to adjust the closed-loop gain of an amplifer. Such trimming methods will typically involve applying a laser beam to reduce the linewidth of a thin-film or thick-film resistor. Closed-loop amplifier stage gain values are adjusted, in some embodiments of the invention, by selecting components which have values scaled in powers of two. For example, if the smallest available value of the feedback resistor is R f0 , thin film (polysilicon) resistors would be provided with values of 2R f0 , 4R f 0 , 8R f 0 , etc.
  • the presently preferred embodiment provides such digitally scaled values not only for resistors, but also for capacitors.
  • the trimmable resistors and capacitors are adjusted to set both the center frequency and Q of a bandpass filter.
  • the mathematical relations which define the center frequency and Q of an active RC filter as a function of the component values used are very well known to those skilled in the art. However, the use of digitally scaled selectable components, so that the desired component values can be directly "dialed in,” is believed to be new in the art.
  • the value of a thin film resistor can be changed by changing the width/length ratio of a layer of a given sheet resistance, by changing the film thickness of a material of a given resistivity, by modifying the thin film layer so that it has a different sheet resistance (e.g. implanting it with a dopant), or by substituting a material with a different sheet resistance.
  • the preferred embodiment simply uses pattern modifications, to provide a variety of width/length ratios. This idea is particularly useful where high-gain amplifer stages may be needed.
  • Filtering electrical signals is one of the most basic operations in electronics. Typically filtering functions will be defined with reference to the frequency domain. For example, if a complex signal is passed through a "low-pass” filter, only those signal components which are below a certain frequency will pass through the filter. Similarly, a “bandpass” filter wQl pass only those signal components which are within a range of frequencies around a center frequency. (The “bandwidth" of a bandpass filter specifies how wide this range of frequencies is.) The filtering characteristics of an electrical circuit will be determined by the values and interconnections of the active and passive components used.
  • a filtering characteristic may be implemented in a wide variety of ways.
  • the different possible implementations can differ in many respects.
  • the power consumption of different implementations may vary.
  • the sharpness of the boundaries between the passband and stopband may also vary.
  • a very simple passive filter which includes only one capacitor and one inductance in series, will typically have a slope of about 6 dB per octave at the passband edges.
  • the wider the passband the less sharp the passband edges will be.
  • More complex circuits can provide much sharper slopes.
  • Different implementations may also differ in their area requirements, sensitivity to parameter variation, passband ripple, maximum attenuation, insertion loss, practicable frequency range, etc.
  • DSP Digital signal processing
  • the system design already includes a microprocessor or specialized DSP unit, and digital/analog and analog/digital converters, a substantial amount of hardware must be added before DSP techniques can be used.
  • DSP is likely to consume relatively large amounts of power, and may generate significant amounts of electrical noise.
  • microprocessors which can operate on extremely low power are also now available.
  • An important example is the DS5000, available from Dallas Semiconductor Corporation, Dallas, Texas. (This chip, and its description in the data books of Dallas Semiconductor Corporation, are hereby incorporated by reference.)
  • This microprocessor can operate with very low power consumption in active and standby modes. The power consumption is so small that this microprocessor can be used in an extremely compact module powered by a very small lithium battery, and still have good operating lifetime.
  • microprocessors can be useful in a very wide variety of applica ⁇ tions, and it would be very useful to be able to make use of them in a portable wireless data module.
  • the present invention provides a system architecture, for a "smart" portable wireless module, in which a large volume of memory space is shared by a microprocessor (or other complex chip) and by the demands of wireless access.
  • microprocessors are not the only type of integrated circuit which the present invention helps to integrate into a portable data module.
  • Different chips and/or multiple chips
  • display drivers can also be connected to memory through a high-data-rate internal bus.
  • customized signal processing chips adapted to functions such as speaker identification, can also be used.
  • More exotic chip types such as neural networks or cellular automata, can also be used (in suitably low-power versions).
  • the disclosed novel memory controller is not applicable only to portable modules, nor even to low-power applications generally.
  • the innovative teachings herein can provide improved access arbitration between serial and parallel ports, wherever a multiport interface to serial and parallel ports is used.
  • this controller architecture could also be used in much higher-data-rate environments.
  • Error-check-and-correct protocols are commonly used to preserve data integrity. However, in a wireless data communication system, which inherently has a high exposure to noise, one important class of error must be carefully avoided: if a write were to be directed to the wrong location in the module's memory, data integrity would be lost, even though the error checkbits for the data stream all indicated that- no error had occurred.
  • the presently preferred embodiment provides an architecture wherein a substantial amount of random-access memory (RAM) is included in the remote module.
  • RAM random-access memory
  • serial access protocol is used to control wireless accesses. Since the data rate of wireless access is rather slow, a special command is added to this protocol to accelerate access arbitration between wireless accesses to memory and the higher-bandwidth internal accesses.
  • the memory controller chip of the presently preferred embodiment provides dual-port access to single-port memory, where one of the two ports is serial and one is parallel.
  • an arbitration byte is used to avoid conflicts between the two ports. (Some bits of the arbitration byte can be written only by the serial port, and some bits can be written only by the parallel port.)
  • the serial port always has priority for access to the memory. Normally, in a multiport memory organization of this kind, the serial port would read, write, read the arbitration byte to check for no access collision.
  • a prime determinant of the lifetime is the power consumption when the integrated circuit is idle. For example, even a few microAmperes of standby current will exhaust a 2000- Joule battery within a ten-year lifetime.
  • Various design techniques can be used to reduce standby current, but the system designer can readily find other uses for any excess battery capacity. (For example, other functions may be added, or longer lifetimes specified, or smaller batteries used.) Since standby power consumption is a significant factor in design lifetime, the design lifetime must normally be dated from the time when standby power consumption begins.
  • the customer needs to know the lifetime from the time when he gets the part. To provide customers with this assurance, the manufacturer and distributors must therefore control the distribution chain so that the maximum time in inventory is known, and the design lifetime for the part must be reduced to allow for this maximum time in inventory. This is inconvenient. Moreover, in some applications a long inventory time is highly desirable. For example, in military or industrial applications it might be useful to keep a stock of "field spares" on hand, very close to the actual installation, so that a failed electronic module could be rapidly replaced.
  • the present invention provides a way to totally inactivate (or reactivate) a sealed integrated circuit module, without using any mechanical elements which might fail, or using any electrical contacts which might burden the hermeticity of the module packaging.
  • the present invention provides a micropowered module containing one or more integrated circuits and a battery.
  • the module is originally in a state of zero power consumption.
  • a very strong electromagnetic field is applied at a predetermined frequency.
  • the user can hold the module between the poles of a C-shaped solenoid which is being driven by a significant current at the appropriate frequency.
  • a very small and simple antenna is used to receive this energy.
  • the output of this antenna is, in the presently preferred embodiment, connected directly to the input of MOS logic gates, so that no current flows unless the incoming signal reaches a high enough voltage to switch the MOS transistors.
  • a preset pulse code at this frequency will be detected by subsequent logic elements, .and will change the status of a stored bit which identifies whether the integrated circuit should be turned off (Le. in "sleep" mode) or on. (although the integrated circuit is on, it may be in active or standby mode. This is determined by other logic, and is separate from the operations described.) In standby mode, the power from the battery will avoid data loss.
  • the lithium batteries preferably used have a very long shelf life, so that the time when the module is in sleep mode does not subtract from the design lifetime.
  • the manufacturer can ship modules which are in sleep mode, and the customer (or distributor) can activate the modules when they are nearing use. Only one chip in a module normally needs to have this sleep and wake capability. This chip can provide a control signal or a power supply output to the other chips accordingly.
  • the wireless "freshness seal" command can be used to command the module to wake up or to command it to go back to sleep.
  • a user who foresees a long idle time for a module can cause the module to go back into a zero-power- consumption mode until needed.
  • the present invention is particularly advantageous in a wireless-access data module, since the module can be made totally hermetic.
  • this wireless freshness seal is also advantageous in other module configurations too.
  • the lack of external switches or contacts improves the reliability of the module.
  • the fact that the freshness seal switching is not readily apparent may prevent unsophisticated users from inadvertently activating it, and losing functionality or stored data.
  • the present application discloses significant architectural innovations which provide improved functionality and power efficiency in a portable data module which can. be used for wireless data transfer.
  • the disclosed innovative teachings enable a portable data module, accessible by wireless communication.
  • the module includes an internal serial data bus, which carries data in a different coding scheme than that used on the wireless channel.
  • the internal data bus connects receiver/decoder chips to one or more memory chips, and to other integrated circuits if desired.
  • the innovative architecture provides a number of advantages, including architecture flexibility (le. the ability to rapidly modify the module's design to accommodate different functions).
  • architecture flexibility le. the ability to rapidly modify the module's design to accommodate different functions.
  • various alternative embodiments may optionally include a dual-port memory controller; an access control chip; a parallel data transfer connector; and various combinations of these.
  • a further advantage is the ability to include very complex functionality within a battery-powered portable data module.
  • the standardized bus interface permits a very large variety of functions to be easily integrated, including such functions as one or more microprocessors.
  • a further advantage is the ability to select between alternative communications channels. For example, it may optionally be desirable to be able to select between quite different communications channels, where different hardware is used for different channels.
  • the use of the serial bus can permit various custom chips to be included in the module, and powered-up only when needed.
  • a further advantage is the ability to perform high-bandwidth data manipulations within the portable module. Although the bandwidth of a wireless micropower communication link is normally very hmited, the internal serial bus permits a much higher data rate to be used within the module. This can be useful, for example, in applications where sophisticated cryptographic encoding or speech recognition capabilities are used.
  • this memory chip provides internal data communications which are decoupled from the design constraints of the wireless communication link.
  • pulse-width modulation is used on the send-data channel, together with a coding scheme and a data formatting protocol which provides reasonable protection against noise-induced errors.
  • the cost of this protection is a fairly low data rate.
  • the internal data bus is not as exposed to noise, and less protection can be accepted to achieve a higher data rate.
  • the disclosed innovative teachings enable an improved memory controller architecture.
  • a dual-port memory controller is used, which interfaces one or more memory chips to both a serial port and a parallel port.
  • the local bus which runs between the controller and the memory chip is defined so that multiple controllers can be stacked together to provide multiport access.
  • the present invention enables an expandable .system in which a memory is addressable by any desired number of serial ports.
  • a bank of memory (or other single-port resource) can be efficiently shared by multiple serial ports, even if the shared resource is not directly compatible with serial access protocols.
  • the disclosed innovative teachings enable a wireless data module which has a backup communication mode. Normally data is encoded into a pair of RF channels to achieve short-range communication, but the portable module also has a pair of touch contacts, which can override the RF link, thus permitting data communication if an RF channel is jammed or if the module's battery goes bad.
  • the touch contacts do not provide a full digital link, but are used for coded communication, at a frequency different from those used in the normal RF links. This permits isolation elements to be used, so that the touch contacts can be exposed to normal electrostatic discharge levels without destroying any key components of the module. This also permits the to.uch contacts to be relatively insensitive to the presence of dirt or corrosion.
  • the disclosed innovative teachings enable a receiver architecture which is not only advantageous in a portable wireless data module, but can also be used in a wide variety of other communications receivers where low power consumption is needed (and particularly where low standby power consumption is needed).
  • a micropowered RF receiver which uses a comparator (or comparators) at its input terminals. Preferably no analog gain stages are used, either before or after the comparator, and the comparator's input terminals are directly connected to an all-passive antenna circuit. This provides reasonable sensitivity, but does not consume large amounts of power in the standby mode.
  • a further subclass of embodiments uses feedback from pulse-counting logic to adjust the gain of the compa ⁇ ator(s) which receive the input.
  • the length of incoming pulses is measured, in a digital stage of the portable module, by a counter.
  • this counter When this counter reaches a count which is much longer than would be expected from any of the allowed set of symbols, it provides an overflow-indicating pulse to control logic which reduces the bias current supplied to the comparators 420 at the input to the receiver circuits, and thereby reduces the sensitivity of these comparators.
  • the current source in the input comparators in the receiver circuits is the primary location of standby power dissipation in the presently preferred embodiment. Therefore, the size of this current source is a significant parameter in designing the remote module: if the comparators are redesigned to draw more current, the sensitivity of the receiver circuits will be increased, but the battery lifetime will be decreased. The total charge available in the battery, and the desired design lifetime, set a limit to the current which can be drawn. The minimum current draw is defined
  • the channel width of the current source device is divided up between several devices in parallel. For example, where the maximum device width is W, this device width can be allocated into four parallel current-source devices having widths of W/15, 2W/15, 4W/15, and 8W/15.
  • a switching transistor is placed in series with each of these current-source devices, and a four-bit down counter is used as a current- source-control counter. The four output bit lines of the current-source- control counter are each connected to one of these switching transistors, to control one of the current-source devices.
  • a further feature of this class of embodiments is the use of a slow timer circuit to recover from saturation.
  • a simple RC timing circuit with a long time constant e.g. 1 to 10 seconds is used to periodically reset the current-source-control counter. This assures that the portable module will be able to rapidly recover from saturation.
  • the wireless data modules may includes two micro-antennas oriented to avoid coincident nulls. However, the RF signals cannot be directly combined, or the two antennas will simply act as one combined antenna, with a new " set of possible nulls.
  • the presently preferred embodiment uses two separate comparators, connected to separate antenna inputs, to detect the presence of an RF signal.
  • One of the two comparators is given preference, but, if no pulses are being detected by the primary comparator, the output of the secondary comparator is monitored. (Thus the two comparator outputs are combined in what is almost an OR relation, except that, once an incoming pulse train has been detected by one comparator, interference by the other comparator is avoided.)
  • U.S. Patent 4,584,709 to Kneissel et al. discloses a portable radio which switches between multiple antennas until an antenna with adequate signal quality is found.
  • the configuration disclosed in this patent uses separate tank circuits for the two antennas, with PIN diodes used to switch the tank circuits (and therefore the antennas) in and out.
  • Timesharing is used to monitor the signals on the two antennas, to see which is better, and the signal from the better antenna is connected to the receiver. (By contrast, the presently preferred embodiment does use timesharing in this fashion.)
  • the present invention provides a communications system which uses a variable-symbol-length coding scheme, such as pulse-width modulation
  • information is encoded (in the RF signal) as variable-duration pulses separated by quiet periods.
  • the length of the pulses is thresholded at several levels, so that each pulse can correspond to one of several symbols.
  • the pulse length thresholds are well separated, so that accurate
  • variable-length pulses are translated into pulse trains at the carrier frequency.
  • the 25 embodiment attempts to assign the most frequently used commands to the shortest pulses, to maximize the average baud rate.
  • the symbol for "reset" is the next- shortest symbol after the read and write symbols.
  • receiver circuits detect an
  • incoming pulse-width-modulated signal and generate digital pulse trains which are correspondingly burst-length-modulated. These variable-length bursts of constant-width pulses are counted.
  • An intersymbol detector watches for a ⁇ ri ⁇ ri ⁇ m.m silence period, which would indicate that one symbol has ended and another has begun. When an intersymbol silence is detected, the counter total is thresholded against a set of predetermined boundary values, using a ripple-through magnitude comparator. A series of one-bit outputs, showing the results of these comparisons, is then provided as inputs to a state machine. The state machine translates the various pulse length possibilities and drives lines to perform the appropriate action.
  • the present application not only discloses significant architectural innovations which provide improved functionality and power efficiency in the portable data module, but also discloses a complete system architecture and coding protocol which provides substantial advantages.
  • the power consumption constraints on a portable station are exceedingly stringent.
  • standby power consumption must also be reduced. That is, over the lifetime of the portable module (which should ideally be years), the portable module may be required to spend tens of thousands of hours in standby mode,' where it can detect an incoming query from a base station.
  • This difficult constraint also has implications for the choice of frequency. Higher frequencies permit higher data rates, but may require the use of devices which have greater power consumption. For example, in embodiments (such as the first embodiment discussed below) which use op amps for RF detection, higher frequencies mean that higher-bandwidth op amps (broad-broad operational amplifiers) must be used. Such op amps tend to have higher static power consumption.
  • comparators can be used for RF detection if the signal levels are sufficiently high (and the frequencies are sufficiently low). However, if lower signal levels must be detected (in a micropowered direct detection circuit), then op amps are preferably used.
  • the power level which is seen by the receiver is determined by various system parameters, including the size and configuration of the receiver antenna, the Q of the receiver antenna circuit, the power and antenna gain of the transmitter, and the ma ⁇ m ⁇ m distance between the transmitter and receiver. In the system described, comparators are considered to be satisfactory for a mim ' mnm detectable signal of 10 mV at 200 kHz. However, if the ini n detectable signal level is to be less than one millivolt, it is preferable to use op amps.
  • the frequencies used include: 300 MHz: (the "read-data" frequency): This UHF frequency is used for transmission from the portable module to the base station. This frequency falls in a relatively quiet part of the spectrum, where good range can be achieved This frequency also facilitates antenna design and placement, since a high-Q resonant antenna circuit can readily be configured to fit inside a small module.
  • This frequency is used for transmissions from the base station to the portable module. This frequency is low enough to permit a reasonably good power efficiency (in the receiving circuits) during data reception, while also permitting an acceptably high data rate to be achieved.
  • 100 kHz (the alternate "write-data" frequency): This is an alternate frequency, which can be used instead of 200 kHz for transmissions from the base station to the portable module.
  • the portable module in the presently preferred embodiment, also includes circuitry for receiving 100 kHz signals which are seen at a pair of electrical contacts. This provides a back-up data channel which permits a user to bypass the RF link. This can be particularly useful in factory automation or other high-noise environments. If desired, the module can be readily reconfigured so that this frequency is received by an antenna, instead of (or in addition to) the 200 kHz antenna. Due to regulatory constraints, this frequency may be available in some places where the 200 kHz is not usable.
  • 20 kHz (the "wakeup” frequency): This frequency is used solely to initiate wake-up of the portable module. When the module is in standby mode, it monitors this frequency only. A base station broadcasts a signal on this frequency to wake-up nearby portable modules. 2 kHz (the “freshness-seal” frequency): This lowest frequency is monitored with essentially zero standby power. This is done by connecting the antenna input directly to an MOS gate (biased at ground), so that no current is drawn unless the signal is large enough to turn on the transistor, Le ⁇ exceeds one V ⁇ (threshold voltage). Pulse trains at this low frequency are used to switch the module out of (or into) a shutdown mode, where the module is not even monitoring the 20 kHz frequency.
  • the signals at this lowest frequency must be of large magnitude, such as would be achieved by physically inserting the module in the slot in a toroidal coil, or between a pair of driven electrodes.
  • the power required to monitor the 20 kHz frequency in the standby mode is approximately two orders of magnitude less than that required to monitor the 200 kHz frequency in the active mode.
  • the power saving achieved by this frequency allocation is very considerable.
  • only four frequencies can appear at the portable module, since the 20 kHz wakeup signal is not used.
  • the 2 kHz and 100 kHz frequencies are not often used, and the 200 kHz (or equivalent) and 300 MHz (or equivalent) frequencies provide the primary data channels.
  • the specific frequencies referred to are merely illustrative, and verbal labels are accordingly used to refer to disclosed frequencies and to other frequencies which could be substituted therefor.
  • the specific frequencies are not at all critical, although some aspects of the relation of frequencies, and of the frequency bands used, are particularly advantageous and are believed to be novel.
  • the specific frequencies used in the sample embodiments described can easily be changed (to a certain degree) simply by changing the values of reactances in the disclosed circuits.
  • the disclosed innovative teachings provide a wireless data-interface system, where the identification field (which is 64 bits long in the presently preferred embodiment) can be parallel polled.
  • the base station can see the 64-bit identification fields combined in what is almost a "wired-OR" fashion. That is, if any one of the portable modules within range is pulsing (reporting a "1" bit) in a given time window, the base station will see a pulse; the base station will see the absence of a pulse only if all of the modules within range are reporting a "0" bit (not pulsing).
  • This can be used, for example, to implement combinatorial logic functions on all (or some subfields of) the 64-bit identification field.
  • Disclosed innovative teachings advantageously enable a wireless data communication system, including at least one base station and at least one low-power portable module.
  • RF assignments, protocols, and coding are chosen to permit the portable module to provide data exchanges with the base station over very short distances, at moderate baud rates, with high power efficiency in the portable modules.
  • a connector, including a power supply input, is also provided on the portable module. Using this connector permits the data in the portable module to be read out very rapidly, even if the data has been accumulated from a long series of transactions.
  • the power supply input means that block-dump operations can be performed as often as desired without degrading the battery lifetime of the portable module, no matter how large the memory in the module is.
  • the disclosed innovative teachings provide a very simple filter circuit, which is all-digital but does not require the complex circuits and techniques used in DSP techniques. In effect, the present invention exploits the analog properties of digital circuit configurations.
  • a simple digital inverter will usually have fairly sharp low-pass cutoff characteristics. That is, an analog input signal at a certain frequency, applied to a logic gate with a certain time constant, will provide a peak voltage which depends on only three factors: the peak voltage of the input signal; the RC time constant of the circuit; and the frequency of the input signal. If the frequency of the input signal is low enough, in relation to the RC time constant, the analog input signal will be able to switch the logic gate on each cycle, so that the output of the logic gate will contain a strong signal component at the input frequency.
  • the present invention makes use of this characteristic to provide a compact, low-power, bandpass filter.
  • the characteristic of this filter has very sharp band ' edges, and essentially no ripple in the passband.
  • this filter configuration is relatively insensitive to parameter variation.
  • This filter configuration is particularly advantageous at low frequencies and in low-power systems.
  • the presently preferred embodiment uses the time constants of the inputs to two logic gates to define the upper and lower passband edges.
  • the passband center frequency is 2 kHz
  • two digital inverters are used, with cutoff frequencies which bracket the desired signal frequency (e.g. 1500 Hz and 2500 Hz).
  • the cutoff frequency of the two digital inverters is selected by changing their RC time constants. (In practice, this is done merely by adding series resistance or shunt capacitance in the gate circuit.)
  • the inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff frequency has its output connected to the clock input of a counter.
  • the counter output is monitored, to see when a certain count threshold has occurred.
  • this very simple digital circuit provides a bandpass filter, with sharp passband edges. This filter also has the advantage of very sharp rejection of 1/f noise.
  • this circuit performs both filtering and thresholding functions: an in-band signal must be present, and must have sufficient magnitude, before any AC component will appear in the output of the logic gate.
  • this circuit is not linear, and will treat complex signals quite differently from simple signals.
  • This circuit is particularly well adapted to detecting the presence or absence of an in-band signal whose energy is largely concentrated at a single frequency.
  • This circuit is less well adapted to passing more complex in-band signals, since (in this circuit) the different frequency components may interfere with each other.
  • this circuit can be used to detect the presence of -in-band energy, and enable a more complex circuit to perform more complex filtering operations accordingly.
  • the output of this circuit can be used to provide a clock signal which is used to synchronize other circuits to the principal in-band frequency of the incoming signal.
  • Another feature of this circuit is that even a strong in-band signal can be blocked by low-frequency noise.
  • a large series capacitor can be used to attenuate the lowest frequencies.
  • the present invention is particularly advantageous in low-power applications. Where the incoming analog signal is expected to be a strong one, it can be connected directly (i.e. without amplification) to the logic gates being used for filtering. This means that no power is consumed if the incoming signal is not able to trip either of the logic gates.
  • the disclosed innovative teachings provide a battery-powered module architecture which is particularly advantageous where a serial data interface is used to link two (or more) integrated circuits within the module.
  • a battery- powered system where a first integrated circuit provides a secondary power supply to a second integrated circuit, and also provides data signals in a serial protocol. The first integrated circuit steps down the secondary power supply when the reset-bar signal is being driven high. The second chip goes active whenever its reset-bar input exceeds its battery-voltage input.
  • a scaled supply voltage output is provided by a data converter chip to downstream chips (including an access control chip, in the presently preferred embodiment).
  • the access control chip (in the presently preferred embodiment) goes active whenever its RST* input exceeds its V BAT input. Since RST* can be driven only to the positive power supply level, the converter chip provides the access control with a reference voltage level which is lower than the power supply level. (However, to minimize power consumption, this reference voltage level is lowered only when necessary, ije. when the RST* line is being driven high.) This reference voltage is connected to the V BAT input of the access control chip.
  • a further feature is that the switching transistors are arranged in a configuration such that two transistors would have to fail before the battery could receive uncontrolled charging current. This provides improved safety.
  • the disclosed innovative teachings provide additional insurance against data corruption, by testing for errors in the address field before any memory write is permitted to occur. This prevents data corruption due to errors in the address field, without greatly degrading the overall data rate.
  • the presently preferred embodiment provides an architecture wherein a substantial amount of random-access memory (RAM) is included in the remote module.
  • RAM random-access memory
  • the presently preferred embodi- ment uses error-checking logic to implement a cyclic redundancy check.
  • the cyclic redundancy check is used to detect errors in data transmission. It is also used to lock out access if a bit error occurs anywhere in the protocol word (which includes the memory address bits). Thus, one-bit errors cannot cause data to be written to the wrong address in memory.
  • the claimed inventions are used in the context of a wireless-accessible data module.
  • Various features of this system context will therefore be described in great detail below.
  • the general features of this context will now be described.
  • Many of the innovative teachings of the present application will initially be described in the context of an embodiment, as shown in Figure 1, wherein RF communication is established between a base station ' and one or more portable data modules.
  • Each portable module can be accessed, in slave mode, by a base station 110 whenever the portable module comes within range of the base station.
  • a split frequency allocation is used on the RF channel.
  • the base station transmits at a relatively low frequency (referred to herein as the "write-data” frequency), and the remote module transmits at a much higher frequency (referred to herein as the "read-data” frequency).
  • the transmitter powers used permit communication over a very short range.
  • the portable data module is preferably extremely compact, and is powered by an small non-rechargeable battery.
  • the base station is assumed not to be power-limited, but of course the innovative teachings set forth herein could also be applied to systems where some of the base stations are micropowered and/or some of the portable modules are not micropowered.
  • each variable-length pulse in an incoming RF signal is converted into a variable-length burst of digital pulses. These bursts are decoded to derive commands and data.
  • the portable module operates in slave mode, so that the commands thus received govern its operation.
  • the portable module also contains an internal serial data bus, and memory or other devices in the portable module can be written to (or read from) over this serial bus, as commanded by the incoming RF signals.
  • the 3-wire serial data bus within the portable module can be used in a variety of ways.
  • this bus is connected to an access control chip and to the converter chip.
  • this bus is connected to a memory controller chip (instead of the access control chip), and, through the memory controller chip, to an SRAM.
  • additional micropowered integrated circuits such as a microprocessor or display driver
  • the portable module preferably also contains access control logic, to provide security against unauthorized access, this can be omitted if desired.
  • the portable module has the capability to be completely turned off or on, by wireless control. By keeping the receiver circuit turned off until the module is put into service, the battery life is conserved. In the off state (which is referred to as the "sleep" or "freshness seal” mode, as distinguished from the standby mode), the battery drain is reduced to transistor leakage currents - almost zero power (a few nanoamps). To put the module into service, the whole module is placed in a strong 2 kHz electromagnetic field. A strong coded signal at this frequency is detected by zero-standby-power circuits, with control logic to turn on or turn off all the other detection functions of the receiver. BRIEF DESCRIPTION OF THE DRAWING
  • Figure 1 shows the general organization of a wireless communication system enabled by the present invention, wherein a base station 110 can send data to a nearby remote module 120 at a first frequency, and can receive data from the remote module 120 at a second frequency.
  • Figure 2A shows a block diagram of the remote module 120, in a first embodiment.
  • Figures 2B and 2C show a more detailed circuit diagram of the module of Figure 2A, including discrete reactances and the VHF/UHF transmitter circuit.
  • Figure 2D shows an alternative embodiment of the portable module portion of Figure 2A, including a large block of memory, a memory access controller, and an external connector which allows a rapid readout of the stored data.
  • Figure 3A is a block diagram, showing key signal connections, of the base station 110 shown in Figure 1.
  • Figure 4A shows the organization of some functions of the receiver chip 210 of the presently preferred embodiment.
  • Figure 4B shows the preferred implementation of the bandpass filter used in the receiver chip 210.
  • Figure 4C shows a second embodiment 210' of the receiver chip, which can detect lower signal levels.
  • Figure 4D shows further details of the configuration of a single amplifier stage with constant-multiplier-scaled arrays of feedback and series resistors.
  • Figure 4E shows further details of an active bandpass filter stage with constant-multiplier-scaled arrays of capacitors and feedback resistors.
  • Figure 4F shows how digital automatic gain control is performed in the receiver chip, in an alternative embodiment.
  • Figure 4G shows a further alternative embodiment, wherein digital automatic gain control is performed by using transistors to selectably switch out individual elements of a resistor ladder.
  • Figure 5A shows the overall organization of the converter chip of the presently preferred embodiment.
  • Figure 5B shows the power switching circuit preferably used in the converter chip of Figure 5A
  • Figure 5C shows the control logic 550 preferably used in the converter chip of Figure 5A.
  • Figure 5D shows an alternative embodiment of the converter chip of Figure 5A, and shows separately some additional portions of the control logic 550, as well as the input select.
  • Figure 5E shows the timing relations used, in the presently preferred embodiment, to implement the pulse counter 530.
  • Figure 5F shows an eight-bit digital magnitude comparator which is preferably used within the pulse width detector 530.
  • Figure 5G shows the state diagram which is preferably implemented by the state machine 552 shown in Figure 5D.
  • Figure 6A is a block diagram of the access control chip used in the presently preferred embodiment, in its normal mode of operation.
  • Figure 6B is a flow chart of the normal mode of operation of the access control chip of Figure 22.
  • Figure 6C is a block diagram of the access control chip used in the presently preferred embodiment, in its program mode of operation.
  • Figure 6D is a flow chart of the program mode of operation of the access control chip of Figure 6A
  • Figure 7A shows an overall block diagram of the memory controller chip 260 which is used in the alternative remote module embodiment of Figure 2D.
  • Figure 7B shows the communication protocol preferably used in the memory controller chip 260.
  • Figure 7C shows the command structure for selectable masking of address bits in the memory controller chip 260.
  • Figure 7D shows the format of the arbitration byte preferably used to arbitrate between the two ports which may seek access to memory, through controller 260.
  • Figure 7E shows the logic used, in the presently preferred embodiment, to generate the cyclic redundancy check (CRC) data.
  • Figure 8 shows how the converter chip, in the presently preferred embodiment, controls its power-supply output line to help other chips receive data from the serial bus.
  • CRC cyclic redundancy check
  • a portable data module can, for example, be attached to a product on an assembly line. As the product moves from station to station, the portable module 120 can be interrogated to let the station known what the product is, what operations must be done, what the next destination is, etc.. all without physical contact.
  • One example of this is in semiconductor manuf ⁇ cturing, where an RF-accessible data module, embedded in a wafer carrier, can provide an instantly accessible detailed processing history of the wafer or lot being transported. This remotely accessible data memory provides an important tool for reconciling automated handling and transportation with highly flexible and reconfigurable workpiece routing.
  • Another advantageous instance of work-in-process tracking is in livestock management.
  • the history of each animal can be carried with it, and automated gates can be used to select animals as desired.
  • feeding can be controlled to optimize the rate of weight gain, and animals which are off their feed can be detected very promptly.
  • a related class of applications is for inventory control. Note that the disclosed communication system can be used for completely automatic inventory control, since each base station can readily ascertain what portable modules 120 are in its vicinity. Similarly, base stations mounted at every entrance and exit can track all movements of inventoried goods.
  • the wireless system disclosed can also be used to provide a wireless link between a hand-held terminal and a host system.
  • Another related class of applications is for monitoring and control of machinery or other capital equipment. For example, maintenance and use records of vehicles or other machinery can be automatically maintained and remotely queried.
  • a portable module 120 can be used to store extensive identification parameters for the person to whom it is assigned, including (for example) height, weight, voice recognition parameters, or even parameters for image recognition (of fingerprints, faces, or retinas).
  • Base stations 110 can be positioned at key movement bottlenecks in a large building, so that the movements of individuals can be tracked. Thus, for example, in secure facilities, access intrusions can be detected, and movements of persons without clearance can be tracked. In hospitals, control of inpatient movements can be readily achieved. Where the present invention is used to monitor personnel movements, infrared sensors (or other such auxiliary remote sensors) can be used to detect any individual who is not carrying a functional remote module 120.
  • Medical applications generally are a very advantageous class of embodiments. Key parts of a patient's medical records (including, for example, recent weight and temperature data, and current medication authorizations) can be stored in a remote module 120 which is physically attached to the patient. Similarly, the source and history of specimens can be tracked by data modules.
  • Another class of applications is in financial instruments, such as credit cards, securities, large checks, letters of credit, or large-denomination currency.
  • the disclosed communication system permits the convenience of bearer instruments to be provided without the untraceable diversion possibilities of conventional bearer instruments.
  • the remote polling capability of the disclosed system permits convenient query for authentication, as well as remote detection of spurious items.
  • FIG 1 schematically shows a very simple system embodiment, where RF communication is established between one base station module 110 and one portable data module.
  • the base station module 110 interfaces to a host system (e.g. using a wired serial bus), and also provides an RF communications link to one or more remote modules 120.
  • the remote modules 120 are preferably small portable units, which operate with very high power efficiency from a battery. (Units of this type are generally referred to as "micropowered.")
  • a split frequency allocation is used on the RF channel.
  • the base station 110 transmits at a relatively low frequency (referred to as the "write-data” frequency), and the remote module 120 transmits at a much higher frequency (referred to as the "read-data” frequency).
  • the read-data frequency actually falls in the VHF or UHF bands, and the write-data frequency falls within the LF (low-frequency) band.
  • a pulse-width modulation coding scheme is used for transmissions on the write-data frequency channel.
  • This scheme provides good noise immunity, and the code assignments are selected to optimize the data rate (by assigning the most frequently used symbols to the shortest pulse widths).
  • the RF transmitter is simply switched on or off, to provide binary (on or off) pulses of varying length.
  • a simple binary amplitude shift keying scheme is used for transmissions on the read-data channel.
  • the RF organization is designed for very short-range communications. However, the power levels of the RF channels are very unequal. Higher transmitter power and net receiver sensitivity are preferably located in the base station, where the power budget, and the volumetric constraints, are less limited.
  • Each active base station 110 can broadcast a query signal, to determine whether any portable data modules 120 are in its vicinity. If one of the remote modules 120 is within range (e.g. within 5 feet or less), it will detect the base station's query signal, and will then put out a beacon response by keying its ttansmitter (on the read-data frequency) with a square wave (e.g. by chopping at a 10 kHz rate). The base station scans the read-data frequency band, to detect any such beacons. Once the beacon is detected, the base station 110 can then initiate an RF communication session, and get read or write access to the data memory in the portable module 120.
  • a beacon response by keying its ttansmitter (on the read-data frequency) with a square wave (e.g. by chopping at a 10 kHz rate).
  • the base station scans the read-data frequency band, to detect any such beacons. Once the beacon is detected, the base station 110 can then initiate an RF communication session, and get read or write access
  • One full transmission and reception cycle contains 280 bits, maximum, and is called a transaction.
  • the 10-year estimated battery life allows for more than 10 s transactions during the portable module 120's lifetime.
  • the portable module 120 is slaved to the base station 110.
  • an access control chip is used in the portable module, and this chip includes a 64-bit identification field and a 64-bit password
  • the converter chip also includes a 16-bit chip-selection-tag field, which can be used for first-level scan of possible portable modules within range.
  • the access control preferably also has the capability to generate random data when access is attempted without the correct password.
  • the base transceiver transmits a command, on the write-data frequency, requesting (normally) that the module's 64-bit identification code be returned.
  • a 64-bit password is transmitted to "unlock" the secure memory in the access control chip, so that data can be read from it or written to it.
  • Two features speed up the base station's ability to identify which of the possible remote modules may be within its range. These features may be particularly useful in applications where a large number of remote modules may come within range of a given base station.
  • the base station can scan over segments of the 16-bit chip-selection-tag field to rapidly identify whether a given module is nearby. This means that all possible combinations of the 16-bit chip-select field can be scanned in 8x2 2 searches, rather than 2 16 as would otherwise be required. (Of course, if more than one portable module is nearby simultaneously, the amount of time required to identify all modules present may well be longer than 8x2 2 searches.) '
  • a further optional alternative embodiment permits parallel polling of the 64-bit identification field.
  • the base station can see the 64-bit identification fields combined in what is almost a "wired-OR" fashion. That is, if any one of the portable modules within range is pulsing (reporting a "1" bit) in a given time window, the base station will see a pulse; the base station will see the absence of a pulse only if all of the modules within range are reporting a "0" bit (not pulsing).
  • This can be used, for example, to implement combinatorial logic functions on all (or some subfields of) the 64-bit identification field.
  • the portable data module is preferably extremely compact, and is micropowered.
  • the base station is assumed not to be power-limited, but of course the innovative teachings set forth herein can also be applied to systems where some of the base stations are micropowered and or some of the portable modules are not micropowered.
  • RF radio frequency
  • the portable data module 120 provides a miniature transportable electronic memory, together with a self contained transmitter, receiver, and power supply, which provides wireless data communication, via a base station 110, with a host computer system.
  • the small, lightweight construction makes the device suitable for carrying in a pocket or for direct attachment to any mobile object.
  • FIG. 2A shows an overview of the remote module 120.
  • the RF receiver functions are segregated on a receiver chip 210. No decoding is performed by the receiver chip 210. Decoding and encoding are performed by a converter chip 220, which also controls the serial data bus 206 within the remote module 120.
  • the receiver chip 210 receives an RF signal (from an antenna tuned to the write-data frequency), and tracks the amplitude shifts of the RF signals to output a burst of pulses (at full digital logic levels).
  • the duration of the digital pulse bursts at the receiver chip's output corresponds to the duration of the analog pulse seen at its input from the write-data RF channel.
  • the receiver chip 210 Since the output of the receiver chip 21Q is simply pulse bursts, the receiver chip 210 is connected to the converter chip 220 by a simple one-wire bus, with no clock or reset signals required.
  • the data converter chip 220 decodes the pulse bursts provided by the receiver chip 210. This converter chip translates these digital pulse bursts from the one-wire pulse-width modulation protocol to data signa. ls on a conventional 3-wire serial data bus 206 within the portable data module 120.
  • the 3-wire serial data bus 206 within the portable module can be used in a variety of ways. In the presently preferred embodiment, this bus is connected to an access control chip 230 and to the converter chip 220. (In an alternative embodiment, as seen in Figure 2D, bus 206 is also connected to a memory controller chip 260, and, through the memory controller chip 260, to SRAMs 262.) In further alternative embodiments, additional micropowered integrated circuits (such as a microprocessor or display driver) can also be included in portable module 120, and connected to bus 206, if desired. Similarly, while the portable module preferably also contains access control logic, to provide security against unauthorized access (e.g. implemented as access control chip 230), this can be omitted if desired.
  • access control chip 230 e.g. implemented as access control chip 230
  • the portable module 120 has the capability to be completely turned off or on, by wireless control.
  • the receiver circuits When the receiver circuits are turned off, the power consumption is essentially zero.
  • the battery life is conserved.
  • the off state (which is referred to as the "sleep" or "freshness seal” mode, as distinguished from the standby mode)
  • the battery drain is reduced to transistor leakage currents - almost zero power (a few nanoamps).
  • the whole module 120 is placed in a strong 2 kHz electromagnetic field. A strong coded signal at this frequency is detected by zero-standby-power circuits in the receiver chip 210, which control logic to turn on or turn off all the other detection functions of the receiver.
  • variable-duration pulses received on the write-data channel, and converted by the receiver chip 210 into variable-length bursts of digital pulses on the one-wire connection to converter chip 220, are decoded by the converter chip 220 into one of the set of possible symbols (commands).
  • the possible command set includes: A. Write 0 or read when active;
  • This bus includes one line reserved for clock signals, one bidirectional data line, and one line reserved for Reset signals.
  • Such a bus can readily be connected to serial- port memory chips, or to port pins on a DS5000 or on other microcontrollers sold by Dallas Semiconductor.
  • One important alternative embodiment uses a modified receiver chip 210', and a slightly different RF frequency allocation.
  • the portable data module 120 has the capabihty to detect quite weak RF signals (RF voltages down to about 300 micro Volt).
  • the alternative receiver chip 210' uses op amps rather than comparators at its input. To minimize the power drain of these op amps in standby mode, a much lower frequency (e.g. ten times lower than the write-data frequency) is used solely for wakeup.
  • a touch-contact port 270 is also provided. Signals received at this port will override signals received from the antenna 121 which receives signals on the write-data frequency. Preferably this input is connected directly to the converter chip 220, so that antenna 121 and receiver chip 210 are bypassed if this input is used. In the presently preferred embodiment, the touch contact port 270 transfers data using a carrier frequency of 100 kHz.
  • the port 270 provides a backup interface mode, which can be used to supplement the RF interface in (e.g.) high noise environments, or when the battery of the portable module 120 is weak.
  • the capability to handle a 100 kHz interface also provides useful versatility, since the module can be reconfigured fairly easily to (for example) provide capabihty for both 100 kHz and .200 kHz RF links.
  • An advantage of the encoding used on the write-data channel is that it is relatively insensitive to frequency. For example, when data is being transferred over the touch-contact port 270, the exact same coding can be used as would be used for transfer over the write-data channel. The data rate will be lower, because the frequency is lower, but the state-machine decoder circuits in the converter chip 220 can still operate in the same way. Similarly, the frequency assigned to the write-data channel can easily by changed, simply by changing or varying the reactive elements in the turned circuits, but the coding scheme will still provide a good balance of data rate with noise immunity at whatever frequency is being used.
  • variable-duration pulses sent by the base station 110 at the write- data frequency (200 kHz) are picked up by the write-data receive antenna 121, and are thereby seen at the comparator input terminals (A+ and A-) of the receiver chip 210.
  • the receiver chip 210 will amplify the analog input pulse signals from as low as 10 mV to provide full digital level pulse-burst signals at the output pin.
  • the receiver chip 210 does not demodulate the RF input signal, but simply amplifies its instantaneous level.
  • the carrier is a component of the amplified digital signal, so that what is sent to the converter chip 220 is not merely a series of variable-length pulses, but a series of variable-length bursts of constant- length pulses.
  • two parallel tuned antenna circuits 121 are used for reception the write-data (200 kHz or equivalent) frequency, and each of the antenna circuits is separately connected to an open loop comparator. (These connections are shown in Figure 4A as input pairs A+/A- and B+/B-.)
  • the tuned .antenna circuit 121 at the write-data frequency is also coupled to a tuned tank circuit, and/or to a notch filter centered at half the pass frequency, to provide sharper passband characteristics.
  • a tuned circuit with a discrete inductance is used to receive signals at the freshness seal frequency, but no other antenna is used. (Thus, the effective antenna cross-section at this frequency is very small. This is acceptable because the freshness seal only needs to detect very strong signals.)
  • the input to the freshness-seal-signal detection circuits is labelled as signal "FT 1 .
  • the converter chip 220 is basically a state machine, which controls the serial bus 206 and determines what action is to be taken by the attached access control chip 230.
  • the access control chip 230 receives signals from the converter chip 220 over the bus 206. These signals either write data into or read data out of the access control chip 230.
  • the access control chip 230 includes specially partitioned memory space, which stores a 64 bit identification code and a 64-bit password.
  • the password memory is combined with comparison logic, so that data accesses are screened for password match.
  • the password memory (which, in this embodiment, includes 128 bits of readAvrite nonvolatile memory) cannot be read, and can be overwritten only by an access which includes a match with the existing password.
  • the converter chip 220 When the portable data module is receiving data to store in the access control chip 230, the converter chip 220 generates the CLK, RST* and data signals, in accordance with data received from the receiver chip 210. However, when the portable data module is being read, data is transmitted back to the base station 110 via a 300 MHz transmitter which is controlled by the converter chip 220.
  • the portable data module is self powered by a lithium energy cell.
  • the unit is designed to last for over ten years.
  • the converter chip 220 and receiver chip 210 control the energy consumption and power distribution within the module.
  • FIGS 2A-2C show a more detailed view of the portable module 120 of the presently preferred embodiment.
  • a timed coil 121 acts as an antenna, and is connected, through an RLC filter network, to a receiver chip 210.
  • the receiver chip 210 provides an output, at full digital levels, to a data converter chip 220.
  • the receiver chip 210 and the data converter chip 220 are both powered from a battery
  • an access control chip 230 is connected to the data converter chip 220 by the 3-wire serial data bus 206.
  • the access control chip 230 can receives its power supply voltage from the data converter chip 220 either over the RST* line, or (when RST* is low), over the V BAT input (which is connected to the reduced-voltage supply BATOUT of the- converter chip 220).
  • the data converter chip 220 also provides a signal RFOUT, which controls a transmitter 240 (shown in Figure 2C).
  • Figure 2D shows an alternative embodiment of the portable module 120 portions shown in Figure 2B.
  • a memory access controller 260 is also connected to the 3-wire data bus 206 from the converter chip 220 to the access control chip 230.
  • This memory controller is connected to a block of memory, such as a pair of 256K SRAMs 262.
  • the preferred memory access controller 260 can control up to 16 32Kx8 SRAMs.
  • Figure 2D also shows the further alternative feature of a parallel port contact 290. (Note that this is not the same as the touch-contact port 270, which provides serial data transfer.
  • the parallel port 290 unlike the serial port 270, provides data transfer which is much faster than that achievable over the RF channel.
  • the parallel port 290 can be connected to a complementary parallel port connector, to permit a rapid dump of all the data in memo ⁇ y with burden on the battery 250.
  • a parallel port contact 290 can be used without the memory controller chip 260 (especially if serial-ported memories 262 are used, or if a microprocessor is also included in the portable module).
  • a memory controller chip 260 can be used advantageously, even if the parallel port contact 290 is not included.
  • the memory controller chip 260 in the presently preferred embodiment, provides dual-ported access to a parallel memory bus 703. Access is shared between serial bus 206 and parallel bus 701 (which is connected to the connector 290 in embodiments like that of Figure 2D).
  • parallel port 290 preferably also includes a power input, which is connected to a power supply input of the converter chip 220. When the converter chip 220 detects a voltage higher than V BAT on this input, it will switch over to the higher supply voltage. This means that the rapid readout cycles will not place a burden on the battery 250.
  • This embodiment permits a large volume of data, collected in portable modules over a relatively long period of time, to be rapidly downloaded. Thus, the wireless communications channels can be organized for very high power efficiency, at very low data rates, since a.
  • a further advantage of this class of embodiments is that very large amoimts of memory (e.g. a megabyte) can be used in a micropowered portable module, while still achieving long data-retention lifetimes.
  • This fast data dump capabihty is particularly advantageous for applications (such as delivery logbooks, retail inventory, or vehicle management), where data is collected slowly in the field, and then rapidly dumped at a more central location.
  • One important alternative embodiment uses a modified receiver chip 210', and a slightly different RF frequency allocation.
  • the portable data module 120 has the capability to detect quite weak RF signals (RF voltages down to about 300 micro Volt).
  • the alternative receiver chip 210' uses op amps rather than comparators at its input.
  • an additional RF frequency (which is a much lower frequency, e ⁇ . ten times lower, than the write-data frequency) is used solely for wakeup.
  • the write- data frequency is not monitored when the module 120 is in standby mode.
  • Another pair of op amps which have a lower slew rate and smaller gain-bandwidth product than those used to track the signals on the write-data channel, are kept active to monitor an antenna input at the wakeup frequency. Any inputs received on the wakeup frequency are decoded by a very simple thresholding scheme, like that used to decode symbols on the write-data frequency, which provides noise rejection. If a properly encoded signal is detected on the wakeup frequency, the (higher- powered) detection circuits in the write-data channel are turned on.
  • the receiver chip 210 will draw about 1 microAmp, while amplifying incoming RF signals at the wakeup frequency (20 kHz in this example) to digital pulse bursts on one-wire bus 215. These pulse bursts are momtored by the converter chip 220, and when the proper sequence occurs the converter chip 220 provides an enable signal EN back to input El of the receiver chip 210. After this enable signal has been received, the receiver chip 210 activate a higher- power pair of op amps, which have a high enough slew rate and gain- bandwidth product to track signals at the write-data frequency, and which draw about 100 microAmp. The receiver chip 210 will stay enabled for as long as signals are seen at either the write-data frequency or the wakeup frequency. If neither signal is present for 2 msec, the 200 kHz receiver will automatically turn off. The 200 kHz receiver can also be turned off by a specific sequence of 20 kHz signals.
  • FIG. 2C shows details of the transmitter 240.
  • This transmitter is powered and controlled by signal RFOUT, which is provided by the data converter chip 220.
  • signal RFOUT is pulled high, transistor 241 is enabled to turn on.
  • the transistor 241, in this example, is an NPN transistor with a cutoff frequency substantially higher than the desired transmission frequency. For example, an MRF931 has been found to be satisfactory.
  • the various reactances shown provide feedback, so that the transistor 241 sustains oscillation.
  • the oscillation output is connected to read-data transmit antenna 122.
  • Antenna 122 is preferably an etched PC board trace, tuned by a discrete capacitor 242 to achieve resonance at the desired operating wavelength (which in this example about 100 centimeters).
  • the desired operating wavelength which in this example about 100 centimeters.
  • Such stabilization means that the base station does not have to sweep so broad a band to detect an incoming signal.
  • Figure 2C shows-a SAW filter used to provide a reactance from gate to ground, but a capacitor may be used instead if a lower insertion loss or lower Q is desired.
  • the antenna is connected across the tank circuit: this has been found to be advantageous in such low-power applications.
  • FIG. 3A shows key blocks and key signal connection of the base station 110 of the presently preferred embodiment.
  • a digital interface 300 interfaces to a standard RS232 bus, using data lines HOST_TXD and HOST_RXD. This digital interface permits the host computer (or a terminal) to provide an interface to the transmitter 301 and the receiver 302.
  • the receiver 301 is shown in several blocks, to clarify the functions performed.
  • Antenna 112 is tuned to the read-data frequency, to receive RF signals transmitted by a portable data module 120.
  • This antenna is connected, through a bandpass filter 320, to an RF receiver section 330.
  • Section 330 provides outputs' RFA, indicating amplitude of the RF signal, and outputs QUAD and /QUAD, which respectively correspond to the average amplitude of leading and lagging phase components.
  • Block 340 performs the ASK (amphtude-shift keying) and automatic frequency control (AFC) functions.
  • ASK amphtude-shift keying
  • AFC automatic frequency control
  • the AFC operation is controlled by a feedback loop which extends through several of the components:
  • the ASK/AFC block 340 compares the signals QUAD and /QUAD, to determine if the frequency needs to be adjusted. That is, phase error in one direction will indicate that the local oscillator is leading the incoming RF signal, and phase error in an opposite direction will mean that the local oscillator is lagging.
  • the FREQJHIGH or FREQ_LOW lines are driven.
  • the digital interface 300 increments or decrements a control value, which is converted by a digital/analog converter in the interface 300 to provide the signal DAC.
  • the signal DAC is fed back to control the local oscillator frequency and RF section 330.
  • the digital interface 300 controls a 200 kHz transmitter 302. This transmitter is shown as switching (control) transistor 1710, antenna 1720 (or 111), and resonator circuit 1730.
  • This sample transaction will be a normal read of the data in access control chip 230.
  • the access control chip 230 has contents as follows (where each byte is represented as two hexadecimal numbers):
  • the base station will have to know (from user input, or from data stored in the host computer) that the password is 01 23 45 67 89 AB CD EF.
  • the base station 110 is told (for example) to read the first portable data module it finds. The conversation now proceeds as follows:
  • Step 1 The base station turns on the beacons of all keys in range. This is done by sending (on the write-data frequency) pulse group
  • any portable modules in range will be in beacon mode, and will be transmitting a 300 MHz ( ⁇ 15 MHz) RF carrier, chopped at a 5 kHz rate.
  • Step 2 The base station 110 then sweeps its 100 kHz bandwidth input band pass filter 320 from 285 MHz to 315 MHz. At each step the base station 110 looks for the presence of any beacon from a portable module 120. Since any beacon will be chopped at 5 kHz (100 microsec on, 100 microsec off) the base station 110 must search each frequency range for at least 100 microseconds. (In alternative embodiments the sweep time can be decreased by increasing the beacon chopping frequency.) If no signal is present at a given step, the bandpass filter 320 is stepped to the next frequency range. If signal is present, the base station 110 records the times t 15 1 ⁇ , ... t 10 of the next ten rising edges of 300 MHz signal.
  • a portable module 120 is assumed to be present, and the base station 110 goes to step 4. If not, the band pass filter is stepped to the next frequency step.
  • Step 4 The base station now sends a 24 bit command word to the portable module 120.
  • This command word will be passed over the serial bus 206 to access control chip 230.
  • the 24 bit word in hex is A00162. Since this is sent LSB first, the base station 110 transmission is as follows (where a write 0 command is represented by 10 pulses, and a write 1 is represented by 20 pulses): 10 pulses, q, 20 pulses, q, 10 pulses, q, 10 pulses, q, 2
  • Step 5 The access control chip 230 will now read out data for the next 64 clock cycles.
  • the data read out will be that in its ID field.
  • the base station 110 sends out 10 pulses, and then checks, 100 microsec later, for the presence of a 300 MHz signal. If the base station detects a 300 MHz signal at this instant, it infers that a "1" has been read out; otherwise the base station infers that a "0" has been read. This step is repeated for each of the 64 bits. Note that this readout scheme has the advantage that the timing of communication is entirely controlled by the base station. This provides additional noise margin. This also permits reliable communication even if significant clock inaccuracy exists in the micropowered portable module.
  • Step 6 Next (unless the base station rejects the identification data just received), the 64-bit password is sent to the portable module 120 as a series of write commands. Accordingly, the password data will be written to the access control chip 230. Step 7. The access control chip 230 will now read out 128 bits of data from its data field.
  • the base station 110 After receiving this data, the base station 110 can respond appropriately.
  • the base station may report the 64 bits of identification and 128 bits of data back to its host computer.
  • the host computer may then command the base station to initiate another transaction (such as a data write), or to reprogram the identification or password fields of the module, or to resume polling for other remote modules, or to initiate a physical action (such as unlocking a door).
  • a physical action such as unlocking a door.
  • the base station 110 may first send a "wake-up" or enable command, with a 16-bit chip-selection-tag and one additional byte of command parameters.
  • this may be a masked wakeup, so that the byte of command parameters will specify which fields are to be compared to the transmitted value.
  • this step is not used in the presently preferred embodiment, since the 16-bit cbip-selection-tag field is not used.
  • This wake-up or enable step may be repeated after scanning, if duty cycling is used to avoid the chance of missing a portable module which simply happened to be in the quiescent part of its duty cycle.
  • Receiver Chip 210 This integrated circuit in the portable data module performs the RF reception functions.
  • the receiver chip 210 is an ultra-low-power dual comparator circuit designed to listen for signals of up to 250 kHz. Input signals as small as 10 mV peak- to-peak will be amplified to provide full digital signals, at power supply levels, at the output.
  • a dual comparator arrangement is used, 'where an alternate antenna input is used if no signal is found on the primary antenna input. By using two orthogonal antennas, the risk of nulls or dead spots are eliminated.
  • the receiver chip 210 of the preferred embodiment can also be used advantageously in many systems other than the preferred system embodiment.
  • this integrated circuit can also be used as a front end for wireless communication links using infrared, ultrasonic, or magnetic field.
  • the ultra-low-power features of this integrated circuit are particularly advantageous in apphcations where a portable module must be permanently powered by an energy source capable of lasting over ten years.
  • the "freshness seal" logic which provides a zero-power sleep mode, is particularly advantageous in this respect.
  • the available duty cycle options can further reduce power consumption in special apphcations. Two alternative embodiments of this chip are specifically disclosed.
  • the first embodiment uses op amps for detection, and can detect RF voltages- as low as about 0.1 mV.
  • the second (and preferred) embodiment uses comparators rather than op amps, but requires a significantly higher RF signal for detection.
  • FIG. 4A shows a block diagram of the micropowered receiver chip 210.
  • Two comparators 420 are used to amplify analog inputs. Comparator 420A receives inputs A+/A-, and comparator 420B receives inputs B+ B-. Each comparator is followed by a one-shot 422, to ensure that the digital outputs have a certain minimum duration, and to guarantee that the output state will be zero if no input is present.
  • the comparators 420 are enabled, an AC input signal which exceeds 10 mV peak-to-peak will cause the comparator to change state at least twice per full cycle of the AC input signal.
  • the comparator output goes high, it will fire one-shot 422. This produces an output signal at full digital levels, with a certain minimum width per output pulse.
  • a duty cycle generator 430 generates periodic duty cycle waveform, for an on off ratio which can be programmed to be anywhere from 64/64 down to 1/64. (Whatever the ratio, the duration of the on- state is preferably at least 2 msec.)
  • the duty cycle generator is enabled or disabled by a laser fuse 432. (For clarity, the Figure shows this fuse as a simple series connection. However, in practice, this fuse is actually used to control a gate which provides the desired logic state.)
  • An enable input (El) can be driven by the data converter chip 220, to turn on the comparators 420 directly (if the freshness seal has been enabled). This input is particularly useful when the duty cycle feature is being used, since it permits the converter chip to override the duty cycle as soon as a data transaction begins.
  • comparator 420A While comparator 420A is active, it will provide digital outputs through OR gate 425, and AND gate 424 will cut off the output of comparator 420B. However, when no signal is detected at terminals A+/A- for at least three pulse periods, delay/integrator 423 will change state, enabling AND gate 424 to pass through the output from comparator 420B (and one-shot 422B).
  • the freshness input (FI) is used to seal or break receiver chip 210 power consumption activity. This input accepts 2 kHz pulse packets at a signal level greater than one Volt. When the seal is broken, comparators "A" and “B” continuously listen for activity at the inputs. When the seal is intact, no listening occurs and the receiver chip 210 enters a zero- power-consumption sleep mode.
  • FIG. 4B shows details of the bandpass filter preferably used in the freshness seal logic 410.
  • the input FI is connected to a first timing circuit 413, in which the time constant is determined by the RC time constant of a PMOS load element and a depletion capacitor.
  • the output of this stage is connected both to a counting chain 415 and to a second timing circuit 414.
  • the second timing circuit will add an additional time delay onto the delay of the first circuit, so that the output of the second circuit will have a lower cutoff frequency than will the output of the first timing circuit. If the second timing circuit is permitted to switch its output, it will reset the elements of the counting chain 415, and also block the outputs of the first timing circuit from clocking the counting chain 415.
  • Counting chain 415 is combined with additional flip-flops 416 as shown, to perform the freshness-seal filtering and decoding function as described.
  • the (optional) duty cycle generator 430 in the receiver chip 210 provides additional power savings.
  • Figure 4C shows the analog portions of an alternative embodiment 210' of the receiver chip 210.
  • This alternative embodiment does not have as low power consumption as the primary embodiment 210, but does have much higher sensitivity.
  • the first chain uses op amps 442 which have a relatively low slew rate, and require a relatively modest bias current. This chain monitors the 20 kHz wakeup frequency to detect wakeup signals.
  • the second chain uses op amps 444 which have significantly higher slew rates, and correspondingly higher bias current requirements. The slew rates and reactance values of this chain are chosen to permit detection of signals at the write-data frequency, which, in the presently preferred embodiment, is 200 kHz.
  • the first op amp chain when active, uses 1 to 2 microamps of bias current
  • the second op amp chain when active, uses about 200 microAmps.
  • Figure 4D shows further details of the configuration of a single amplifier stage 444 with constant-multipher-scaled arrays of feedback and series resistors.
  • the resistive elements 446' of the series resistor are scaled in powers of two, from a width/length ratio of 125 microns by 2 microns (nominal) up.
  • the resistive elements 446' of the feedback resistor are also scaled in powers of two, but begin with dimensions of 625/2.
  • the maximum value of the feedback resistance is five times as large as the maximum series resistance.
  • this arrangement permits .the resistance values to be "dialed in”: once the designer has an appropriately scaled 6-bit (in this example) digital value for the resistances, he simply specifies that the fuses 446" corresponding to each "1" bit of the resistance are to be blown.
  • the individual resistance elements 446' are polysilicon resistors, but of course a wide variety of other device technologies could be substituted.
  • Figure 4E shows further details of an active bandpass filter stage with constant-multipher-scaled arrays of capacitors and feedback resistors. In this drawing, each of the individual capacitor elements 448' has equal capacitance.
  • the individual capacitor elements 448' is a 30 micron square polysihcon-to-polysihcon capacitor, but of course a wide variety of other device technologies could be substituted.
  • the stage shown provides a one-pole bandpass filter function, and that selection of the values of the two capacitors 448 shown and of the feedback resistor 446 can select both the center frequency and Q of this active filter.
  • a bandpass filter stage is used, in combination with several op amp stages.
  • the bandpass filter stage has a Q of about 5, with minimal gain.
  • the individual op amp stages have respective gains of about 10, for a net total gain of about 10,000 at the center frequency.
  • the voltage gain V oa V m of the op amp stage will be equal to the ratio of the resistances -Rp R j ,., where the net resistance of the enabled elements of the feedback resistor is Rp, and the net resistance of the enabled elements of the input resistors is written as R ⁇ .
  • the presently preferred embodiment provides such digitally scaled values not only for resistors, but also for capacitors.
  • the trimmable resistors and capacitors are adjusted to set both the center frequency and Q of a bandpass filter.
  • the mathematical relations which define the center frequency and Q of a bandpass filter as a function of the component values used are very well known to those skilled in the art. However, the use of digitally scaled selectable components, so that the desired component values can be directly "dialed in" is believed to be new in the art.
  • the value of a thin film resistor can' be changed by changing the width/length ratio of a layer of a given sheet resistance, by changing the film thickness of a material of a given resistivity, by modifying the thin film layer so that it has a different sheet resistance (e.g. implanting it with a dopant), or by substituting a material with a different sheet resistance.
  • the preferred embodiment simply uses pattern modifications, to provide a variety of width/length ratios.
  • noise rejection can optionally be increased by increasing the Q of the (passive) antenna circuit, or by using a filter function which includes poles at two closely spaced frequencies within the passband, or by other passive filtering options well known to those skilled in the art.
  • This integrated circuit in the portable data module 120, performs the function of 2-wire to 3-wire conversion.
  • the one-wire bus 215 provides pulse bursts as inputs to converter chip 220.
  • This one-wire bus 215, together with the transmitter control output from the converter chip 220, may be regarded as a two-wire bidirectional bus.
  • Converter chip 220 decodes these pulse bursts, and drives serial bus 206 accordingly.
  • the converter chip 220 is a low-power CMOS integrated circuit which accepts pulse packets at the input, and interprets these signals to control bidirectional data transfer on a 3 wire serial bus 206.
  • the converter chip 220 also controls an output pin RFOUT, which is switched, when data is being read from the serial bus 206, in accordance with the data seen.
  • This output pin is preferably used to control a simple VHF/UHF transmitter 240, but alternatively the RFOUT signal can be connected to gate a variety of transmitting devices.
  • the touch-contact port 270 can be connected, as a bidirectional interface, so that the converter chip 220 both receives 100 kHz pulse packets from port 270 (instead of from receiver chip 210), and also returns data to port 270 (instead of keying the transmitter 240).
  • the converter chip 220 also provides stretched clock and DQ signals. These signals facilitate synchronization to work with a microprocessor.
  • the detailed circuit implementation described below contains features which support various of the alternative embodiments discussed. However, it should be realized that these features can be omitted if desired, and in fact several of the disclosed features are not used in the preferred embodiment as presently practiced (although it is contemplated that it will be desirable to restore these features in future versions, at least for some apphcations).
  • a set of five commands is used, as detailed above.
  • the pulse streams on the one-wire bus 215 (which are extracted by receiver chip 210 from the variable-length pulses on the 200 kHz RF channel, or are directly connected in from the touch- contact port 270) are counted. The count values are divided into classes by five boundary values Bl, B2, B3, B4, and B5.
  • boundary values B1-B5 are set at 5, 15, 25, 35, and 45, and the numbers of pulses sent by the base unit to transmit symbols A through E are 10, 20, 30, 40, and 50 respectively.
  • the boundary values B1-B5 are independently selectable, by laser trimming, in the range from 0 to 255.
  • noise margins allow, these numbers can be decreased to decrease transmit time.
  • boundary values B1-B5 are set at 3, 9, 15, 21, and 27, and the numbers of pulses sent by the base unit to transmit symbols A through E are 6, 12, 18, 24, and 30 respectively, the gross data rate would increase by two-thirds, if the error rate did not increase.
  • these boundary values B1-B5 can be increased.
  • a state diagram of the converter chip 220 is shown in Figure 5G. This shows how the converter chip 220 will react to all possible pulse train sequences on the one-wire bus 215. This diagram can be explained in three divisions.
  • the first division is the inactive state (represented as 000).
  • the converter chip 220 drives lines RST*, DQ, and CLK (of the serial bus 206) low, and turns off the 300 MHz oscillator 240 (except when arriving at state 000 from Beacon state 011).
  • Pulse classes E and F 45 pulses or more, and inactivity for 2 msec will always send the converter chip 220 to this state. (These pulse classes are also represented as "tl500” and "t200P" in the wiring diagrams shown.)
  • the second division is the active state 100.
  • the converter chip 220 drives the RST* line high, pulses the CLK line, and drives data onto the DQ line (or loads data from the DQ line, depending on whether data is being read from or written to access control chip 230).
  • the converter chip 220 will also turn on the 300 MHz transmitter 240 whenever a 1 is read out from the access control chip 230.
  • the third division includes states 001. 010. and 011.
  • a sequence of pulse classes DAB received by the converter chip 220 when it is in die inactive state 000 will put it into the first beacon state.
  • the converter chip 220 will pulse the 300 MHz oscillator on and off at a 5 kHz rate (laser programmable to 2.5 kHz, 10 kHz, 20 kHz, and 40 kHz).
  • the pulsing will terminate in 200 msec or upon reaching active state 100.
  • This beacon permits the base station's 300 MHz receiver to differentiate a valid key from background noise, when it is scanning the frequency range of 285-315 MHz looking for a key.
  • pulse groups A, B, and C (corresponding to internal signals t50, tlOO, and tl50 respectively) will keep the converter chip 220 in this state. It is in this state that reading and writing of the access control chip 230 occurs. Following are the actions caused by the pulse groups A, B, and C when the converter chip 220 is in the active state 100.
  • a number of pulses C will cause the converter chip 220 to drive RST* low and then high, terminating any conversation with the access control chip 230 and initializing the access control chip 230 for the start of a new conversation.
  • a number of pulses B will keep RST* high while driving DQ and CLK so as to write a 1 to the key.
  • the converter chip 220 will not turn on the 300 MHz transmitter, even though the access control chip 230
  • a number of pulses A will keep RST* high while driving DQ and CLK so as to write a 0, or read data, from the access control chip 230.
  • the combination of the write-0 and read functions decreases circuit complexity and increases the speed of communication.
  • the presently preferred embodiment makes the pull down strength of converter chip 220 much less than the pull up strength of access control chip 230. If the access control chip 230 is expecting to be written to, it does not drive the DQ line, so that the converter chip 220 can drive the DQ line. If the access control chip 230 is being read from, it will drive the DQ line with data while CLK is low.
  • the waveforms are identical to those above, since the converter chip 220 and access control chip 230 both drive DQ to ground. However, if a "1" is read from the access control chip 230 the converter chip 220 and access control chip 230 will contend when CLK is low, with the access control chip 230 winning. Note that out of all three cases of Write 0, Read 0, and Read 1, the only time DQ went high while CLK was low was during the Read 1. If DQ goes high while CLK is low, the 300 MHz transmitter 240 is turned on, sending a 1 to the base station 110. The 300 MHz transmitter 240 will turn itself off after about 150 microseconds. In an alternative embodiment, the transmitter 240 will also be turned off by the fourth rising edge of the 200 kHz signal presented to the converter chip 220. Following are descriptions of some of the pin connections and signal names used in the presently preferred embodiment of this chip:
  • V g ⁇ This input is designed to be connected to a lithium battery with a voltage range between 2.5 and 4 volts.
  • the converter chip 220 acts as a battery operated device, and power is supplied from the V BAT pin at all times.
  • the V BAT input should be grounded if not used.
  • VCCI This input is designed to be connected to a power supply with a voltage range of 4.5 to 5.5 volts. This voltage input is switched to the VCCO pin as long as VCCI is greater than V ⁇ - j . However, when V BAT is the greater, its voltage will be present at VCCO. When both VCCI and V BA ⁇ inputs are used, the converter chip 220 is in the battery operate mode until VCCI becomes greater than V BA ⁇ VCCI should be grounded when not being used.
  • VCCO This is a switched output, which will always be the greater of V ⁇ - or VCCL jjgp.: This output pin represents the battery voltage input Vg ⁇ j .) less 0.6 Volts. It is designed to be connected to the battery input pin on the access control chip 230, or to such additional chips as a DS1207 TimeKey (TM) or DS1207 Electronic Tag.
  • This input/output pin provides an override for standard
  • the port pin acts as an input pin for 100 kHz pulse packets containing both command and data input to the 3 wire serial port. Data is also output on the same pin when memory content is read via the 3 wire serial port.
  • STDO This output (stretched data) contains the same data as the serial port DQ pin. The difference is that the data output remains valid until the STCLK is transitioned high via an external source.
  • STCLK This input/output (stretched clock) contains the same clock output as the serial port CLK pin. This pin differs in that an external source is required to drive the STCLK pin high after the converter chip 220 has asserted it high.
  • IN This input accepts the 200 kHz pulse packets. In typical apphcations this pin is connected to the signal output pin of the receiver chip 210.
  • This output pin is active high when the protocol shift register has received a command (including an appropriate match in the 16-bit cbip-selection-tag field) to "wake-up." In a typical application this pin is connected to the enable pin El of the receiver chip 210. In the embodiments where the duty cycle option of the receiver chip 210 is used for power conservation, this connection can be used to hold the receiver chip 210 on.
  • the duty-cycle control logic (as will be discussed below) holds the receiver chip 210 active, during each active cycle, for at least long enough for the converter chip 220 to receive an enable command and activate this connection. This assures that, even in the maximum- efficiency duty cycle mode, it will be possible to detect an enable pulse and wake-up.
  • TRI This input is used to tristate outputs CLK, RST*, and DQ.
  • the TRI pin is active in high state.
  • DOTRP This input is used to tristate the DQ pin only.
  • the DQTRI pin is active in the low state.
  • OUT The OUT pin carries the data which is output from the
  • this pin is used to key the RF transmitter which will send data back to a base station 110 via a 300 MHz loop.
  • RST* This output signal is the reset-bar signal for the 3 wire serial bus 206.
  • RST* When RST* is at high level, the 3 wire port is active, and data can be written into or read from the serial bus.
  • FIG. 5D shows a high-level overview of an alternative embodiment of the converter chip 220. This embodiment differs from the embodiment of Figure 5A in two major respects:
  • Figure 5A in having the ability to enter (and awaken from) a sleep mode.
  • a corresponding hardware difference is that this alternative embodiment has a protocol register 554.
  • the input select logic 506 selects between inputs from the data line of one-wire bus 215 and port 270. (Note that this logic can also divert the output of the beacon control logic 556 to provide an output to port 270 instead of to the transmitter 240.)
  • the pulses from the selected input are provided to pulse counter 530, where they are deciphered into various action codes which affect the protocol shift register, the state machine, and ultimately the 3 wire serial bus 206.
  • the pulse packets received by the pulse counter 530 will have approximately a square-wave shape at 200 kHz, with a 50 microsec dead time after the last pulse in each packet
  • the pulse counter logic 530 watches for such dead time intervals, and then assesses the count value to determine what action to be taken, in accordance with the threshold values B1-B5.
  • the converter chip 220 will time-out, reset the protocol shift register 554, and place the state machine 552 into an inactive state.
  • a signal is incoming from the touch-contact port 270, the operation of the converter chip 220 is modified slightly. Due to the lower frequency used for communication over the port 270, all time windows are doubled (except that the limit for timeout is kept at 2000 microseconds). If a read pulse packet is detected, time is allotted beyond the 100 microsec between pulse packets for the converter chip 220 to send out a one or a zero. This time is specified as a 400 microsec window. If a logic "0" is being sent, the port line will remain low for the entire window. If a logic "1" is being sent, the port line will be driven high within a maximum of 150 microsec. The port line is guaranteed to be inactive after a third 150 microsec time period.
  • the pulse counter 530 will direct the interpretation of each packet of input pulses to one of two circuits. If a pulse packet of more than 44 pulses (e. a "50-pulse" packet) arrives at the pulse counter 530, the next 24 pulse packets- are sent to the protocol shift register 554, and the state machine 552 is set inactive. .(Thus, a 50-pulse packet always sets the state machine to inactive, regardless of any action which may have been occurring.
  • This packet can be used to abort a current ac ⁇ tion/conversation.
  • the 24 pulse packets following a 50-pulse packet which are routed to the protocol shift register 554, can command a normal wakeup, a masked wakeup, a read of the chip-select bits, a write of the chip-select bits, or a lock of the chip-select bits.
  • the chip-select bits (in an incoming command) are the first 16 bits of the 24-bit protocol shift register 554. The last eight bits are the function field.
  • the state machine 552 which implements a state diagram as described above, receives inputs from the protocol shift register and also from the pulse counter 530. The outputs of the state machine control the three lines RST*, D/Q, and CLK of the serial bus 206. Another output of the state machine 556 also activates the beacon control logic 556, which provides outputs to the transmitter 240 and to the multiplexer (input select logic) 506. The state machine 552 can also use the D/Q line as an input
  • the D/Q and CLK lines are also connected to stretch circuit 558, which generates STDQ and STCLK signals as described above.
  • the STCLK and STDQ pins are similar to the CLK and DQ lines: when CLK goes low, the STCLK line is also pulled low by the converter chip 220. This signal tells a monitoring device (such as a microprocessor) that the STDQ pin contains data, and that this data matches the data on the normal DQ pin. When the normal CLK goes high, however, STCLK and STDQ both remain valid. This allows time for a monitoring device to capture the data. Once the monitoring device retrieves data, the STCLK signal must be forced to a high level externally. In this manner the monitoring device will terminate the cycle, and the STDQ line will go to high impedance.
  • a power switching circuit 510 selects between alternative power supply inputs V BAT and VCCI, to supply the internal power supply V DD and a supply voltage output VCCO.
  • This circuit also supplies a lowered supply voltage output VR ⁇ J , which provides power to certain downstream chips as discussed above. (The use of this reduced-voltage output means that, when the converter chip 220 drives the RST* line to full supply voltage, the downstream chips which use the V REF output for their battery supply voltages will see an RST* voltage which is higher than their supply voltages.)
  • Figures 5A-5C show a much more detailed circuit diagram. Note that the protocol shift register 554, state machine 552, stretch circuit 558, and beacon control logic 556 are all shown implemented as control logic 550 in Figure 5A.
  • Input buffers 502 receive incoming signals 507, 20KP (used, in alternative embodiments, to indicate that the receiver chip 210 is receiving a signal on the wakeup frequency), DQ, DQOE, and TRIWIR.
  • Output buffers 504 buffer output signals DQ, CLK, and EN.
  • Counter logic 530 receives the data from line 507 (which will usually be connected to the data line of the bus 215), and also receives the 20KP signal (which indicates when the currently incoming data was received on the wakeup frequency rather than the write-data frequency).
  • the incoming digital pulses are expected to have symmetrical high and low durations of about 2.5 microsec ( ⁇ 20%).
  • the minimum quiet time required for the converter chip 220 to recognize the end of one pulse packet and the beginning of another is 50 microsec. Conversely, if another pulse occurs after less than 10 microseconds of quiet, this pulse can be recognized as a continuation of the previous packet. If an idle period (with no pulses) of 2.0 msec occurs, the protocol shift register 554 will initialize and the state machine will go inactive. Quiet intervals of about 100 nsec or less may not even be noticed by the converter chip 220. Pulse packets range from 10 pulses to 50 pulses, depending on the action to be taken.
  • a read pulse packet If a read pulse packet is detected, data is to be read from a device connected on the 3 wire serial bus 206, and the output pin will become active high for a logic one or remain low for a zero. Time is allotted beyond the 50 microsec between pulse packets for the converter chip 220 to send out a one or a zero. This time is specified as a 225 microsec window. If a logic "1" is being sent, the out pin will be driven to high level within a maximum of 75 microsec and will remain high for a minimum of an additional 75 microsec. However, if a minimum of four 200 kHz pulses are received at the 200 kHz input, the RFOUT pin activity is terminated on the assumption that a logic one has been received and the sending unit has started the next pulse packet.
  • the RFOUT pin is guaranteed to be inactive after a third 75 microsec time period.
  • counter logic 530 detects a gap of 50 microseconds or more, which would indicates the end of a pulse packet, the counter 530 drives a data-valid line DV, compares the current count value against various threshold values, and updates the threshold output lines 531.
  • lines 531 are not simply counter output bits, but represent the results of multiple comparison tests.
  • the boundary values B1-B5 are separately laser-programmable, and the lines 531 represent the separate logical results of magnitude comparisons between each of these boundary values and the count value for the latest completed pulse packet.
  • the counter 530 also provides another output (not shown), indicating that a quiet delay long enough to cause timeout (set to 2 msec, in the presently preferred embodiment) has been detected.
  • Wakeup logic 520 receives the highest bit of the comparison bits 531, and also receives the signal 20KP to detect activity on the wakeup frequency. Wakeup logic 520 performs the wakeup-frequency decoding mentioned above. This capabihty is used in the alternative embodiment which uses the more sensitive receiver chip 210' of Figure 4C, with signalling on a lower wakeup frequency used to initiate all transactions.
  • signals received on the wakeup frequency are amplified by receiver chip 210, to provide pulse bursts on the one-wire bus 215.
  • Converter chip 220 counts pulses in the pulse trains of the wakeup-frequency signal, hi a manner which is analogous to its operation for pulse trains received on the write-data frequency. (However, note that, when the pulse packets are derived from a wakeup signal, the individual pulses will have a high-state duration which is equal to half the period of the RF carrier at the wakeup frequency, instead of half the period of the RF carrier at the write-data frequency.)
  • the converter chip 220 counts these pulses, and measures them against a pulse count boundary B0. A stream which has fewer pulses than B0 is considered a "0", while greater than or equal to B0 pulses is considered a "1".
  • the value of B0 (like that of boundary values B1-B5 discussed below) is laser trimmable from 0 to 255. If no laser trim is used, B0 will • be equal to 20. In the present system, 10 pulses will be used to send a 0, and 30 pulses to send a 1 with B0 set at 20. (Optionally, if noise and error margins allow, these numbers can be decreased to decrease transmit time.)
  • the converter chip 220 looks at a moving window of bits received at 20 kHz as described above. When the last bit of a pattern B9 (10111001) is received, the converter chip 220 will enable the 200 kHz receiver of the receiver chip 210.
  • the converter chip 220 When the last bit of a pattern 6D(01101101) is received, the converter chip 220 will disable the 200 kHz receiver of the receiver chip 210. If no 20 kHz or 200 kHz signal is received by the converter chip 220 for at least 2 msec, the converter chip will disable the 200 kHz receive operation.
  • FIG. 5B shows details of the power switching circuit 510. Note that this circuit can actually accommodate two system supply voltage inputs VCCI, in addition to the battery voltage input V BAT . Comparator 512A tests supply voltage input VCCI 1? to see whether it is greater than the battery voltage V BAT . Comparator 512B tests supply voltage input VCCI 2 , to see whether it is greater than the battery voltage V BAT .
  • the large switching transistors 513 are controlled in accordance with the logical outputs of these comparators:
  • voltage VCCI 2 is greater than the battery voltage V BAT , then the on-chip supply voltage V DD and the supply voltage output VCCO will both be connected to VCCI 2 and disconnected from VCCI j and V BAT . If voltage VCCI j is greater than the battery voltage V BAT AND voltage VCCI 2 is NOT greater than the battery voltage V BA ⁇ , then the on- chip supply voltage V DD and the supply voltage output VCCO will both be connected to VCC ⁇ and disconnected from VCCI 2 and V BAT .
  • the capabihty to use two alternative power supply inputs helps to allow system flexibility. Moreover, this is a desirable safety feature, since it helps to minimize the risk of cross-connection of separate power supply sources (which could cause damaging high currents), without wasting power in diode drops.
  • the reduced-voltage output supply ⁇ tEF is generated by one or two bipolar transistors 511. (The second transistor is connectable, by a laser option, to provide a Darlington pair.) As noted above, this provides a V jj ⁇ p output which is about one diode drop (or two, depending on the laser option just mentioned) below the on-chip supply.
  • the control signal to switch power supply sources is first tied to the gate of the the device which switches in the battery. If VCCI is less than V BAr , the battery wfll not be charged. If VCCI is greater than V BAr , the gate of the battery-switching device will be high. If a failure occurs, so that the gate of the battery-switching device goes low, the resulting voltages will ripple through the circuit to the V cc -switching device, and turn it off.
  • the converter chip 220 in the presently preferred embodiment, can work off of a battery supply as low as 2.5 volts. However, if an alternative supply is available, it can be connected to the VCG ⁇ or VCCI 2 inputs. (To avoid disturbing the switching transistors 513, any unused supply input VCCI should preferably be grounded.)
  • Figure 5C shows the presently preferred embodiment of the state machine 552. Note that three outputs of the state machine control the bus 206. (Three other lines are assigned to receive signals from the serial bus 206.)
  • the RST* pin on the serial bus 206 is driven high whenever a 30-pulse packet is received by the state machine.
  • the RST* signal remains high until a 40- or 50-pulse packet is received, or until 2.0 msec has elapsed without activity at the 200 kHz input.
  • the CLK pin on the converter chip 220 is normally low, and will remain low until the RST* signal goes high.
  • the CLK pin When RST* goes high, and a 10- or 20-pulse packet is received by the state machine (indicating a "read from” or “write to” the 3 wire port), the CLK pin is driven low for a period of 500 nsec minimum to 1 microsec maximum. If data is being read from a device on the 3 wire serial port, it will become vahd within 200 nsec of the falling edge of the clock, and remain vahd until the clock returns high. This data is transferred to the RFOUT pin after a time delay of 75 microsec maximum. The output will be a high level for a logic ohe or remain at low level for a logic zero.
  • the state machine includes three flip-flops 560, which implement the 8-state diagram of Figure 5G. Note that inputs on lines E or F (signals t200p and tl500) reset the flip-flops 560, and all other inputs clock the flip-flops. Reset logic 562 generates an output signal on line RST* (of bus 206) under the appropriate conditions. Two one-shots are also provided, to drive pulses, under the appropriate conditions, onto lines CLK and DQ of bus 206. Figure 5E shows the timing relations used, in the presently preferred embodiment, to implement the pulse counter 530.
  • a rising pulse edge (of the pulses derived from the one-wire bus 215) resets the counter (at the time shown as t E1 ), and causes a decode enable signal to go low.
  • the decode enable signal is again brought high. .(The delay t DELAY provides setup time, so that the count value, which has been vahd since the rising edge of the last pulse, can ripple through the magnitude comparators.)
  • the decode enable signal wfll again go low.
  • Figure 5F shows the magnitude comparator which is preferably used in the pulse counter 530, to rapidly threshold the pulse-count values against the preset thresholds. Note that this is a ripple-through architecture, where the highest boundary values are tested first.
  • the small cell which is used at each stage provides both "greater than” and "equal to x" outputs. Only three stages are shown, although eight stages are used in the presently preferred embodiment (and of course more or fewer stages could be used instead).
  • Figure 8 shows how the converter chip, in the presently preferred embodiment, controls its power-supply output line to help other chips receive data from the serial bus. Note how the V ⁇ p output is driven opposite to the RST* signal.
  • the protocol register is always loaded by sending write zeroes (10-pulse packets) or write ones (20-pulse packets).
  • the loaded pulse packets are compared to values stored in the 8 bit function Code Table and the previously stored 16 chip-select bits (storing the chip-select values will be covered later).
  • the first entered bits LSBs
  • Bits 0 and l wfll be the only bits unmasked if "mask 2-15" is selected. Pulse packets of 25 to 44 pulses are ignored when loading the protocol shift register 554.
  • a pulse packet of greater than 45 pulses always initializes the protocol shift register 554 back to starting with the LSB and aborts any previous transaction.
  • the state machine is also set inactive. After the first 24 bits are received and a vahd wakeup is decoded, the protocol shift register 554 will no longer allow data bits to be written into it and the enable output will become active and remain active until another 50-pulse packet is received to reinitialize. Subsequent pulse packets which are - received will be directed to the state machine with action taken corresponding to the number of pulses received as shown in Table 1.
  • a pulse packet train of 40-pulse packet, followed by a 20-pulse packed, followed by a 10-pulse packet enables the beacon mode of the state machine.
  • Beacon mode turns on and off the out pin at a 5 kHz rate for 100 msec.
  • This signal can be used (for example) to key a transmitter, which allows a base station 110 to lock onto the transmitted beacon.
  • the converter chip 220 is now put into the active state by issuing a 3G-pu_.se packet which takes RST* high on the 3 wire serial port. This same 30-pulse packet also turns off the beacon if it has not already timed out With reset high a conversation can now take place between devices placed on the 3 wire port (such as Access control chips 230, memory controller chips 260, or such other circuits as a DS1207 TimeKey
  • TM Electronic Tag
  • the converter chip 220 will time out, initialize the protocol shift register 554, and set the state machine back to the inactive state.
  • the converter chip 220 now waits for new 200 kHz inputs to the protocol serial shift register which begins with a 50-pulse packet.
  • the 16 bit CS value stored in the protocol shift register 554 can be determined in several ways. In fact, an exhaustive search could be implemented with a trial and error method which would eventually eliminate all but the correct bit pattern. Obviously, this method is painfuUy slow as 2 16 possible combinations may need to be tried. In a similar but much more expedient manner, mask bits can be used in a successive approximation manner to determine the value of the CS bits. This procedure is accomplished by gradually increasing the size of the unmasked chip-select fields as each set of bits are identified. However, the simplest method of detemnning the 16 bit CS value is to read the 16 bit value directly. The following step by step procedure will illustrate how to read the chip-select bits. 1.
  • Wakeup the converter chip 220 using the mask-all function code This is accomplished by sending a 50-pulse packet followed by 24 10-pulse and 20-pulse packets. In the protocol used, the least significant bits are transmitted first. The command format preferably used therefore transmits the command code for the desired action first Thus, in this example, the first 8 pulse packets must match the mask-all function code.
  • the next 16 packets, which are the chip-select field, may be any combination of 10- and 20-pulse packets (since the 16 CS bits are masked).
  • the beacon mode of the state machine is enabled by sending a 40-pulse packet followed by a 10-pulse packet followed by a 20- pulse packet.
  • the beacon mode must be enabled when using an RF link with a scanning receiver, as the beacon will allow the receiver to lock on to the transmitter frequency. If the port pin is used directly or if the out pin is read directly or indirectly by a non-scanning device, this step can be ' omitted. Finally, if the beacon mode has been enabled, it should be disabled after receiver lock on by sending a 30-pulse packet to the IN pin.
  • the converter chip 220 will start over again reading the CS bits, beginning with the first bit. Pulse packets of 20, 30, or 40 pulses are ignored, and 50-pulse packets will initialize the protocol shift register 554 and set the state machine inactive. 4. During the entire CS bit read operation, the state machine is disabled. All pulse packets except the 50-pulse packet are ignored. As usual, the 50-pulse packet or a time-out of 2.0 msec will initialize the protocol shift register 554 and return the state machine to inactive.
  • the converter chip 220 does not lock up after 16 pulse packets are sent in this mode. If more packets are sent, the new packets whl continue to shift in, storing the last 16 packets that are received.
  • the design of the converter chip 220 allows for both battery backup and battery operation.
  • the device also consumes only modest amounts of power.
  • most apphcations for this device are permanently powered and memory elements within the device, like the protocol shift register 554 CS bits, are nonvolatile.
  • a special latch is provided so that upon initial power up (when battery is first connected) the nonvolatile chip-select bits can be written with a store CS function code.
  • the CS bits can be changed as often as desired, using the store function until a lock
  • the lock CS bit can be accomplished by the following step by step procedure.
  • the 8 bit function code for locking the CS bits is then transmitted, followed by the 16 bit chip-select value, using 10- and 20-pulse packets. Only 10- and 20-pulse packets are accepted, and 30- and 40- pulse packets are ignored. A 50-pulse packet whl cause the lock CS bits to abort, initializing the protocol shift register 554 and returning the state machine to the inactive state.
  • the latch is set automatically and no further action is required. 4. The only way the latch can be reset is to remove power (the battery) from the device. During the lock-CS operation the main state machine is disabled, so that ah pulse packets have no effect on the state machine. As usual, a 50-pulse packet or a time-out of 2.0 msec will initialize the protocol shift register 554 and return the state machine to inactive.
  • the presently preferred embodiment does not include any automatic gain control circuits (AGC) stages, although these are frequently used, and recognized as being usefiil, in RF communication systems.
  • AGC automatic gain control circuits
  • NormaUy AGC is implemented using analog amplification stages, which are controlled by feedback to reduce their gain when large incoming signals are overloading subsequent circuits.
  • the micropowered receiver circuits of the presently preferred embodiment do not use any analog amplification, since such circuits tend to consume power.
  • an alternative embodiment shown in Figure 4F, uses a digitally controlled automatic gain control, which does not consume any additional power. This is very advantageous, since it reduces the risk of short-range RF communications being disrupted in high-noise environments, or in environments where a remote module can hear multiple base stations.
  • the counter 530 when the counter 530 receives an extremely long pulse train it simply saturates at its maximum count value (255 in this embodiment). However, in this alternative embodiment, the counter 530 provides an overflow-indicating pulse to a current-source- control counter 470. This current-source-control counter provides control signals to a spht current source in the comparators 420 at the input to the receiver circuits.
  • the current source in the input comparators in the receiver circuits is the primary location of standby power dissipation in the presently preferred embodiment. Therefore, the size of this current source is a critical parameter in designing the remote module: if the comparators are redesigned to draw more current, the sensitivity of the receiver circuits will be increased, but the battery lifetime will be decreased. Thus, in the presently preferred embodiment (using a 190 mA-hour battery), the current sources have been designed for the maximum current draw which can reliably be accommodated by the battery lifetime. (As mentioned above, this current draw is a few microAmps total.) In the presently preferred embodiment, these current sources are conventionally configured using a CMOS current mirror circuit which controls an NMOS driver (current source) device.
  • the channel width of the current source device is divided up between several devices in parallel. For example, where the maximum device width is W, this device width can be allocated into four parallel current-source devices 461 having widths of W/15, 2W/15, 4W/15, and
  • this embodiment provides a significantly different current source for the comparators 420.
  • the individual driver elements are each driven by the voltage output of a current-mirror circuit 465, just as the single driver element is in the current source of the primary embodiment.
  • a switching transistor 463 is placed in series with each of these current- source devices 461, and a four-bit down counter 470 is used as the current-source-control counter.
  • the four output bit lines 472 of the current-source-control counter 470 are each connected to one of these switching transistors, to control one of the current-source devices.
  • the current source device sizes are chosen so that the maximum current into the comparator is about 1.5 microAmps.
  • the multiplier defined by the ratio of the current-source device to the pull-down device in the current mirror, will be changed (as is well known to those skilled in the art of MOS circuit design) as the separate branches of the current-source device are switched in or out.
  • the input side of the current mirror receives a current of one microAmpere, and drives this current through an NMOS device which is 5 microns wide and has its gate tied to its drain, the gate of this device can be connected to control the gate of a following NMOS device (with the same threshold voltage, gate oxide thickness, etc.). which will provide a current source.
  • the voltage from the input side of the current mirror can be used to control as many NMOS devices in parallel as desired.
  • Each of these NMOS devices will source a current (into sufficiently low impedance) of 1 microAmpere times its width (in microns) divided by 5.
  • the current-source-control counter is decremented, and the total channel width of the current sources in the input comparators 420 of the receiver circuits is reduced. This reduces the sensitivity of the comparators. Pulse counting continues, and if saturation occurs again the receiver sensitivity is decremented again.
  • a further feature of this embodiment is the use of a slow timer circuit to recover from saturation.
  • a simple RC timing circuit 474 with a long time constant e.g. 1 to 10 seconds is used to periodically reset the current-source-control counter. This assures that the portable module will be able to rapidly recover from saturation.
  • this embodiment requires at least one additional control line between the circuits which are now on the converter chip 220 and the circuits which are now on the receiver chip 210.
  • This line can be added into these chip designs if needed, or alternatively the receiver .and converter chips can be combined.
  • two stages of gain reduction are used when saturation occurs. First, as just discussed, the receiver gain is decremented whenever the pulse counter saturates. However, after such decrement operations have reduced the gain so that the system is not overwhelmingly saturated, an additional small decrement is performed to optimize reception.
  • This intermediate value would be chosen to reveal saturation problems - for example, it might be set slightly higher than the length which would be seen if the intersymbol separation for the longest legal two-symbol sequence were missed.
  • a further alternative way to implement the digital AGC function is using transistors to selectably switch out individual elements of a resistor ladder.
  • a constant current source is used for the comparator, instead of the adjustable current source just described.
  • Gain control is performed by dynamically scaling the RF input voltage, using a digital feedback circuit as described above.
  • the input A+ would not be connected directly to the + input of the comparator 420A, but instead would be connected through a high-impedance resistor ladder to the - input of the comparator 420A A third terminal on this resistor ladder (i.e.
  • a "wiper" terminal would be connected to the + input of the comparator 420A
  • the counter outputs would be connected to control transistors which switch the individual elements of the resistor ladder in or out.
  • two resistor arrays would be used, one between the A+ input and the + terminal of the comparator, and one between the comparator's + and - terminals.
  • the digital inputs would each be connected to two pass transistors.
  • This embodiment is illustrated in Figure 4G. Note that the values of the resistor elements are scaled in multiples of 1.5, rather than in multiples of two.
  • the total value of the resistance between A+ and A- is large enough not to greatly degrade the Q of the circuit; for example, a resistance
  • the embodiment of Figure 4G may be advantageous in providing a wider range of gain control. Since the gain of the comparator varies as the square root of the bias current, the current sources might have to be scaled over a wider range than is practical to achieve the desired sensitivity range.
  • This integrated circuit in the portable data module, implements addressing and security controls.
  • the access control chip 230 in the presently preferred embodiment, is a miniature security system which stores 64 bits of user definable identification code and a 64 bit password which protects 128 bits of read write nonvolatile memory. This security subsystem enables the access control chip 230 to act, in effect, as an electronic key.
  • the 64-bit identification code and the password are programmed into the access control chip 230 via a special program mode operation. After programming, the access control chip 230 follows a special procedure with a serial format to retrieve or update data. Interface cost to a microprocessor is minimised by on-chip circuitry which permits data transfer with only three signals: CLK (clock), RST* (reset complemented), and DQ (data input or output).
  • the access control chip 230 has two modes of operation: the normal mode and the program mode.
  • the block diagram ( Figure 6A) illustrates the main elements of the access control chip 230 when used in the normal mode.
  • RST* is taken high and 24 bits are loaded into the command register on each low to high transition of the CLK input.
  • the command register must match the exact bit pattern which defines normal operation for read or write or communications is ignored.
  • K the command register is loaded properly, communications are allowed to continue.
  • the next 64 cycles to the access control chip 230 are read. Data is clocked out of the access control chip 230 on the high to low transition of the clock from the identification memory. Next, 64 write cycles must be written to the compare register. These 64 bits must match the exact pattern stored in the security match memory.
  • FIG. 6B is a flow chart of the normal mode sequence.
  • FIG. 6C illustrates the main elements of the access control chip 230 when used in the program mode. Note that, preferably, any change of password will cause the data memory to be wiped. This enhances data security.
  • RST* is driven high and 24 bits are loaded into the command register on each low to high transition of the CLK input.
  • the command register must match the exact pattern which defines program operation. If an exact match is not found, the remainder of the program cycle is ignored. If the command register is properly loaded, the entire RAM (ah 256 bits) is pulsed to all zeros. The next 128 bits received are written to the identification memory and the password memory.
  • Figure 6D is a flow chart of program mode operation.
  • Each data transfer for the normal and program mode begins with a three byte command word.
  • the first byte of the command word specifies whether the 128 bit nonvolatile memory will be written into or read. If any of the bits of the first byte of the command word fails to meet the exact pattern of read or write, the data transfer will be aborted.
  • the 8 bit pattern for read is "01100010" (binary).
  • the pattern for write is "10011101" (binary).
  • the first two bits of the second byte of the command word specify whether the data transfer to follow is a program or normal cycle.
  • the bit pattern for program is 0 in bit 0 and 1 in bit 1.
  • the program mode can be selected only when the first byte of the command word specifies a write. If the program mode is specified and the first byte of the command word does not specify a write, data transfer will be aborted.
  • the bit pattern which selects the normal mode of operation is 1 in bit 0 and 0 in bit 1. The other two possible combinations for the first two bits of byte 2 will cause data transfer to abort.
  • each respective code pattern must be written exactly for a given device, or data transfer will abort.
  • the bit pattern as defined by the user must be written exactly or data transfer will abort.
  • the last bit of byte 3 of the command word must be written to logic 1 or data transfer will abort.
  • Ah data transfers are initiated by driving the RST* input high.
  • the RST* input serves three functions. First, it turns on control logic which allows access to the command register for the command sequence. Second, the RST* signal provides a power source for the cycle to follow. To meet this requirement, a drive source for RST* of 2 mA at 3 Volts is required. However, if the V cc pin is connected to a 5 Volt supply which is within nominal limits, then RST* is not used as a source of power. In this case, input levels will revert to normal inputs with a drive current requirement of 500 microA Third, the RST* signal provides a method of terminating data transfer.
  • a clock cycle is a sequence of a falling edge followed by a rising edge.
  • the data For data inputs, the data must be vahd during the rising edge of a clock cycle.
  • Command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock.
  • Ah data transfer terminates if the RST* pin is low and the DQ pin goes to a high impedance state.
  • the transition of RST* must occur while the clock is at high level, to avoid disturbing the last bit of data.
  • Figure 2D shows how the memory controller chip 260 is used in an alternative embodiment of the portable module 120.
  • the memory controller chip has capabilities which can be useful in a wide variety of embodiments, including system embodiments which are not closely analogous to that shown in Figure 2D.
  • the architecture and operation of this integrated circuit will now be described in detail.
  • the memory controller 260 is a dual-port memory controller, which permits three-wire serial port to interface to a bank of one or more byte wide static RAMs 262, yet maintains the existing byte wide port.
  • Memory address space in the presently preferred embodiment, of up to 512K can be addressed directly.
  • a single controller 260 in the presently preferred embodiment, can provide dual-port interface to a bank of 512 kbytes of memory, eg. 16 32K-by-8 SRAMs.
  • Arbitration between the serial and byte wide port is accomplished either by handshaking or by using predictable idle time as an access window.
  • the serial port requires a six byte protocol to set up memory transfers. Cyclic Redundancy Check circuitry is included to monitor serial data transmission for error.
  • the disclosed architecture can readily be modified for use with by-9, by-4, by-16, or other memory organization if desired. If a wider memory organization than that built into the controller 260 is needed - e.g.. in this example, if a by-16 organization is needed rather than by-8 - the parallel ports of multiple controllers can easily be parallelled. In this case the serial port access would need to be multiplexed over the multiple controllers (either by additional controllers or otherwise), but the parallel system port could simply be spht
  • RST* This pin provides a selection signal input to the serial port 705 (at serial port buffer 706).
  • the serial port 705 is connected to the serial data bus 206 in portable module 120.
  • RST* When RST* is low, all communications to the serial port are inhibited. When high, data is clocked into or out of the serial port.
  • the clock input signal is used to input or extract data from the three-wire serial port 705.
  • a clock cycle is defined as a falling edge followed by a rising edge on this line.
  • read cycles data is driven out onto the bus 206 after a falling edge.
  • write cycles data is latched into the port on the rising edge.
  • DQ This is the bidirectional data signal for the 3 wire serial port 705. Vahd data will be read from the DQ line, while RST* is high, on the low to high transition of the CLK signal, if the data is stable on the DQ line with the proper setup and hold times.
  • the DQE output signal is active (high level) whenever the 3 wire serial port buffer 706 is driving the DQ line. Therefore, this pin wiU be high whenever data is being read from the confroUer 260.
  • A0 Sys -A18 Sys are the lines of system address bus 701A
  • These 18-bit addresses can specify one of 2 19 (524,288, frequently written as "512K”) locations for access.
  • AOR ⁇ M-AISR ⁇ Addresses supphed to RAM, on RAM address bus 703 These signals aUow access to up to 512K bytes of RAM confroUed by the memory confroUer 260.
  • the addresses are either derived from the system address bus (AOs ys -Al ⁇ s y ..), or from the protocol and internal binary counter provided by the 3 wire serial port and associated timing circuits.
  • D0 Sys -D7 Sys are the lines of system data bus 701D. This bidhectional bus is used to carry data to and from the paraUel system bus and RAM.
  • D0 RAM -D7 RAM Data supphed to or read from RAM 262 on
  • RAM data bus 703D During write mode, this data is either derived from the system data bus (00 ⁇ -07 ⁇ ) or from the protocol and data stream provided by the 3 wire serial port and associated timing circuits.
  • the system control lines 701C provide control inputs CEg j .-* (chip enable), OE ⁇ -.* (output enable (read))(for transfer of data from RAM to the paraUel system bus), and WE Sys * (write enable). If the system paraUel port 701 has access to RAM 262, these control lines wiU be translated into the corresponding signals CE RAM *, OE RAM *, and E R ⁇ * on RAM control lines 703C. If the serial port 705 has access, these control signals wfll be derived from a 56-bit protocol provided by the 3 wire serial port and associated timing circuits.
  • V cc +5 Volt power for the memory controUer 260 (2 pins).
  • GND Ground for the memory controUer 260 (2 pins).
  • the block diagram of Figure 7A illustrates the main elements of the memory controUer 260.
  • the memory controUer 260 performs two major functions: serial to paraUel conversion (in converter 720), and access arbitration between the two ports (the serial port and the paraUel port). Access is arbitrated, between serial port 705 and byte-wide paraUel port 701, by address multiplexer 740 and data multiplexer 760. Arbitration is preferably controUed by signals from the 3 wire to byte wide converter 720.
  • the 3 wire serial port 705 has priority in accessing the RAM. Accesses through the paraUel port 701 are expected to "steer around" accesses through the serial port 705.
  • the byte wide paraUel port 701 has immediate access to RAM 262.
  • the system-derived control signals CE Sys *, OE Sys *, and WE ⁇ .*
  • CE Sys *, OE Sys *, and WE ⁇ .* are buffered by the control signal buffer 702C and passed through by control line multiplexer 710, to provide CE R ⁇ *, OE R ⁇ *, and WE RAM * respectively, which are connected directly to the control inputs of memory chip(s) 262.
  • the byte wide paraUel bus addresses (A0 S -A18 s ) and control signals (CE SyB *, OE Sys *, and WE Sys *) are buffered by the control signal buffer 702C, and passed through by the control line multiplexer 710 to provide outputs AO ⁇ -AIS RAM , CE RAJ , OE ⁇ *, and WE ⁇ * respectively, which are connected directly to the RAM memory chip(s) 262.
  • the data input/output signals (D0 Sys -D7 Sys ) are inte naUy buffered and sent to RAM on the data input/output signals D0 RAM -D7 RAM .
  • the buffering is designed to handle bidirectional data transfer.
  • Data will be written from the byte wide paraUel bus to RAM when CE ⁇ * and WE Sys * inputs .are both active (low).
  • the OE Sys * signal is a "don't care" signal during a write cycle. Data is read from RAM via the byte wide paraUel port when CE ⁇ * and OE Sys * signals are both low and WE Sys * is high.
  • the 3 wire to bytewide converter 720 takes control of the RAM, by switching the control/address/data multiplexers 710, 740, and 760.
  • the converter 720 foUows a 56-bit protocol, which is written seriaUy from port 705, to determine the action required and also the starting address location in the RAM to be used.
  • the last 8 bits of the 56 bit protocol give the value of a cyclic redundancy check byte (CRC).
  • CRC cyclic redundancy check byte
  • a correct value for this byte provides assurance that aU bits of the 56-bit protocol have been received correctly. If the 56 bits of protocol have not been received correctly, further action wiU be aborted.
  • the CRC check byte can detect up to three single bit errors within the 56 bit protocol, and can also be used on incoming and outgoing serial data streams to check the integrity of data being read or written.
  • the serial bus protocol can cause the memory controUer 260 to perform any of the foUowing eight actions:
  • a read function is defined by the binary pattern 11101000. This pattern, therefore, apphes to commands 1, 3, 5, and 6 of Table 1.
  • a write function is defined by the binary pattern
  • a burst read uses a 19 bit address field (which includes the second and third bytes plus bits 0, 1, and 2 of the fourth byte) of the protocol to determine the starting address of information to be read from RAM.
  • the byte of data resident in that location is loaded into the eight- bit shift register within the memory controUer 260.
  • the byte of data is then transferred from the shift register to the 3 wire bus by driving the DQ line on the falling edge of the next eight clocks with the LSB first.
  • a burst write uses the same 19 bit address field to determine the starting address of information to be written into RAM. Data is shifted from the DQ line of the 3 wire bus into an eight bit shift register within the memory controUer 260 on the next eight rising clock edges.
  • burst reads and writes wiU continue on a byte by byte basis, automaticaUy incrementing the selected address by one location for each successive byte. Termination of a current operation wiU occur at any time when RST* is taken low. However, once a byte of data has been loaded into the shift register, the ongoing write cycle wiU be aUowed to finish, even if RST* goes low during RAM write. This prevents corrupted data from being written into the RAM. If a fuU byte of data has not been loaded into the shift register when RST* goes low, no writing occurs. Reads can be terminated at any point, since there is no potential for corruption of data.
  • the read CRC command provides a method for checking the integrity of data sent over the 3 wire bus.
  • the CRC byte resides in the last byte (Byte 6) of the protocol.
  • the eight bit CRC byte not only operates on the protocol bits as they are written in, but also on aU data that is written or read from RAM.
  • the final value of the CRC is stored in the memory controUer 260. If a read CRC register command is issued, the stored CRC value is driven onto the D/Q line by the first eight clock cycles after the protocol is received.
  • the CRC value generated by the memory controUer 260 should match exactly with the value generated in the host system which is transmitting or receiving data on the other end of the 3 wire bus. If it does not, data has been corrupted and retransmission should occur.
  • the CRC for a previous transaction can only be obtained if a read CRC command is issued immediately after RST* goes low to reset the memory controUer 260, then high to accept a read CRC command If any other sequence is foUowed, an intermediate CRC wiU be generated and stored whenever RST* goes low again, destroying the CRC value of interest.
  • an arbitration byte is provided so that the serial and paraUel ports of the memory controUer 260 can determine the status of the other port.
  • a special byte in RAM address space is reserved to aUow for handshaking between the two ports.
  • This arbitration byte has a special attribute in that it is simultaneously accessible by both ports.
  • Two commands are used by the 3 wire serial port protocol to manage the arbitration byte. First, since this byte wiU create a hole in RAM address space for the paraUel byte wide port, a command is added to move the arbitration byte to either address location "00000" or address location "3FFFF".
  • the arbitration byte When setting the arbitration byte address location, the correct read/write field and command field must be entered, along with a value for bit A0 of the address field. (A 0 moves the arbitration byte to 00000, and a 1 moves it to 3FFFF.) It is important to note that the arbitration byte is located in the paraUel memory location assigned by the serial port using the appropriate commands. However, the physical byte of RAM is located within the memory controUer 260. The existence of this physical byte is transparent to the bytewide paraUel port and looks like normal RAM space with some write restriction. However, the serial port can stiU address the actual RAM location at either 00000 or 3FFFF in addition to accessing the arbitration byte.
  • the second command used by the 3 wire serial port provides for polling of the arbitration byte to determine the status of the paraUel port.
  • the arbitration byte can be set to indicate to the paraUel port at the serial port is taking over the RAM.
  • the second command protocol aUows the serial port to do a compressed read-write-read operation, which causes the arbitration byte to be read by the first eight clocks foUowing the protocol. The next eight clocks cause data to be written into the arbitration byte, and the last eight clock cycles aUow for a second read of the data for verification. These 24 cycles are initiated by entering the 56 bit protocol only once.
  • the protocol pattern entered is a write function in the read/write field (00010111), and the correct control field.
  • a third command, masking specific select bits provides a means for determining the identify of specific memory controUers in the presence of many memory controUers.
  • a read in the read/write field and a "11000" in the command field wiU execute a burst (masked) read. This operation ignores aU select bits, to permit a base station 110 to quickly determine the presence of any memory controUers.
  • a search can begin by masking aU but a single pair of memory controUer select bits.
  • a read in the read write field and a "11001" in the command field wiU unmask the first two LSBs of byte 4 of the select bits ( Figure 7C).
  • one byte of RAM has been reserved for arbitration between the 3 wire port and the bytewide paraUel bus.
  • the location of this byte within the memory map will be at address 00000 or at address 3FFFF (as determined by the protocol input from the 3 wire serial port).
  • the arbitration byte has special restrictions and disciplines so that the
  • the serial port 705 can read the whole arbitration byte, but can only write bits S2-SO.
  • the paraUel port 701 can read the whole byte, but can only write -bits P1-P0.
  • An internal counter controls count bits C2-C0, which cannot be written by either port.
  • the ports read the status bits, and write the bits over which they have control. If the serial port wants to access RAM, it poUs the arbitration byte until bit PI equals zero (indicating that the paraUel port is not engaged in access).
  • the 3 wire serial port should always abort any attempt to access RAM if PI equals one. When the 3 wire serial port completes any transfer of data to or from RAM, Bit S2 should be written back to zero so that the bytewide paraUel port wfll know that the 3 wire serial port is not using the RAM.
  • the bytewide serial bus can gain access to RAM by polling the arbitration byte until S2 bit equals zero.
  • the bytewide paraUel port When S2 equals zero, the bytewide paraUel port then writes a one into bit PI. A read cycle verifying that S2 equals zero and PI equals one confirms that the bytewide paraUel port has access to RAM. The bytewide paraUel port can then read or write RAM as required. When the entire transaction is complete, the bytewide paraUel port should write the PI bit to zero, signalling the 3 wire serial port that the RAM is not in use.
  • the bits B0, SI, and SO can be defined by the user definition to pass additional arbitration information making possible.more elaborate handshaking schemes between two ports. Some typical uses for these bits could be an indication that a port desires access to RAM, or the amount of RAM.
  • An alternative method of arbitration can also be foUowed.
  • arbitration is accomphshed by use of the count bits CO-C2. Due to the overhead protocol used for accesses on the serial bus 705, the serial port cannot read or write from RAM more often than once in every eight clock cycles. Moreover, the internal counter (which is updated whenever another byte is loaded into the internal serial buffer) is organized so that it is certain that serial port accesses wfll only occur when the counter transitions from a "111" state to a "000" state. The serial port has access on these clock cycles, and the paraUel port has access at aU other times, regardless of the arbitration byte status bits.
  • the software which controls the bytewide paraUel bus is never aUowed to access the bytewide RAM bus at these times (when the count bits are aU ones).
  • the paraUel port can determine the mim ' mnm time left before the 3 wire serial port wfll access the memory, by reading the count bits and the minimum clock cycle apphed to the 3 wire clock input. EssentiaUy the 3 whe serial port is given priority on access to RAM, and the bytewide paraUel port determines when it can access the RAM to avoid colliding with the 3 whe serial port.
  • the cyclic redundancy check byte is generated, within the controUer 260, by a conventional configuration.
  • this logic includes an eight bit shift register, four exclusive-OR gates, and two sets of transmission gates.
  • the transmission gates are connected so that the CRC Generator monitors the data stream from the DQ pin, and continuaUy updates its internal parameters, without disrupting the serial data flow.
  • the reset signal (RST*) must be high while the CRC Generator is being used, since an inactive state wfll disable the eight bit shift registers.
  • a CRC Generator for serial port communications can be constructed as described above to satisfy the memory controUer CRC requirements. However, another approach is to generate the CRC using software. Analysis of Power Efficiency
  • the portable module is a low power device capable of operating on one battery for ten years.
  • the power dissipation of the portable module faUs into two main categories: DC listening (or quiescent) power dissipation, and transient transaction power dissipation.
  • DC listening power dissipation refers to the current used by receiver chip 210 to continuously monitor for the presence of a signal delivered to it by the receiving antenna network.
  • the input comparator of receiver chip 210 operates with a current of 1.5 microA In ten years this wiU consume a charge of:
  • CVF 210-(-220 Some charge is used by receiver chip 210 and converter chip 220 in amplifying and interpreting pulse packets. This charge is referred to below as CVF 210-(-220 and refers to the charge used to move the voltage on the capacitances in the chip. The total of the charge consumption of the two chips has been measured to be 25 pC/input pulse.
  • the oscillator in converter chip 220 that provides the 5 kHz modulation of the 300 MHz transmitter burns 20 microA when active.
  • the converter chip 220 in the presently preferred embodiment, actuaUy divides down an 80 kHz oscfllator output to 5 kHz.
  • a contemplated improvement wfll replace the 80 kHz oscillator with a 20 kHz oscfllator, reducing the current by a factor of four to 5 microA
  • the 300 MHz transmitter burns 120 microA when on. As with receiver chip 210 and converter chip 220, there is charge used to move the capacitances in access control chip 230.
  • CVF 230 This is referred to as CVF 230 in the table below, and has a value of 25 pC/bit
  • the RAM in access control chip 230 burns 500 microA when it is active.
  • the RAM sensing scheme wfll be redesigned to reduce this value to 25 pC/bit.
  • access control chip 230 Whenever the RST* pin of access control chip 230 is high, access control chip 230 wfll sink 250 microA from it. (In a contemplated revision of access control chip 230 this value wfll be reduced to zero.)
  • 300 MHz transmit 120 microA 120 microA CVF 23Q 25 pC/bit 25 pC/bit
  • Step 1 Wake up module 1 To wake up module 1, 24 bits (16 bits of chip select and 8 bits of command) must be sent to converter chip 220. Assuming the data sent is 50% “1" bits and 50% "0" bits, and that the pulse packet sizes are 10 and 20 for a 0 and a 1 respectively this results in a charge consumption of:
  • Step 2 Send beacon protocol
  • Step 3 Scan for beacon
  • 20 microA is burned when the beacon oscfllator is running.
  • the 300 MHz transmitter wfll burn 120 microA at a 50% duty cycle for an average current burn of 60 microA
  • Converter chip 220 and the 300 MHz transmitter thus burn a total of 80 microA when the beacon is operating.
  • the beacon oscfllator current wfll be reduced from 20 microA to 5 microA When added to the 60 microA of transmitter current this gives a total current drain of 65 microA Also, it is planned to increase the beacon frequency to 20 kHz. This reduces the dweU time at each frequency step to be
  • 0.3 msec/4 0.075 msec and speeds up the scan by a factor, of four.
  • the bandwidth of the receiver is also planned to be increased, thus decreasing the number of steps required.
  • Step 5 Send access control protocol
  • access control chip 230 wfll not draw current from the RST* line, thereby removing the 250 microA x 4.8 msec component of charge above.
  • the new design's total charge consumption wfll be:
  • Step 6 Data transaction with access control chip 230
  • the combined number of bits sent to/from these fields is 256.
  • receiver chip 210 and converter chip 220 wfll consume 128 x (10 + 20) x 25 pC 96 nC.
  • the total charge used in the example transaction is 17,101.7 nC, using the present design, and 2,566.1 nC using the new design.
  • This transaction is merely an example, which shows how the total charge consumption of a transaction can be calculated. Moreover, this calculation Charge consumption of example transaction
  • the particular frequencies used for communication can be widely modified and varied.
  • the write-data frequency is preferably 200 kHz (as described) for North American apphcations; but for European apphcations, this frequency is preferably set to about 132 kHz instead.
  • an optical (infrared) link could be directly substituted for the 200 kHz RF link from the base station 110 to the portable module 120.
  • a sending interface could use a solid-state LED (driven by an output of the converter chip), in place of the transmitter circuit and antenna described.
  • the receiving interface could use a photodiode (covered by an appropriate filter), in place of the antenna, receiver chip, and converter chip described.
  • ultrasonic or microwave channels could also be readily substituted, particularly in the channel from the base station 110 to the portable module 120.
  • the period of the write-data frequency is about 50 times as long as the clock period of the low-power CMOS digital circuits used in the converter chip 220.
  • an optical (infrared) link could be directly substituted for the 200 kHz RF link from the base station 110 to the portable module 120.
  • Ultrasonic or microwave channels could also be readily substituted, particularly in the channel from the base station 110 to the portable module 120.
  • Additional signal processing can also be used in the base station 110.
  • AGC circuitry could be added to the RF receivers, to improve the signal-to-noise ratio over the expected range of signal strengths.
  • time-domain multiplexing can be used to aUocate time slots among the base stations.
  • the presently preferred embodiment uses a nonrechargeabie lithium battery; but alternatively a variety of other power sources can be used, including a combination of rechargeable and nonrechargeable batteries, or batteries combined with a solar-powered or
  • Additional signal processing can also be used in the base station 110.
  • AGC drcuitry could be added to the RF receivers, to improve the signal-to-noise ratio over the expected range of signal strengths.
  • time windowing in the base station's polling logic, so that the base station could exclude responses from remote modules 120 outside a certain radius (regardless of RF signal strength differences).
  • time-domain multiplexing can be used to aUocate time slots among the base stations.
  • circuits can readily be configured to detect signals with energy either in band A or in band B; or to detect only signals with energy in both band A and band B.
  • more complex logic gates can optionaUy be used instead of the two inverters of the presently preferred embodiment. For example, by substituting an AND gate for an inverter, a joint-timing relationship can be implemented, where one signal is gated by another. Similarly, by substituting XOR gates, a different combined relationship can be imposed. It should also be recognized that the power and data links described are not by any means limited to the specific chips described, nor even to the general area of communications modules.
  • the disclosed architecture could also be adapted to a wireless data communication module which included other integrated circuits, such as a microprocessor, display driver, and/or more memory.
  • the disclosed architecture could also be adapted to other module functions, such as a calculator which included a microprocessor and a digital signal processing chip.
  • the 56-bit access protocol could be widely varied, or other signalling schemes could even be used instead.
  • the power source for the micropowered remote module uses a nonrechargeable hthium battery; but alternatively a variety of other power sources can be used, including a combination of rechargeable and nonrechargeable batteries, or batteries combined with a solar-powered or RF-powered additional power input, etc.
  • the power-switching abilities of the disclosed integrated circuits make such multiple-source power architectures particularly convenient.

Abstract

Système de communication de données sans fil basse tension, dans lequel des postes de base (11) peuvent se connecter à des modules de données (210) portatifs alimentés par batterie lorsqu'ils sont amenés à portée. Dans les modules de données (210), chaque antenne de réception (121) est directement reliée à un comparateur (420A, 420B) à commande de gain. Des circuits numériques simples assurent le filtrage passe-bande (448) pour un faible coût. La sortie numérique à deux niveaux de comparateur (420A,420B) est amenée (par l'intermédiaire d'un détecteur de symbole intermédiaire, d'un compteur, et d'un comparateur d'intensité ondulatoire) à une machine d'état (552), décodant la forme d'onde numérique obtenue et un format bus sériel classique. Le bus de données interne (701D) assure l'interface avec des puces (262) de la mémoire et (facultativement) avec d'autres puces, telles qu'une touche électronique. La puce (220) de décodage fournit également une alimentation secondaire aux autres puces (230), et module l'alimentation (250) afin d'aider à la détection de transitions se produisant dans la ligne de la barre de remise à zéro du bus sériel (206). Les modules (230) utilisent des fréquences très distinctes pour des opérations de lecture et d'écriture. Les transmissions par le poste de base (110) utilisent un agencement de modulation de largeur d'impulsion dans lequel les signaux utilisés le plus communément correspondent à l'impulsion la plus courte. Un ordre de 'lecture' est codé avec la même largeur d'impulsion qu'un des deux ordres d'écriture. De plus, on peut utiliser une paire de contacts (270) par touches pour dériver la liaison HF. Le contrôle des erreurs (Fig. 75) est exécuté sur les ordres entrants avant que l'accès (260) à la mémoire ne soit permis. Une logique (510) 'anti-décharge' empêche la décharge de la batterie jusqu'à ce que le module soit initialement mis en circuit (en le plaçant dans un champ fort).
PCT/US1989/005579 1988-12-09 1989-12-08 Modules de donnees hf microcommandes WO1990006633A1 (fr)

Applications Claiming Priority (30)

Application Number Priority Date Filing Date Title
US283,426 1981-07-15
US28342788A 1988-12-09 1988-12-09
US28353488A 1988-12-09 1988-12-09
US28241788A 1988-12-09 1988-12-09
US28342588A 1988-12-09 1988-12-09
US28342888A 1988-12-09 1988-12-09
US28354988A 1988-12-09 1988-12-09
US28314088A 1988-12-09 1988-12-09
US28240288A 1988-12-09 1988-12-09
US28279288A 1988-12-09 1988-12-09
US283,140 1988-12-09
US282,008 1988-12-09
US283,549 1988-12-09
US07/282,410 US4897662A (en) 1988-12-09 1988-12-09 Integrated circuit with wireless freshness seal
US282,410 1988-12-09
US07/283,426 US4989261A (en) 1988-12-09 1988-12-09 Power supply intercept with reference output
US282,417 1988-12-09
US282,406 1988-12-09
US07/282,819 US4955038A (en) 1988-12-09 1988-12-09 Low-power RF receiver
US283,427 1988-12-09
US282,819 1988-12-09
US07/282,008 US4984291A (en) 1988-12-09 1988-12-09 Coded communication system with shared symbols
US07/283,554 US4967108A (en) 1988-12-09 1988-12-09 Differential-time-constant bandpass filter using the analog properties of digital circuits
US07/282,406 US5025486A (en) 1988-12-09 1988-12-09 Wireless communication system with parallel polling
US283,428 1988-12-09
US283,554 1988-12-09
US282,402 1988-12-09
US283,425 1988-12-09
US283,534 1988-12-09
US282,792 1994-07-29

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US5265615A (en) * 1992-12-18 1993-11-30 Eyal Frank Method and apparatus for continuous measurement of cardiac output and SVR
EP0715273A3 (fr) * 1994-08-17 1996-07-24 Metrologic Instr Inc Système et procédé pour lire des symbols codées par exemple de code à bâtonnets
US6253068B1 (en) 1997-05-09 2001-06-26 Micrel, Incorporated Fully integrated all-CMOS AM transmitter with automatic antenna tuning
USRE41207E1 (en) * 1997-05-09 2010-04-06 Micrel, Inc. Fully integrated ALL- CMOS AM transmitter with automatic antenna tuning
US6687488B2 (en) 1997-05-09 2004-02-03 Micrel, Incorporated Fully integrated all-CMOS AM transmitter with automatic antenna tuning
US6665520B2 (en) 1997-10-03 2003-12-16 Hewlett-Packard Development Company, L.C. Power management method of and apparatus for use in a wireless local area network (LAN)
EP0907262A3 (fr) * 1997-10-03 2002-11-06 Hewlett-Packard Company, A Delaware Corporation Procédé de gestion de la puissance pour un réseau local sans fil
US6564074B2 (en) 1997-10-03 2003-05-13 Hewlett-Packard Company Power management method of and apparatus for use in a wireless local area network (LAN)
EP0907262A2 (fr) * 1997-10-03 1999-04-07 Hewlett-Packard Company Procédé de gestion de la puissance pour un réseau local sans fil
EP1571760A3 (fr) * 1997-10-03 2011-02-02 Hewlett-Packard Company (a Delaware Corporation) Procédé de gestion de la puissance pour un réseau local sans fil
EP0942545A2 (fr) * 1998-03-07 1999-09-15 Philips Patentverwaltung GmbH Alimentation en tension pendant le mode d'attente
EP0942545A3 (fr) * 1998-03-07 2004-10-13 Philips Intellectual Property & Standards GmbH Alimentation en tension pendant le mode d'attente
WO2000067384A1 (fr) * 1999-04-30 2000-11-09 Micrel, Inc. Emetteur am tout cmos completement integre a reglage d'antenne automatique
EP2128736A1 (fr) * 2007-03-29 2009-12-02 Kyushu Institute of Technology Dispositif de circuit électronique
EP2128736A4 (fr) * 2007-03-29 2010-07-21 Kyushu Inst Technology Dispositif de circuit électronique
US7924636B2 (en) 2007-03-29 2011-04-12 Kyushu Institute Of Technology Electronic circuit device
CN112703645A (zh) * 2018-06-18 2021-04-23 相干公司 带有脉冲串模式控制的激光器-mopa

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