WO1988002955A1 - Circuit for delaying a digital signal - Google Patents

Circuit for delaying a digital signal Download PDF

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Publication number
WO1988002955A1
WO1988002955A1 PCT/EP1987/000571 EP8700571W WO8802955A1 WO 1988002955 A1 WO1988002955 A1 WO 1988002955A1 EP 8700571 W EP8700571 W EP 8700571W WO 8802955 A1 WO8802955 A1 WO 8802955A1
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Prior art keywords
clock
signal
signals
circuit
digital
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PCT/EP1987/000571
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German (de)
French (fr)
Inventor
Jean-Claude Guillon
Hans-Georg Von Umbscheiden
Original Assignee
Deutsche Thomson-Brandt Gmbh
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Publication of WO1988002955A1 publication Critical patent/WO1988002955A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0009—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15066—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices

Definitions

  • Circuit arrangement for delaying a digital signal
  • the invention relates to a circuit arrangement for delaying a digital signal using a shift register. It is often necessary to delay digital signals. To do this, they are loaded into shift registers and pushed through them at a certain rate until they are available again at the output. The data or signals that are read in first are then read out again (first in - first out FIFO). However, these shift registers are not suitable for an arbitrarily high clock frequency. If digital signals are now available that are transmitted with a wide bandwidth, processing is limited by the permissible clock frequency. Should e.g. digital television signals with a bandwidth of 6 MHz are transmitted via a delayed shift register, this would have to be clocked at 12 MHz.
  • the object of the invention is to enable a delay circuit with a large bandwidth using today's conventional digital modules, although these digital modules are not readily able to process the clock frequency required for the required bandwidth.
  • the object of the invention is to delay a digital television signal with a sufficiently high bandwidth by the duration of a line period. This object is achieved by the invention specified in the patent claim. Further embodiments of the invention result from the subclaims.
  • Figure 1 shows a block diagram
  • Figure 2 shows the clock signal generation for controlling the stages of the block diagram of Figure 1;
  • FIGS. 3 to 7 show pulse diagrams of the clock signals.
  • the CVBS signal to be delayed is connected via input I to an analog-to-digital converter AD, which converts the analog signal into an 8-bit data word, for example, and switches via the data bus D1 to a latch L1, a so-called latch, which with a clock CK1 of z.8. 12 MHz gives the data on the output data bus D2.
  • This data bus is divided into two parallel branches D2 'and D2''and gives the data to two further buffers L2 and L3.
  • the stored data is now at a clock frequency respectively. , which have the frequency CK1 / 2, in the example 6 MHz, and are out of phase by half a period, on the data bus D3 or D4.
  • the clock frequencies controlling the latches L2 and L3 are thus phase-shifted by one clock period T of the clock CK1.
  • the data bus D3 is connected to the input of a first shift register FIFO1 and the data bus D4 to the input of a second shift register FIFO2.
  • the shift registers FIFO1 and FIFO2 are read in with phase-shifted clocks CKW1 and CKW2 and read out again with phase-shifted clocks CKR1 and CKR2.
  • the shift registers FIFO1 and FIFO2 are periodically reset, for example at the beginning of a picture period of the television signal, with the aid of RS1 and RS2.
  • the frequencies CKR1 and CKR2 are half the clock frequency CK1 and just so large that the shift registers can still process them.
  • a clock generator circuit T to be explained later supplies the clock pulses mentioned in phase and frequency from a quartz-controlled basic clock cycle CK1.
  • the clocks CKR1 and CKR2 for reading out the shift registers FIFO1 and FIFO2 are shifted in relation to the read-in clocks CKW1 and CKW2 in such a way that, for example, the time of a line duration of 64 ⁇ s results between them.
  • the eight-bit-wide data, which are extracted with a delay from the shift registers FIFO1 and FIFO2, reach an intermediate memory L4 via the data bus D5 and an intermediate memory L5 via the data bus D6, which output their data with the clocks CKR1 and CKR2.
  • the two latches L4 and L5 are connected via the data bus D7 and D8 to a multiplex circuit MUX, which alternately transfers the data from the latches L4 and L5 to the outputs ⁇ A to 7A and ⁇ B to 7B Outputs ⁇ to 7 switches.
  • the multiplex circuit is with the clock Clocked depending on the level, so that the data are output on the data bus D9 with the original high frequency. You reach the memory L6, which is read out with the clock frequency CK1, so that the original digital signal of high clock frequency is again available via the data bus D10, which is converted with the aid of a digital-analog converter DA, so that the output 0 delayed signal FBAS 'can be removed.
  • control circuit T according to FIG. 1 required for generating the various clock signals according to FIGS. 3 to 7 is described below with the aid of the circuit diagram according to FIG.
  • a basic clock CK1 of, for example, 12 MHz is generated with the aid of a quartz-controlled oscillator 1.
  • This basic clock CK1 is divided in a frequency divider stage 2 and output as clock CK2 or via an inverter 3 as an inverted clock.
  • a pulse of approximately 40 ⁇ s duration is generated via a monostable multivibrator 4, which pulse arrives at the D input of a D flip-flop 5, at the clock input C of which there is a horizontal frequency pulse.
  • the Signal arrives at the input of a shift register 7, where it can be removed with a delay of 4 clock times (4T) and 8 clock times (8T) of the clock CK1.
  • the signal G delayed by 4T is inverted to G with the aid of the inverter 8 and arrives together with the Signal to a NAND gate 9, whose output signal via a D flip-flop 10 and a D flip-flop 11 with the clock signals CK2 and is synchronized.
  • Reset signals RS1 and RS2 are generated which at the beginning of each picture set the shift registers FIFO1 and FIFO2 to a defined initial state. In this way, temporal errors due to totalization cannot increase.
  • the signal delayed by 8 clocks 8T appears at the output of the shift register 7 as a signal K, which is inverted by the inverter 12 as a signal with the signal is converted to a NAND gate 13 to the signal L, which together with the clock signal CK2 via the NAND gate 14 to the signal X and inverted by the inverter 15 to the signal N shaped reaches the NOR gate 16, where it with the signal M is linked, which arises from the signal L and the clock signal CK1 at the AND gate 17. Then this becomes
  • the signals CKW2 are formed by using the clock signal from the signal L via the D flip-flop 19 a signal L 'is formed which, via the NAND gate 20 linked to the clock signal, forms the signal Y, which is converted to the signal N' via the inverter 21 and reaches the output via the NOR gate 22.
  • the Signal is created by combining the signal L 'with the clock signal CK1 via the AND gate 23 to the signal M' and reaches the output via the OR gate 24.
  • the signal CKR1 is created by combining the signal F with the clock signal CK2 via the NAND gate 25 to the signal Z. This reaches the output of this gate via the inverter 26 as the signal R via the NOR gate 27, to which the signal S is given will that by means of of the AND gate 28 arises from the AND combination of the signals F and CK1.
  • the signal CKR2 is generated by the signal F and the clock signal Via a D flip-flop 29, a signal T is generated which is transmitted via the NAND gate 30 together with the clock signal is connected to the input of an inverter 31, the output of which is connected to the OR gate 32 together with the output signal of the AND gate 33.
  • Figure 3 shows the development of the reset signals RS1 and RS2.
  • FIG. 4 shows the development of the write signal CKW1.
  • FIG. 5 shows the development of the write signal CKW2.
  • FIG. 6 shows the development of the read signals CKR1 and CKR2.
  • Figure 7 shows the mutual temporal position of the signals just referred to.
  • the digital signals are first stored in a buffer at a high clock frequency (CK1) and then written into the shift register
  • A-D converter AD EVM 8308 (Thomson) buffer L1, L2
  • L3, L4, L5, L6 SN 74 As 574 (Texas Instruments)
  • FIFO1, FIFO2 MK 4501 (MOSTEK)
  • D-A converter DA EVM 8408 (Thomson)
  • Shift register 7 SN 74 AS 164 (Texas Instruments)

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

A circuit delays a digital signal by means of shift registers. The digital signal is first stored at a high clock frequency (CK1) in an intermediate memory (21), after which it is alternately stored in intermediate memories (L2, L3) by means of half-clock frequency (CK1/2) synchronisation signals, displaced by a half-clock period. The outputs of these memories (L2, L3) are each connected to the inputs of a shift register (FIFO1, FIFO2). The signals, after a predefinable time, are again extracted by reading cycles (CKR1, CKR2) and each fed to an intermediate memory (L4, L5) which is also read at a clock frequency (CK1/2). The intermediate memory outputs (L4, L5) are connected to the inputs of a multiplex (MUX) circuit, which again reverses the initially-effected breakdown of the signals into two signal channels, and again inserts the signal in the correct sequence.

Description

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Schaltungsanordnung zur Verzögerung eines digitalen SignalsCircuit arrangement for delaying a digital signal
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------- ---------------------------
Die Erfindung betrifft eine Schaltungsanordnung zur Verzögerung eines digitalen Signals mit Hilfe eines Schieberegisters. Oftmals ist es erforderlich, digitale Signale zeitlich zu verzögern. Dazu werden diese in Schieberegister geladen und mit einem bestimmten Takt durch dieses geschoben, bis sie am Ausgang wieder zur Verfügung stehen. Dabei werden die zuerst eingelesenen Daten bzw. Signale zuerst wieder ausgelesen (first in - first out FIFO). Diese Schieberegister sind jedoch nicht für eine beliebig hohe Taktfrequenz geeignet. Liegen nun digitale Signale vor, die mit großer Bandbreite übertragen werden, ist die Verarbeitung durch die zulässige Taktfrequenz begrenzt. Sollen z.B. digitale Fernsehsignale mit einer Bandbreite von 6 MHz über ein verzögerndes Schieberegister übertragen werden, müßte dieses mit 12 MHz getaktet werden.The invention relates to a circuit arrangement for delaying a digital signal using a shift register. It is often necessary to delay digital signals. To do this, they are loaded into shift registers and pushed through them at a certain rate until they are available again at the output. The data or signals that are read in first are then read out again (first in - first out FIFO). However, these shift registers are not suitable for an arbitrarily high clock frequency. If digital signals are now available that are transmitted with a wide bandwidth, processing is limited by the permissible clock frequency. Should e.g. digital television signals with a bandwidth of 6 MHz are transmitted via a delayed shift register, this would have to be clocked at 12 MHz.
Der Erfindung liegt die Aufgabe zugrunde, unter Verwendung heute üblicher digitaler Bausteine eine Verzögerungsschaltung mit großer Bandbreite zu ermöglichen, obwohl diese digitalen Bausteine nicht ohne weiteres in der Lage sind, die für die erforderliche Bandbreite benötigte Taktfrequenz zu verarbeiten. Insbesondere soll mit der E r f i ndung die Aufgabe gelöst werden, ein digitales Fernsehsignal mit genügend hoher Bandbreite um die Dauer einer Zeilenperiode zu verzögern. Diese Aufgabe wird durch die im Patentanspruch angegebene Erfindung gelöst. Weitere Ausgestaltungen der Erfindung ergeben sich aus den Unteransprüchen.The object of the invention is to enable a delay circuit with a large bandwidth using today's conventional digital modules, although these digital modules are not readily able to process the clock frequency required for the required bandwidth. In particular, the object of the invention is to delay a digital television signal with a sufficiently high bandwidth by the duration of a line period. This object is achieved by the invention specified in the patent claim. Further embodiments of the invention result from the subclaims.
Um die Bildqualität von Fernsehempfängern zu verbessern, werden Speicheranordnungen benötigt, welche die Signalinformation einer Zeile oder eines Halbbildes oder eines. Vollbildes speichern. Auf diese Weise können digitale Filter realisiert werden. Mit einem um eine Zeile verzögerten Fernsehsignal kann ein im Zwischenzeilenverfahren aufgenommenes Fernsehbild in ein progressiv abgetastetes Bild umgewandelt werden.In order to improve the picture quality of television receivers, memory arrangements are required which contain the signal information of one line or one field or one. Save full screen. In this way, digital filters can be implemented. With a television signal delayed by one line, a television image recorded in the interline method can be converted into a progressively scanned image.
Nachstehend wird die Erfindung an dem Ausführungsbeispiel einer Schaltung zur Verzögerung eines FBAS-Signals um die Dauer einer Zeile mit Hilfe der Zeichnung erläutert.The invention is explained below using the exemplary embodiment of a circuit for delaying a CVBS signal by the duration of a line with the aid of the drawing.
Figur 1 zeigt ein Blockschaltbild;Figure 1 shows a block diagram;
Figur 2 zeigt die Taktsignalerzeugung zur Ansteuerung der Stufen des Blockschaltbildes nach Figur 1;Figure 2 shows the clock signal generation for controlling the stages of the block diagram of Figure 1;
Figuren 3 bis 7 zeigen Pulsdiagramme der Taktsignale.FIGS. 3 to 7 show pulse diagrams of the clock signals.
Das zu verzögernde FBAS-Signal wird über den Eingang I an einen Analog-Digital-Wandler AD geschaltet, der das analoge Signal z.B. in ein 8-Bit-Datenwort umwandelt und über den Datenbus D1 an einen Zwischenspeicher L1, ein sogenanntes Latch, schaltet, welches mit einem Takt CK1 von z.8. 12 MHz die Daten auf den Ausgangsdatenbus D2 gibt. Dieser Datenbus ist in zwei parallele Zweige D2' und D2'' aufgeteilt und gibt die Daten an zwei weitere Zwischenspeicher L2 und L3. Die gespeicherten Daten werden nun mit einer Taktfrequenz
Figure imgf000005_0001
bzw.
Figure imgf000005_0002
, die die Frequenz CK1/2, im Beispiel 6 MHz, aufweisen und um eine halbe Periode phasenverschoben sind, auf den Datenbus D3 bzw. D4 gegeben. Die die Zwischenspeicher L2 und L3 steuernden Taktfrequenzen sind also um eine Taktperiode T des Taktes CK1 phasenverschoben. Der Datenbus D3 ist an den Eingang eines ersten Schieberegisters FIFO1 und der Datenbus D4 an den Eingang eines zweiten Schieberegisters FIFO2 angeschlossen. Die Schieberegister FIFO1 und FIFO2 werden mit phasenverschobenen Takten CKW1 und CKW2 eingelesen und mit phasenverschobenen Takten CKR1 und CKR2 wieder ausgelesen. Die Schieberegister FIFO1 und FIFO2 werden periodisch z.B. zu Beginn einer Bildperiode des FernsehsignaIs jeweils zurückgesetzt mit Hilfe von RS1 und RS2. Die Frequenzen
Figure imgf000005_0003
CKR1 und CKR2 sind halb so groß wie die Taktfrequenz CK1 und gerade so groß, daß die Schieberegister diese noch verarbeiten können. Eine später noch zu erläuternde TakterzeugerschaItung T liefert die genannten Taktimpulse in Phase und Frequenz aus einem quarzgesteuerten Grundtakt CK1. Die Takte CKR1 und CKR2 zum Auslesen der Schieberegister FIFO1 und FIFO2 sind in Bezug auf die Einlesetakte CKW1 und CKW2 derart verschoben, daß sich zwischen diesen z.B. gerade die Zeit einer Zeilendauer von 64 μ s ergibt. Die verzögert aus den Schieberegistern FIFO1 und FIFO2 entnommenen acht-bit-breiten Daten gelangen über den Datenbus D5 an einen Zwischenspeicher L4 bzw. über den Datenbus D6 an einen Zwischenspeicher L5, die ihre Daten mit den Takten CKR1 bzw. CKR2 ausgeben. Die beiden Zwischenspeicher L4 und L5 sind über den Datenbus D7 bzw. D8 mit einer Multiplexschaltung MUX verbunden, welche die Daten aus den Zwischenspeichern L4 und L5 mit den Ausgängen ΦA bis 7A und ΦB bis 7B abwechselnd auf die Ausgänge Φ bis 7 schaltet. Die MulitplexschaItung wird mit dem Takt
Figure imgf000006_0001
pegelabhängig getaktet, so daß die Daten auf den Datenbus D9 mit der ursprünglichen hohen Frequenz ausgegeben werden. Sie erreichen den Speicher L6, der mit der Taktfrequenz CK1 ausgelesen wird, so daß über den Datenbus D10 wieder das ursprüngliche digitale Signal hoher Taktfrequenz zur Verfügung steht, welches mit Hilfe eines Digital- Analog-Wandlers DA umgeformt wird, so daß am Ausgang 0 das zeitverzögerte Signal FBAS' abgenommen werden kann.The CVBS signal to be delayed is connected via input I to an analog-to-digital converter AD, which converts the analog signal into an 8-bit data word, for example, and switches via the data bus D1 to a latch L1, a so-called latch, which with a clock CK1 of z.8. 12 MHz gives the data on the output data bus D2. This data bus is divided into two parallel branches D2 'and D2''and gives the data to two further buffers L2 and L3. The stored data is now at a clock frequency
Figure imgf000005_0001
respectively.
Figure imgf000005_0002
, which have the frequency CK1 / 2, in the example 6 MHz, and are out of phase by half a period, on the data bus D3 or D4. The clock frequencies controlling the latches L2 and L3 are thus phase-shifted by one clock period T of the clock CK1. The data bus D3 is connected to the input of a first shift register FIFO1 and the data bus D4 to the input of a second shift register FIFO2. The shift registers FIFO1 and FIFO2 are read in with phase-shifted clocks CKW1 and CKW2 and read out again with phase-shifted clocks CKR1 and CKR2. The shift registers FIFO1 and FIFO2 are periodically reset, for example at the beginning of a picture period of the television signal, with the aid of RS1 and RS2. The frequencies
Figure imgf000005_0003
CKR1 and CKR2 are half the clock frequency CK1 and just so large that the shift registers can still process them. A clock generator circuit T to be explained later supplies the clock pulses mentioned in phase and frequency from a quartz-controlled basic clock cycle CK1. The clocks CKR1 and CKR2 for reading out the shift registers FIFO1 and FIFO2 are shifted in relation to the read-in clocks CKW1 and CKW2 in such a way that, for example, the time of a line duration of 64 μs results between them. The eight-bit-wide data, which are extracted with a delay from the shift registers FIFO1 and FIFO2, reach an intermediate memory L4 via the data bus D5 and an intermediate memory L5 via the data bus D6, which output their data with the clocks CKR1 and CKR2. The two latches L4 and L5 are connected via the data bus D7 and D8 to a multiplex circuit MUX, which alternately transfers the data from the latches L4 and L5 to the outputs ΦA to 7A and ΦB to 7B Outputs Φ to 7 switches. The multiplex circuit is with the clock
Figure imgf000006_0001
Clocked depending on the level, so that the data are output on the data bus D9 with the original high frequency. You reach the memory L6, which is read out with the clock frequency CK1, so that the original digital signal of high clock frequency is again available via the data bus D10, which is converted with the aid of a digital-analog converter DA, so that the output 0 delayed signal FBAS 'can be removed.
Die zur Erzeugung der verschiedenen Taktsignale nach den Figuren 3 bis 7 erforderliche Steuerschaltung T nach Figur 1 wird mit Hilfe des Schaltbildes gemäß Figur 2 nachstehend beschrieben.The control circuit T according to FIG. 1 required for generating the various clock signals according to FIGS. 3 to 7 is described below with the aid of the circuit diagram according to FIG.
Zunächst wird ein Grundtakt CK1 von z.B. 12 MHz mit Hilfe eines quarzgesteuerten Oszillators 1 erzeugt. Dieser Grundtakt CK1 wird in einer Frequenzteilerstufe 2 geteilt und als Takt CK2 bzw. über einen Inverter 3 als invertierter Takt ausgegeben. Aus dem Vertikalsynchronimpuls V wird über eine monostabile Kippschaltung 4 ein Impuls von ca. 40 μs Dauer erzeugt, der auf den D-Eingang eines D-Flip-Flops 5 gelangt, an dessen Clock-Eingang C ein horizontaIfrequenter Puls anliegt. Am Ausgang des D-Flip-Flops 5 entsteht dadurch ein Impuls von genau einer Zeilendauer, der sich periodisch mit einer Frequenz von 25 Hz wiederholt und der mit Hilfe eines nachgeschalteten weiteren D-Flip-Flops 6 auf die Taktfrequenz CK2 synchronisiert wird. Der 25-Hz-Puls mit einer Impulsdauer von 64 us steht als F- und
Figure imgf000006_0003
-Signal an den Ausgängen zur Verfügung. Das
Figure imgf000006_0002
-Signal gelangt an den Eingang eines Schieberegisters 7, wo es mit einer Verzögerung von 4 Taktzeiten (4T) und von 8 Taktzeiten (8T) des Taktes CK1 abnehmbar ist. Das um 4T verzögerte Singnal G wird mit Hilfe des Inverters 8 invertiert zu G und gelangt zusammen mit dem
Figure imgf000007_0001
-Signal auf ein NAND-Gatter 9, desse Ausgangssignal über ein D-Flip-Flop 10 und ein D-Flip-Flop 11 mit den Taktsignalen CK2 und
Figure imgf000007_0002
synchronisiert wird. Es entstehen Reset-Signale RS1 und RS2, die zu Beginn jedes Bildes die Schieberegister FIFO1 und FIFO2 auf einen definierten Anfangszustand setzen. So können sich zeitliche Fehler durch Aufsummierung nicht vergrößern. Das um 8-Takte 8T verzögerte Signal
Figure imgf000007_0003
erscheint am Ausgang des Schieberegisters 7 als Signal K, welches durch den Inverter 12 invertiert als Signal mit
Figure imgf000007_0005
dem Signal
Figure imgf000007_0004
auf ein NAND-Gatter 13 zum Signal L gewandelt wird, welches zusammen mit dem Taktsignal CK2 über das NAND-Gatter 14 zum Signal X und Invertierung durch den Inverter 15 zum Signal N geformt an das NOR-Gatter 16 gelangt, wo es mit dem Signal M verknüpft wird, welches aus dem Signal L und dem Taktsignal CK1 am AND-Gatter 17 entsteht. Daraus wird dann dasFirst, a basic clock CK1 of, for example, 12 MHz is generated with the aid of a quartz-controlled oscillator 1. This basic clock CK1 is divided in a frequency divider stage 2 and output as clock CK2 or via an inverter 3 as an inverted clock. From the vertical sync pulse V, a pulse of approximately 40 μs duration is generated via a monostable multivibrator 4, which pulse arrives at the D input of a D flip-flop 5, at the clock input C of which there is a horizontal frequency pulse. At the output of the D-flip-flop 5, this results in a pulse of exactly one line duration, which is repeated periodically at a frequency of 25 Hz and which is synchronized to the clock frequency CK2 with the aid of a further D-flip-flop 6 connected downstream. The 25 Hz pulse with a pulse duration of 64 us stands as F- and
Figure imgf000006_0003
Signal available at the outputs. The
Figure imgf000006_0002
Signal arrives at the input of a shift register 7, where it can be removed with a delay of 4 clock times (4T) and 8 clock times (8T) of the clock CK1. The signal G delayed by 4T is inverted to G with the aid of the inverter 8 and arrives together with the
Figure imgf000007_0001
Signal to a NAND gate 9, whose output signal via a D flip-flop 10 and a D flip-flop 11 with the clock signals CK2 and
Figure imgf000007_0002
is synchronized. Reset signals RS1 and RS2 are generated which at the beginning of each picture set the shift registers FIFO1 and FIFO2 to a defined initial state. In this way, temporal errors due to totalization cannot increase. The signal delayed by 8 clocks 8T
Figure imgf000007_0003
appears at the output of the shift register 7 as a signal K, which is inverted by the inverter 12 as a signal with
Figure imgf000007_0005
the signal
Figure imgf000007_0004
is converted to a NAND gate 13 to the signal L, which together with the clock signal CK2 via the NAND gate 14 to the signal X and inverted by the inverter 15 to the signal N shaped reaches the NOR gate 16, where it with the signal M is linked, which arises from the signal L and the clock signal CK1 at the AND gate 17. Then this becomes
Signal
Figure imgf000007_0006
bzw. über das OR-Gatter 18 das Signal CKW1 gebildet.signal
Figure imgf000007_0006
or the signal CKW1 is formed via the OR gate 18.
In ähnlicher Weise werden die Signale CKW2 gebildet, indem aus dem Signal L über das D-Flip-Flop 19 mit dem Taktsignal
Figure imgf000007_0008
ein Signal L' gebildet wird, welches über das mit dem Taktsignal verknüpfte NAND-Gatter 20 das Signal Y bildet, welches über den Inverter 21 zum Signal N' umgeformt und über das NOR-Gatter 22 an den Ausgang gelangt. Das
Figure imgf000007_0007
-Signal entsteht durch Verknüpfung des Signals L' mit dem Taktsignal CK1 über das AND-Gatter 23 zum Signal M' und gelangt über das OR-Gatter 24 an den Ausgang.Similarly, the signals CKW2 are formed by using the clock signal from the signal L via the D flip-flop 19
Figure imgf000007_0008
a signal L 'is formed which, via the NAND gate 20 linked to the clock signal, forms the signal Y, which is converted to the signal N' via the inverter 21 and reaches the output via the NOR gate 22. The
Figure imgf000007_0007
Signal is created by combining the signal L 'with the clock signal CK1 via the AND gate 23 to the signal M' and reaches the output via the OR gate 24.
Das Signal CKR1 entsteht durch Verknüpfung des Signals F mit dem Taktsignal CK2 über das NAND-Gatter 25 zum Signal Z. Dieses gelangt über den Inverter 26 als Signal R über das NOR-Gatter 27 an den Ausgang dieses Gatters, an welches das Signal S gegeben wird, das mittels des AND-Gatters 28 aus der AND-Verknüpfung der Signale F und CK1 entsteht. Das Signal CKR2 wird erzeugt, indem das Signal F und das Taktsignal
Figure imgf000008_0002
über ein D-Flip-Flop 29 ein Signal T erzeugt, welches über das NAND-Gatter 30 zusammen mit dem Taktsignal
Figure imgf000008_0001
an den Eingang eines Inverters 31 gelegt ist, dessen Ausgang an das OR-Gatter 32 zusammen mit dem Ausgangssignal des AND-Gatters 33 geschaltet ist.The signal CKR1 is created by combining the signal F with the clock signal CK2 via the NAND gate 25 to the signal Z. This reaches the output of this gate via the inverter 26 as the signal R via the NOR gate 27, to which the signal S is given will that by means of of the AND gate 28 arises from the AND combination of the signals F and CK1. The signal CKR2 is generated by the signal F and the clock signal
Figure imgf000008_0002
Via a D flip-flop 29, a signal T is generated which is transmitted via the NAND gate 30 together with the clock signal
Figure imgf000008_0001
is connected to the input of an inverter 31, the output of which is connected to the OR gate 32 together with the output signal of the AND gate 33.
Die in den Figuren 3 bis 7 gezeigten Darstellungen der Signale berücksichtigen nicht die in der Praxis sich ergebenden kurzen zeitlichen Verzögerungen Sie sind der übersichtlichkeit wegen fortgelassen worden.The representations of the signals shown in FIGS. 3 to 7 do not take into account the short time delays that result in practice. They have been omitted for the sake of clarity.
Figur 3 zeigt die Entwicklung der Reset-Signale RS1 und RS2.Figure 3 shows the development of the reset signals RS1 and RS2.
Figur 4 zeigt die Entwicklung des Write-Signals CKW1.Figure 4 shows the development of the write signal CKW1.
Figur 5 zeigt die Entwicklung des Write- Signals CKW2.Figure 5 shows the development of the write signal CKW2.
Figur 6 zeigt die Entwicklung der Read-Signale CKR1 und CKR2.FIG. 6 shows the development of the read signals CKR1 and CKR2.
Figur 7 zeigt die gegenseitige zeitliche Lage der soeben bezeichneten Signale.Figure 7 shows the mutual temporal position of the signals just referred to.
Zu Beginn eines Bildes werden die digitalen Signale zunächst mit einer hohen Taktfrequenz (CK1) in einem Zwischenspeicher gespeichert und dann in die Schieberegister eingeschriebenAt the beginning of an image, the digital signals are first stored in a buffer at a high clock frequency (CK1) and then written into the shift register
(CKW1 und CKW2) und nach einer Verzögerung von einer Zeilen dauer (64 μs) entsprechend 768 Taktperioden (CK1) durch die Signale CKR1 und CKR2 ausgelesen. Für die in der Schaltung verwendeten logischen Bausteine wurden nachfolgend aufgeführte Typen verwendet:(CKW1 and CKW2) and after a delay of one line duration (64 μs) corresponding to 768 clock periods (CK1) read out by the signals CKR1 and CKR2. The following types were used for the logic modules used in the circuit:
A-D-Wandler AD: EVM 8308 (Thomson) Zwischenspeicher L1, L2A-D converter AD: EVM 8308 (Thomson) buffer L1, L2
L3, L4, L5, L6: SN 74 As 574 (Texas Instruments)L3, L4, L5, L6: SN 74 As 574 (Texas Instruments)
FIFO1, FIFO2: MK 4501 (MOSTEK)FIFO1, FIFO2: MK 4501 (MOSTEK)
MUX: 2x SN 74 AS 157 (Texas Instruments)MUX: 2x SN 74 AS 157 (Texas Instruments)
D-A-Wandler DA: EVM 8408 (Thomson)D-A converter DA: EVM 8408 (Thomson)
Mono 4: SN 74 121 (Texas Instruments)Mono 4: SN 74 121 (Texas Instruments)
D-Flip-Flop 5, 6, 19, 29: SN 74 AS 74 (Texas Instruments)D flip-flop 5, 6, 19, 29: SN 74 AS 74 (Texas Instruments)
Schieberegister 7: SN 74 AS 164 (Texas Instruments)Shift register 7: SN 74 AS 164 (Texas Instruments)
NAND-Gatter 9, 13, 14, 20, 25, 30:SN 74 AS 00 (Texas Instr.)NAND gate 9, 13, 14, 20, 25, 30: SN 74 AS 00 (Texas Instr.)
NOR-Gatter 16, 22, 27: SN 74 AS 02 (Texas Instruments)NOR gates 16, 22, 27: SN 74 AS 02 (Texas Instruments)
OR-Gatter 18, 24, 32: SN 74 AS 32 (Texas Instruments)OR gates 18, 24, 32: SN 74 AS 32 (Texas Instruments)
AND-.Gatter 17, 23, 28, 33: SN 74 AS 08 (Texas Instruments)AND gate. 17, 23, 28, 33: SN 74 AS 08 (Texas Instruments)
Inverter 8, 12, 15, 21, 26, 31: SN 74 AS 04 (Texas Instrum.) Inverters 8, 12, 15, 21, 26, 31: SN 74 AS 04 (Texas Instrum.)

Claims

Patentansprüche Claims
1. Schaltungsanordnung zur zeitlichen Verzögerung eines digitalen Signals mit Hilfe von Schieberegistern (FIFO), d a d u r c h g e k e n n z e i c h n e t, daß das mit einem Takt (CK1) hoher Taktfrequenz in einen ersten Zwischenspeicher (L1) eingelesene digitale Signal in zwei parallel angeordnete Zwischenspeicher (L2, L3) mit Taktsignalen (
Figure imgf000010_0001
eingelesen wird, deren Frequenzen halb so groß sind wie die des Taktes (CK1) und diese Taktsignale (
Figure imgf000010_0002
gegeneinander um erine halbe Taktperiode versetzt sind, und daß an den parallelen Ausgängen der Zwischenspeicher (L2, L3) je ein Schieberegister (FIFO1, FIFO2) angeschlossen ist, in welche die digitalen Signale mit zu den Taktsignalen
Figure imgf000010_0003
komplementären Taktsignalen (CKW1, CKW2) eingelesen werden und die Schieberegister (FIFO1, FIFO2) durch um eine vorgebbare Verzögerungszeit versetzte Auslesetakte (CKR1, CKR2) ausgelesen werden, und daß die Ausgänge der Schieberegister (FIFO1, FIFO2) an je einen, Zwischenspeieher (L4, L5) angeschlossen sind, die mit einer MulitplexschaItung (MUX) verbunden sind. welche mit einem Taktsignal
Figure imgf000010_0004
geschaltet wird, dessen Frequenz halb so groß ist wie die Taktfrequenz (CK1) für den an den Ausgang der Multip lexscha Itung (MUX) angeschalteten Zwischenspeicher (L6) der zur Ausgabe der digitalen Signale mit dem Takt (CK1) dient.1. Circuit arrangement for the time delay of a digital signal with the aid of shift registers (FIFO), characterized in that the digital signal read in with a clock (CK1) high clock frequency in a first buffer (L1) in two buffers (L2, L3) arranged in parallel with Clock signals (
Figure imgf000010_0001
is read in, whose frequencies are half the size of the clock (CK1) and these clock signals (
Figure imgf000010_0002
are offset from each other by half a clock period, and that a shift register (FIFO1, FIFO2) is connected to the parallel outputs of the intermediate memories (L2, L3), into which the digital signals are added to the clock signals
Figure imgf000010_0003
complementary clock signals (CKW1, CKW2) are read in and the shift registers (FIFO1, FIFO2) are read out by reading clocks (CKR1, CKR2) offset by a predeterminable delay time, and that the outputs of the shift registers (FIFO1, FIFO2) are each sent to one intermediate memory (L4 , L5) are connected, which are connected to a multiplex circuit (MUX). which with a clock signal
Figure imgf000010_0004
is switched, the frequency of which is half the clock frequency (CK1) for the buffer (L6) connected to the output of the multiplex circuit (MUX), which serves to output the digital signals with the clock (CK1).
2. Schaltungsanordnung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß sie zur Verzögerung eines digitalen Fernsehsignals dient. 2. Circuit arrangement according to claim 1, characterized in that it serves to delay a digital television signal.
3. Schaltungsanordnung nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t, daß die Verzögerungszeit der Dauer einer Zeile des Fernsehbildes entspricht. 3. Circuit arrangement according to claim 2, d a d u r c h g e k e n n z e i c h n e t that the delay time corresponds to the duration of a line of the television picture.
PCT/EP1987/000571 1986-10-07 1987-10-05 Circuit for delaying a digital signal WO1988002955A1 (en)

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DE19863634092 DE3634092A1 (en) 1986-10-07 1986-10-07 CIRCUIT ARRANGEMENT FOR DELAYING A DIGITAL SIGNAL

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EP0499061A1 (en) * 1991-02-13 1992-08-19 Alcatel SEL Aktiengesellschaft Delay circuit and method to delay a binary signal
US5249229A (en) * 1989-04-04 1993-09-28 Laboratoire Europeen De Recherches Electroniques Avancees Societe En Nom Collectif Device and method for generating control signals

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FR2742910B1 (en) 1995-12-22 1998-04-17 Thomson Multimedia Sa METHOD AND DEVICE FOR ADDRESSING A MATRIX SCREEN
DE19732895C2 (en) * 1997-07-30 1999-05-12 Siemens Ag Arrangement for the rapid digital generation of a digital signal with a predeterminable phase position using a reference carrier signal
DE19945684C2 (en) * 1999-09-23 2003-03-27 Siemens Ag Method and device for arithmetic bit shift operations

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FR2545297A1 (en) * 1983-04-26 1984-11-02 Thomson Csf DELAY DEVICE AND ITS USE IN THE DEVICE FOR DECODING DISTANCE MEASUREMENT EQUIPMENT
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FR2645384A1 (en) * 1989-04-04 1990-10-05 Europ Rech Electr Lab DEVICE AND METHOD FOR GENERATING CONTROL SIGNALS
EP0391784A1 (en) * 1989-04-04 1990-10-10 Laboratoire Europeen De Recherches Electroniques Avancees Device and method for generating control signals
WO1990012471A1 (en) * 1989-04-04 1990-10-18 Laboratoire Europeen De Recherches Electroniques Avancees Device and process for the generation of control signals
US5249229A (en) * 1989-04-04 1993-09-28 Laboratoire Europeen De Recherches Electroniques Avancees Societe En Nom Collectif Device and method for generating control signals
EP0499061A1 (en) * 1991-02-13 1992-08-19 Alcatel SEL Aktiengesellschaft Delay circuit and method to delay a binary signal

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