WO1987006071A1 - Systeme et procede de transport de donnees - Google Patents

Systeme et procede de transport de donnees Download PDF

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Publication number
WO1987006071A1
WO1987006071A1 PCT/US1986/000633 US8600633W WO8706071A1 WO 1987006071 A1 WO1987006071 A1 WO 1987006071A1 US 8600633 W US8600633 W US 8600633W WO 8706071 A1 WO8706071 A1 WO 8706071A1
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WO
WIPO (PCT)
Prior art keywords
data
modem
ask
transmission
hybrid
Prior art date
Application number
PCT/US1986/000633
Other languages
English (en)
Inventor
Anthony Michael Andruzzi, Jr.
Stanley Bruce Warner
Original Assignee
Consultant's Choice Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US06/520,683 priority Critical patent/US4580276A/en
Application filed by Consultant's Choice Inc. filed Critical Consultant's Choice Inc.
Priority to EP19860902250 priority patent/EP0261113A1/fr
Priority to PCT/US1986/000633 priority patent/WO1987006071A1/fr
Publication of WO1987006071A1 publication Critical patent/WO1987006071A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26

Definitions

  • ASK/FSK data encoding and transmission scheme which encodes for a logical one, or mark, by the use of one unique frequency, or tone, and similarly a logical zero, or space, is designated by the use of a second unique frequency, or tone, in both the transmitting and receiving of data; this is the FSK-aspect of the transmission scheme.
  • the second, distinct logical-zero frequency, or tone is held “on” for a period of time less than or equal to one-half the total digital bit period of the "0."
  • the two-fold prescription for encoding and transmitting/receiving data in this manner permits a high degree of reliability in data handling, particularly in counteracting false bits, transmission media transients, and other sources of digital error and noise.
  • Implementation of this ASK/FSK scheme is readily accomplished by the modem of this invention insofar as it is in direct contact with other modems of like kind in a local area network (LAN).
  • LAN local area network
  • Such a private data network, or LAN need not be medium-specific in order to practice data handling with the ASK/FSK scheme aforementioned; it could operate over a fiber optical link, acoustic channel, RF channel, line-of-sight laser link or even electrical conductors.
  • the generic embodiment of this full invention includes only a generalized transmission medium to which are interconnected a collection of modems which exchange data according to the hybrid ASK/FSK scheme herein disclosed, and which further may (and should) have computers and/or electronic devices and terminals separately and individually connected thereto which are able to communicate with simplified protocols due to the inherent low error and low noise characteristics of the hybrid ASK/FSK scheme.
  • a hierarchy could be established, for example, among all these devices whereby a computer could serve as the "network master” with the remaining devices or terminals functioning as “network slaves.”
  • a computer could serve as the "network master” with the remaining devices or terminals functioning as “network slaves.”
  • An LAN of any type discussed to this point could utilize a discrete pair of frequencies for its logical one's and zero's in accordance with the dispersion characteristics of the transmission medium selected and the bits-per-second (baud) data transmission rate desired.
  • One preferred embodiment of this invention is transmission- medium-specific in favor of a set of electrical conductors which may be wire pairs or coaxial cables.
  • Such an LAN could be designated "ELECTRICAL SYSTEM TRANSPORTER” (EST), and it could function along the lines of a common power-line carrier system (PLC).
  • EST- embodiment of this invention is herein disclosed to operate within the localized transmission medium defined by the electrical distribution system (metallic conductors) of a building, house or any localized residential/commercial complex.
  • data is exchanged in bidirectional fashion (half-duplex) among at least one network master modem, to which is connected a computer, and a plurality of slave modems which are appropriately connected to separate electronic devices, alarms, printers, thermostats, appliances, monitors or communication terminals.
  • a phase-interface circuit is utilized to minimize phase distortion problems which could occur in the LAN by virtue of the PLC- type multiple electrical branches (conductors) in a single building or plurality of buildings.
  • a modem constructed within the guidelines associated with the EST would have the following minimal features or characteristics: the capability of both transmitting and receiving a pair of distinct tones in the frequency range of c. 170 kHz, a commercial power (i.e., 60 Hz, etc.) drainage filter, an on-board microprocessor controller, an analog-to- digital-converter-type (ADC) receiving circuit, a digital-to-analog- converter-type (DAC) transmitting circuit a special XOR-gating digital error-detecting-and-blocking subcircuit, appropriate digital interfaces for linking the microcontroller to the transmitter and receiver sections, and asynchronous clocking means. Low-cost design could be maintained while still permitting data transmission rates of c. 85 kbaud to be utilized.
  • the error rates and noise rejection characteristics of a modem employing the hybrid ASK/FSK data encoding and transmission scheme are so conducive to high reliability in data handling that a satisfactory EST, including one master and up to 256 slave modems, is disclosed utilizing only 3-bit protocols and 8-bit modem addresses.
  • Figure 1A illustrates the generic embodiment of the invention consisting of a LAN with at least one master controller and with a generalized medium serving as the communication bus.
  • Figure IB illustrates a second embodiment of the invention consisting of an electrically wired LAN functioning as a PLC system with a fixed master controller.
  • Figure 2 represents a typical modem (master or slave) used in the PLC-type LAN of Fig. IB.
  • Figure 3 represents the two-frequency digital transmission and data-encoding scheme intended to be used integrally with this invention for achieving low error rates and high S/N.
  • Figure 4 delineates the essential details of the ADC receiver and S/P interface sections of the modem illustrated in Figure 2.
  • Figure 5 shows the essential details of the DAC transmitter and P/S interface sections of the modem illustrated in Figure 2.
  • Figure 6 is an example of a single 12-bit message format which could be utilized in the data transmission scheme of this invention; also detailed is a legend of the low-level protocols which could be used in the control field of that message. Some higher-level protocols are also exhibited.
  • Figure 7 depicts the interface between the on-board microprocessor controller and the digital shift registers of the transmit/receive circuits of the modem illustrated in Figure 2.
  • Figures 8A and 8B represent a minimal low-level protocol operational algorithm and event chart for two-way communication between the master and slave modems of Figures 1A and IB.
  • Figure lA refers to a design of a local area network (LAN) for two-way data intercommunication employing all the fundamental concepts of this invention in the broadest, most generic fashion. This fact should become immediately apparent to the reader by the absence of identity imputed to the communication bus j, which accordingly may be electrical conductors (as in the second embodiment of this invention), optical fiber,
  • This generic invention is further characterized by the use of at least one master modem 2 or a plurality of master modems, all of which are connected to controller-computers 3i and all of which conduct their digital transmissions with the same pair of frequencies [v.] .
  • master/slave functions and roles are software- implemented (microcontroller) and that masters are only associated with computers herein because of the latters' greater sophistication vis-a-vis appliances, printers, thermostats, alarms or other devices, j3, less amenable to network command.
  • Each modem sends and accepts data and address (information) and protocol to and from its microprocessor (controller) via any of the many possible parallel or serial standards available.
  • the use of multiple master modems/computer-controllers permits the LAN to achieve its maximum utility and flexibility (roving- master option). Accordingly, the network-master-function may be passed in a predetermined fashion among other possible controller-computers J3 on the LAN as a high-level command (protocol) similar to "token-passing" during the pre-programmed polling sequence which occurs among the modems 2.
  • the LAN consist of electrical conductors 1A and IB as the main communications bus and 4 as the network branch links. It is because of the metallic electrical character of the main bus ' in this LAN that this species embodiment of the invention is known as the Electrical System Transporter (EST), and it is intended to operate in either residential or commercial environments through the electrical distribution network of a building in which communications cabling is either undesirable or impractical.
  • EST Electrical System Transporter
  • the communication buses 1A and IB are the electrical wiring system of a building(s) in which an LAN is to be established; 1A and IB represent separate, multiple branches off a common electrical distribution system which differ from one another by a small phase angle ⁇ with respect to the common 60 Hz, or other value of power transmission frequency, fed to the network at its common tie-point at the house service distribution box 1 which is located at the (commercial AC) power cable entrance 12. It is assumed that, given the common gauges of wire used in houses and buildings today, the total maximum length of both conductors 1A and IB are typically less than 4000 feet.
  • This length is in anticipation of placing up to 256 modems 15 and 19 on the line, in an 8-bit address format, at anywhere from , 2 to ohms input impedance for each modem (unmatched) and of transmitting signals below FCC thresholds.
  • the various slave modems 19 and their concomitant devices and appliances J20 should be freely placed around the house or building U which supports the LAN — interconnection into which is accomplished in the standard manner with normal electrical outlets and plugs .
  • this EST embodiment of the invention also anticipates the use (and therefore the limitation) of a single permanent, electrically wired master modem 15 coupled to its controller-computer 16. These two units may be placed at any suitable location within the building or house 11. This goes without saying for the slave modems 19 and their devices £0, which may be locally powered or energized through the conductors 1A and IB in the standard manner.
  • each controEer in each modem is some 8-bit microprocessor means, such as the Intel 8035, 8048, 8051 or equivalent device. Should a second system operating on a second set of frequencies
  • an LC-interface circuit 14A consisting of capacitors and torroids wound on nonsaturable cores (or an equivalent analog means), may be fabricated to tie the various wiring phases together at points remote from the central branching point 13 — yet, as close thereto as possible.
  • the inductance, L, and capacitance, C, of this interface circuit 14A are to be chosen by conventional calculation methods in order to series-tune this crossover to a frequency equal to that of the higher frequency of the set [v.] , which is the more attentuated frequency.
  • This phase interface circuit 14A also serves to cancel signal reflections at the house service distribution box 13 and furthermore tends to mitigate the transmission of both frequencies into the commercial network 12. SimEarly, a second network on the LAN using a different pair of frequencies [v.] would . require the deployment of a second selectively tuned LC-interface 14B.
  • Figure 2 represents a typical modem which, depending upon the software programmed into the microprocessor and the device to which it is coupled, may function either as a master or a slave.
  • the design characteristics which foEow are intended to optimize the function of this modem within the PLC-type LAN embodiment of this invention known as EST.
  • Interconnection to either phase 1A or IB of the LAN is accompUshed via a standard waE plug and socket union 4. That electrical pair is truly the network data line used by aE modems to exchange data; it is plugged directly into an integrated 60 Hz (or other) Hne drainage filter, or line interface circuit, 1 which permits 83 dB quieting. Any noise remaining on the line after this point exists principaEy in the form of transients or "spikes" and are dealt with in the various filter and discrimination sections of the receiver Z2 ⁇ and 3 respectively.
  • the receiver section of every modem consists of three main parts: an ampEtude regularizer and filter stage 32, a data-error eEmination and ADC stage 33, and a serial-to-paraEel (S/P) digital interface 4 which connects directly via circuit path 4£ to the appropriate ports of an 8048-type microprocessor j$S or its equivalent amont controEers.
  • the interface 3 is also paraEeled with a binary integration circuit J3 on path 40 whereby a protocol-predetermined number of consecutive logical ones ("El . . . 1") produces an "acknowledge" message for the microcontroEer 8. (For further details, see Figures 4 and 7.)
  • Modem transmitter sections are fundamentaEy the inverse of the receivers. They also contain three discrete stages: paraEel-to-serial (P/S) digital interface jSJ5, a gating data release stage Z ⁇ , and a DAC 3_7. (For further information, see Figures 5 and 8.)
  • Figure 3 is a graphic representation of the dual-frequency transmission scheme which is at the very heart of this invention.
  • the coding scheme is unequivocal because two separate events must take place in order for a "mark" or "space” to be generated.
  • the best categorization for this coding scheme is hybrid ASK/FSK since it gives an indication of the dual conditions which must obtain before digital data can be created. That duaEty of conditions is as foEows.
  • vaHd data wiE be forthcoming for reception or transmission. It is this same duaEty of events which makes for the unequivocal geberatuib if data which is relatively error-free and virtuaEy immune from the noise and interference which characterizes PLL carrier-sync methods.
  • the specific frequencies, or tones, must be selected so that they are sufficiently far apart in frequency to prevent spurious triggering and harmonic problems with the various filter and detection circuits in the receiver sections 3£ and 3_3 of the modem. They may be as close together as filter discrimination permits, and a good indicium could be a frequency difference sufficent to produce a -6dB signal from the "wrong" fEter at "correct” signal input — hence, a convenient threshold level for a comparator reference signal.
  • StiE referring to Fig. 3, it is the selection of the discrete frequencies which next has a direct bearing on the bit period, and hence, upon the data transmission rate.
  • the minimum burst from one osciEator is one cycle for a time (for a one) or t sauce (for a zero), which intervals are necessarEy unequal since v. is somewhat higher than v modifier. Therefore, a minimum tone burst wiE have two zero-crossings.
  • the digital data transmission rate must be selected and/or the frequency of the lower-tone osciEator must be chosen so that the bit period is temporarEy two times as long as one cycle of v impart (the lower frequency), or alternatively, the bit rate (baud) of the clocked data stream must be one-half v ⁇ .
  • the bit period is temporarEy two times as long as one cycle of v impart (the lower frequency)
  • the bit rate (baud) of the clocked data stream must be one-half v ⁇ .
  • the incoming analog tone bursts must be converted into digital data; hence, the first section of the receiver is known as the ADC.
  • ADC the first section of the receiver. It consists of a bipolar hard Emiter j50_ which itself includes an operational ampEfier and a dual-diode network. It operates in the absence of any automatic gain control within a range of 5 mEEvolts to 10 volts (66 dB dynamic range). It is this stage which kiEs most of the spikes and flash thus rendering weE formed tone bursts v. and v ⁇ into the subsequent filter stage.
  • the circuit path diverges into two sets of filters 51 and 5 I; the former being tuned to pass and double-integrate only v,; the latter, set up for v promotion only.
  • the bipolar waveforms then each separately proceed into the fast-attack/slow-release sample-and-hold detecting (S/H) circuits 5j ⁇ and 54 respectively for v. and v publication.
  • the ADC stage ends where the outputs of these S/H circuits outpulse into respective comparator amps 5(5 and 5J as referenced by an ampEtude standard 55A whose output is always high enough, as an out-of-band false-trigger guard, to keep both comparators 56 and j57_ "normaEy off.”
  • Data/address messages may be sequentiaEy loaded into the S/P converter ZA which comprises shift registers 66, 6J_, and 6 during error- free conditions within the receiver.
  • the S/P shift registers (typicaEy 74164's or 74198's) are configured to load information sequentiaEy and im mediately prior to the generation of a "data-ready" signal ("start bit") in register 6 3, after which, the registers' are data-latched until reset by the controEer 38.
  • the third timer which may be coEocated on a single chip with the other two timers (e.g., 558-type timer device), is set up to reset the S/H detecting circuits i53 and 54 and to clamp the data inputs (+) of the comparators 5ji_ and 57_ to the "off" state during at least one-half of the data bit period.
  • the end result is a paraEel shifting-out of data to the 8048-type microprocessor 38- which could be associated with either a slave device or a master computer.
  • Data can be read through a single 8-bit port since the shift registers , j57, and 6j3 are triggered separately and sequentiaEy.
  • the information bit length, and hence overaE word length may be easily changed, and aE that would be "hardware necessary" involves only the translocation of the start bit to the first Eve pin of the lowest-numbered register in the respective sets 6(5, 67, and 6£ and 81, 8£, and 8Z.
  • Figure 6 provides a syrnboHc chart for the mnemonic structure of the simple, low-level 3-bit protocol required to run a simple yet satisfactory LAN in terms of the design requirements of the EST.
  • a typical message, or word, structure is also depicted — based on the 8-bit model for either data or address.
  • Other combinations are possible given different control field requirements and/or circuit components, and at least one such alternative is displayed wherein a higher-level 4-bit protocol (nos. 9 through 12) could be used with the EST to achieve the roving-master feature mentioned in reference to Figure lA.
  • NaturaEy this would tax these Elustrated shift registers to their fuE capacity, and 24-bit bytes would easEy result.
  • Figure 7 Elustrates a typical interconnection between an 8048- type microcontroEer 38. and the digital interfaces 34 and 35 associated with the transmit/receive subcircuits of EST-type modems or other contemplated embodiments within the spirit of this invention. Also depicted is the interface between the exemplary 8048-type microprocessor jJ!3 and both the binary integration circuit J5 of the modem's receiver and the clocks 84 employed in the modem's transmitter. As one skiEed in the relevant arts can readEy see, only one of the two quasi-bidirectional data ports lOjO (8048 design assumed) is required for interconnection both to the transmit and receive buffers 81, 8 :, and 8J$ and (56, 67.
  • lOjO 8048 design assumed
  • the transmit-start pin of register j5 may be connected directly to (sequential or paraEel fashion) latch/enable pins ("serial input” or "shift load” as found in typical 74165's) of the individual buffers 81, 8%, and 83.
  • latch/enable pins serial input or "shift load” as found in typical 74165's
  • Figure 7 shows that the binary integration circuit j3 should be integrally related to the buffers 6(5_, 67, and j5_8 insofar as the microprocessor J3_8 pin "read” (or output port equivalent) must create a positive output to both disable the binary integration circuit 3_9_ and enable the S/P buffers 66, 67_, and (3i3 and vice-versa.
  • the data-in line originates at the OR-gate j3 ) and terminates both in the first shift register (56 and the binary integration circuit 2! , wherein the detection of a "El . . . 1" in this latter element 3j3 creates a positive "acknowledge" signal hard-wired directly to the microprocessor j3 at a suitable interrupt-style pin termination such as "single step.”
  • the output/input between the 8048-type microprocessor 38 and the various independent devices 2_0 or computers) 16 may be accompEshed in a dozen common ways via an appropriate communication bus 101 which may be fuEy bidirectional or simplex depending upon the expEcit appEcations contemplated.
  • Each modem on the LAN may even have completely different interfaces at this point.
  • Figures 8A and 8B are intended to give one skiEed in arts a simple "big picture" of the function-by-function as weE as the priority of operations available for a (12-bit byte) minimaEy designed, yet versatEe EST.
  • the inventors hope that the inclusion of this algorithmic flowchart wiE spare the reader the experience of traversing ulterior troublesome text.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

Un réseau local privé (LAN) est créé afin d'être utilisé avec divers moyens de transmission afin d'échanger des données, des adresses préaffectées et des signaux de commande selon des protocoles simplifiés. Les éléments du LAN peuvent se composer d'une combinaison quelconque d'ordinateurs (3, 16), de dispositifs électroniques (6, 20) ou de terminaux (10, 18) conçus pour communiquer entre eux par l'intermédiaire de modems (2, 5, 9, 15, 19, 21) commandés par microprocesseur et pouvant fonctionner en mode maître ou en mode asservi à l'intérieur du LAN en fonction des exigences de leur propre logiciel. Chaque modem (2, 5, 9, 15, 17, 19, 21) relié au LAN a la propriété de filtrer le bruit analogique, de détecter/bloquer les erreurs de données numériques, de fonctionner à l'intérieur d'une gamme étendue d'impédances de circuit appropriées et d'émettre et de recevoir des données numériques à des débits avoisinant 85 kbauds sous la forme de fréquences ou de tonalités en rafales selon un schéma de transmission et de codage de données hybrides de modulation par déplacement d'amplitude (ASK)/de modulation par déplacement de fréquence (FSK). Le schéma de codage/transmission consiste à sélectionner une première fréquence, ou une première tonalité destinée à être à la fois émise et reçue pendant un de temps (t1) ne dépassant pas la moitié de la période binaire d'un ''1'', et à sélectionner une seconde fréquence, destinée à être à la fois émise et reçue pendant un temps (t2) ne dépassant pas la moitié de la période binaire d'un ''0''.
PCT/US1986/000633 1983-08-05 1986-03-31 Systeme et procede de transport de donnees WO1987006071A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US06/520,683 US4580276A (en) 1983-08-05 1983-08-05 System and method for transporting data
EP19860902250 EP0261113A1 (fr) 1986-03-31 1986-03-31 Systeme et procede de transport de donnees
PCT/US1986/000633 WO1987006071A1 (fr) 1986-03-31 1986-03-31 Systeme et procede de transport de donnees

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PCT/US1986/000633 WO1987006071A1 (fr) 1986-03-31 1986-03-31 Systeme et procede de transport de donnees

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002013442A2 (fr) 2000-08-04 2002-02-14 Intellon Corporation Procede et protocole permettant d'assurer des intervalles sans conflit et une certaine qualite de service dans un reseau a acces multiple par detection de porteuse (csma)

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US3320364A (en) * 1962-06-07 1967-05-16 Int Standard Electric Corp System for phase coding information by blanking half cycles of a continuous periodicwave
US3486117A (en) * 1966-02-02 1969-12-23 Postmaster General Uk Radio telegraph signal transmission
US3820070A (en) * 1972-06-16 1974-06-25 Mc Cabe Powers Body Co Control system for a derrick utilizing light multiplex communication link
US4001693A (en) * 1975-05-12 1977-01-04 General Electric Company Apparatus for establishing communication between a first radio transmitter and receiver and a second radio transmitter and receiver
US4057793A (en) * 1975-10-28 1977-11-08 Johnson Raymond E Current carrier communication system
US4320522A (en) * 1980-05-09 1982-03-16 Harris Corporation Programmable frequency and signalling format tone frequency encoder/decoder circuit
US4345250A (en) * 1980-12-22 1982-08-17 Honeywell Information Systems Inc. Information communication system with collision avoidance
US4425665A (en) * 1981-09-24 1984-01-10 Advanced Micro Devices, Inc. FSK Voiceband modem using digital filters
US4464766A (en) * 1982-04-29 1984-08-07 Autophon A.G. Radio transmission system for binary coded signals

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3320364A (en) * 1962-06-07 1967-05-16 Int Standard Electric Corp System for phase coding information by blanking half cycles of a continuous periodicwave
US3486117A (en) * 1966-02-02 1969-12-23 Postmaster General Uk Radio telegraph signal transmission
US3820070A (en) * 1972-06-16 1974-06-25 Mc Cabe Powers Body Co Control system for a derrick utilizing light multiplex communication link
US4001693A (en) * 1975-05-12 1977-01-04 General Electric Company Apparatus for establishing communication between a first radio transmitter and receiver and a second radio transmitter and receiver
US4057793A (en) * 1975-10-28 1977-11-08 Johnson Raymond E Current carrier communication system
US4320522A (en) * 1980-05-09 1982-03-16 Harris Corporation Programmable frequency and signalling format tone frequency encoder/decoder circuit
US4345250A (en) * 1980-12-22 1982-08-17 Honeywell Information Systems Inc. Information communication system with collision avoidance
US4425665A (en) * 1981-09-24 1984-01-10 Advanced Micro Devices, Inc. FSK Voiceband modem using digital filters
US4464766A (en) * 1982-04-29 1984-08-07 Autophon A.G. Radio transmission system for binary coded signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002013442A2 (fr) 2000-08-04 2002-02-14 Intellon Corporation Procede et protocole permettant d'assurer des intervalles sans conflit et une certaine qualite de service dans un reseau a acces multiple par detection de porteuse (csma)
EP1312185A2 (fr) * 2000-08-04 2003-05-21 Intellon Corporation Procede et protocole permettant d'assurer des intervalles sans conflit et une certaine qualite de service dans un reseau a acces multiple par detection de porteuse (csma)
EP1312185A4 (fr) * 2000-08-04 2009-09-09 Intellon Corp Procede et protocole permettant d'assurer des intervalles sans conflit et une certaine qualite de service dans un reseau a acces multiple par detection de porteuse (csma)

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