WO1987001207A1

WO1987001207A1 - Harmonic sampling logic analyzer

Info

Publication number: WO1987001207A1
Application number: PCT/US1986/001680
Authority: WO
Inventors: Curtis J. Blanding
Original assignee: Outlook Technology, Inc.
Priority date: 1985-08-23
Filing date: 1986-08-18
Publication date: 1987-02-26
Also published as: EP0235250A1; JPS63500676A; EP0235250A4

Abstract

A logic analyzer employs a phase locked loop (47, 49, 51, 53, etc.) adapted to be driven by a clock signal from a system under test in order to generate a sampling clock (45) that is synchronized in time relationship therewith and a selectable integer multiple in frequency thereof. The time relationship of the system and sampling clocks is controllable.

Description

HARMONIC SAMPLING LOGIC ANALYZER

Background of the Invention

This invention relates generally to digital signal sampling techniques, and more specifically to such techniques as implemented in logic analyzer instruments. Logic analyzer instruments are widely used to test and analyze the operation of digital circuitry by simultaneously acquiring a large number of logic signals at different points within the circuitry. An example of such digital circuitry is a portion of a mainframe computer. The logic analyzer instrument has a large number of conductors, such as 30-50, which are provided at their ends with individual connectors or probes for attachment to a different circuit point within the digital system being tested. Each such logic signal, of course, only has high or low voltage levels. Each is periodically sampled by the logic analyzer to determine whether high or low at each sample time, and this information is stored in a digital memory and used to reconstruct the waveforms on a cathode ray tube display for analysis by the technologist who is conducting the test.

A primary purpose of such test is to determine the relative time relationship of logic signals at the different circuit points to which the logic analyzer is connected within the system or device under test. That is, it is the relative times of the transition of the various logic signals between their high and low states that is analyzed. The determination of the interval between the time that certain of these acquired logic signals change state is useful in testing or evaluating digital hardware parameters, such as propagation delay, channel-to-channel-skew, setup time, and hold time. Another use for a logic analyzer is to record the states of various logic signals when certain input signals to the system under test are stable. Such logic signal state relationships, usually representing addresses or data words, are important in software analysis.

In any application, the logic analyzer has a finite memory which continually records samples of the logic signals being acquired until a triggering event occurs. Such a triggering event can be set to occur in response to a particular combination of the logic signals, some arbitrary time or event, and the like.

Present logic analyzers develop a sampling clock signal in one of two distinct ways. One way is simply to connect the instrument to the internal clock of the system under test, either by a direct connection or by deriving the clock from the acquired signals being analyzed. The logic signals are then sampled at a rate equal to the clock frequency of the system under test. The other way is to generate the clock signal within the instrument that is independent of and asynchronous with the clock of the system under test. In either case, the instrument can only determine for each logic signal acquired that a signal level has changed in an interval between two clock signal periods; that is, between the times of two samples. The higher frequencies now used in computer system clocks, and the current use of multiple phase clocks, require increased sampling rates in order to improve the resolution of the acquired information. The asynchronous technique has been utilized by in¬ creasing the frequency of the instrument's internal clock. This approach is, however, reaching the limit of the instrument's circuit speed, and requires a great deal of memory for a given duration of samples, which makes the instrument quite complex and expensive.

Therefore, it is a primary object of the present invention to provide an improved high speed digital sampling technique particularly adapted for use in logic analyzers that acquires all the necessary information but with reasonable speed and memory require¬ ments.

Summary of the Invention

This and additional objects are accomplished by the various aspects of the present invention, wherein, briefly, according to one aspect, the sampling is accomplished at a rate that is an harmonic of the clock of the system or device under test. Since^' the sampling period is synchronized with the system clock and thus with its logic signal transitions, the instrument sample clock does not have to have as high a frequency to give the desired information of the logic signal as would be required if the instrument sample clock were asynchronous and independent of the system clock. Thus, rather than using a brute force technique of increasing an instru¬ ment's internal asynchronous sample clock rate, a lesser frequency synchronous harmonic sample clock can be employed, thus reducing the complexity of the instrument and allowing the information to be obtained by an instrument that operates within the speed limitations of conveniently available circuit components. Conversely, a synchronous harmonic sample clock instrument operating at its maximum frequency to analyze a high clock rate system under test will provide results which are signi¬ ficantly more useful and accurate that corresponding results provided by an asynchronous sample clock instru¬ ment operating at the same maximum frequency. Moreover, the synchronous harmonic sample clock instrument will provide useful analysis of systems under test having significantly higher clock rates than a corresponding asynchronous sample clock instrument can successfully analyze. Further, synchronous harmonic sampling has an additional advantage over asynchronous sampling of per¬ mitting comparisons of recorded logic signals recon¬ structed from samples acquired at different times. According to another aspect of the present invention, the instrument's sampling clock may be shifted in phase relative to that of the internal clock of the system under test, while still being maintained synchro¬ nous with it. This allows adjustment of the sampling times to coincide with transitions in the level of logic signals being analyzed, thus allowing a determination of the times of such signals' transitions without having to have the extremely high sampling rate that is required in asynchronous instruments in order to provide anything like the same information.

Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of a preferred embodiment thereof, which description should be taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

Figure 1 illustrates, in block diagram form, a logic analyzer and an example of its use;

Figure 2 shows a number of waveforms of signals acquired by a logic analyzer being used as shown in Figure

1; Figure 3 is a block diagram of the logic recorder of the system of Figure 1;

Figure 4 illustrates details of one of . the circuit blocks of the system of Figure 3;

Figure 5 is a schematic diagram of one of the circuit blocks of Figure 4; and

Figure 6 illustrates a number of waveforms at different points within the system and circuits of Figures 3-5.

Description of a Preferred Embodiment Referring to Figure 1, a system under test 11 is any digital system or device whose logic signals are desired to be observed and/or recorded. An example of such a system is a large mainframe computer. A plurality of conductors 13 are connected between various circuit points of the system 11 and a logic recorder 15. Each of the conductors 13 is connected to a different circuit node of the system 11 and thus acquires a separate logic signal for analysis by the logic recorder 15. A logic recorder 15 embodying the various aspects of the present invention is described hereinafter with respect to Figures 3-6. Briefly, its purpose is to periodically sample each of the signals in the conductors 13 independently, and then to store those samples for later use in displaying and analyzing their relative timing. Most current logic analyzers are sold in the form of complete instruments, including keyboard inputs, cathode ray tube displays, and similar basic components. But the trend is to separate such instrumentation into two pieces. A first piece includes the circuits and systems that are peculiar to the specific testing function being performed. A second item is a general piece of equip- ment, such as a general purpose microcomputer, which can serve to perform basic control and processing functions for a number of specific testing instruments. Thus, the total cost of a number of specific instruments is reduced by sharing an available, general purpose computer or other piece of similar equipment to perform functions that are basic to the several instruments. Accordingly, in Figure 1, the logic recorder circuits 15 are those that are specific to the logic analyzer functions being performed, while those circuits are connected through a data link 17 to a general purpose computer 19. The computer 19 runs basic control and implementation soft¬ ware. The techniques of the present invention are involved in the logic recorder 15 portion of the system. The aspects of the present invention described below can also be implemented in a stand alone logic analyzer that includes a built-in keyboard, CRT display, and so forth, as well as the divided system illustrated in Figure 1.

Referring to Figure 2, a number of waveforms are shown in order to illustrate the degree of uncertainty that exists in logic signals reconstructed by a logic analyzer from its periodic samples. Figure 2(A) illus¬ trates a typical sampling clock signal 21 within the logic recorder 15. Samples of each of the signals in the individual conductors 13 are sampled once each clock period, on the leading edge of each clock cycle, as shown by the arrows. The sampling thus takes place at times tl, t2, t3, and so forth.

Figure 2(B) illustrates an example logic signal in one of the conductors 13 that changes from its low to its high voltage level sometime in an interval between signal times tl and t2, this interval being shown as a cross-hatched area 23. Figure 2(C) shows the acquired signal which will have that change at time t2, which is the next sample time after the signal changes states. The acquired signal will appear to be that of Figure 2(C) no matter when the actual signal of Figure 2(B) changes state within the interval 23. Similarly, a second example signal from a different one of the conductors 13 is illustrated in Figure 2(D), having, for this example, a change of state within an interval shown by a cross-hatched block 25 between sample times t2 and t3. The acquired signal, representing the actual signal of Figure 2(D), is shown in Figure 2(E) with its change of state occurring at the next sample time t3 after the actual signal of Figure 2(D) changes state.

The acquired signals of Figures 2(C) and 2(E) that are displayed for analysis will show their changes of state to have occurred one clock cycle apart, but, as can be seen by noting the relative positions of the intervals 23 and 25 of the actual signals, the leading edges of these actual signals can be anywhere in a range of from being practically together to nearly two clock periods apart.

It is this uncertainty and potential error which is desired to be reduced. One way to do so is to increase the frequency of the sampling clock of Figure 2(A) so that the regions of uncertainty 23 and 25 are reduced in absolute time duration, and thus to increase the resolution of the sampling system. This is the predominant approach in logic analyzers, being accom- pushed by increasing the frequency of an internal instrument sampling clock that is asynchronous with the clock of the system under test. The present invention departs from this approach, in two major ways. First, the sampling clock of Figure 2(A) is maintained synchro¬ nous with that of the system under test, but at a frequency that is an integer multiple (harmonic) of the system clock.

Thus, in the techniques of the present inven- tion, the sample clock frequency can be increased to the same limit that it can be increased to in a conventional logic analyzer, but it is unnecessary to increase the frequency as much as required in an asynchronous instru¬ ment to produce the desired result. This is because virtually all high speed digital systems are synchro¬ nously clocked from a master clock, and the logic signal transitions are therefore locked in phase with the master clock. Since the sample clock of the logic analyzer is also locked to the master clock of the system under test, each sample clock pulse of the logic analyzer has a definite, repeatable time relationship with each logic transition of the system under test. Secondly, the technique of the present invention allows the sample clock signal of the logic analyzer to be accurately and precisely positioned relative to the logic signals being analyzed, thus allowing the logic signal transitions to be specifically located by moving the sample points with respect to them. The result is a logic analyzer that can adequately analyze signals of the very high frequencies being employed in new generations of digital equipment, within the speed limitations of existing commonly used circuit elements and with a reasonable amount of memory being required. Figure 3 shows in block diagram form the major components of the logic recorder 15 of Figure 1. The system is controlled by a microprocessor 27 which communicates on an internal address/data bus 29 between the various functional elements of the system, including a memory 31. The individual logic signals in the conductors 13 are used in this embodiment to derive a clock signal ECLK in a conductor 33 from circuits 35. The individual logic signals are then passed through sampling circuits 37. The samples are continually recorded in a high speed memory 39 of finite length L. Each new set of samples, one sample from each input, replaces the set of samples recorded L+l sample intervals earlier, so that the memory 39 always contains L sets of the most recent samples, provided that the sampling process began at- least L sample intervals earlier. It is not unusual for the sampling period to last for several seconds, even though the memory 39 can only contain samples spanning the most recent microsecond, or less. When the trigger selections circuits 37 detect that the samples fit a preselected pattern, a trigger signal is sent in a line 38 to the control circuits 41 which halt the recording of samples into the memory 39, either immediately or a preselected number of sample intervals later. The samples in the memory 39 are then transferred to the host computer via the address data bus 29, the microprocessor 27, and the data link 17 for subsequent processing and display. The components of Figure 3 so far discussed are well known and used in this manner in existing logic analyzers. What is new in the system of Figure 3 is the clock generating circuits 43 which derive a sampling clock signal SCLK in a conductor 45 from the input system clock ECLK of the conductor 33. The clock generator of Figure 3 is shown in detail in Figure 4. The circuit of Figure 4 develops a sampling clock signal SCLK in the line 45, an example waveform of which is shown in Figure 6(H), from the external system clock ECLK in a line 33, an example of which is shown in Figure 6(A). The circuit not only increases the sampling frequency by an integer multiple of that of the system clock, but also allows the relative phase between the input and output signals of Figures 6(A) and 6(H), respectively, to be adjusted relative to each other.

A principal subsystem of the circuits of Figure 4 that allows a phase controlled harmonic clock signal SCLK to be developed is a phase locked loop circuit. Phase locked loops are used in a variety of circuit applications. The phase locked loop of the Figure 4 circuit includes a voltage controlled oscillator 47 that generates a series of pulses VCOO in a line 49, as shown in Figure 6(F). The frequency of this signal is determined by a voltage input through an active filter 51 from a phase comparator 53. The phase comparator 53 has two signal inputs which are compared. A first is a reference clock signal RCLK in a line 55 that is the output of a multiplexer (switch) 57. Figure 6(D) shows that signal when the multiplexer 57 is set to select an input line 59 that carries a delayed clock signal DCLK. The signal DCLK in line 59 is like the system under test clock signal ECLK in line 33, except it has been delayed a period D by a delay circuit 61. The second input to the phase detector 53, in a line 63, is a signal VCLK, as shown in Figure 6(E), which is an output of a dividing circuit 65 that is clocked by the VCOO output in line 49 of the voltage controlled oscillator 47. Thus, the phase of the voltage controlled oscillator 47 output VCOO is locked to that of the signal RCLK in line 55 but of a higher frequency depending upon the value Nl in the division circuit 65. The division circuit 65 is, in this example, a synchronous counter having a clock input C, a top count output TC and a preset enable input P. A pulse is emitted in the TC output when the top count of a preset number of clock pulses VCOO have occurred. That output is also connected to its input P, thereby causing the counter 65 to be preset to the designated number simultaneously with each TC pulse output. Thus, the top count (TC) output TCI is a series of pulses VCLK having a frequency that is that of VCOO, divided by Nl. The factor Nl is selected through control lines 67 which sets the preset count (P) to which the counter of the dividing circuit 65 is set upon occurrence of each VCLK pulse applied to its input P.

The intermediate clock signal VCLK is used to derive the desired output sampling clock SCLK by inter- action with two additional synchronous counters 69 and 77. The counter 69 receives at its initial count preset input (P) the train of pulses VCLK and is connected to provide a controlled delay in the occurrence of those pulses. The counter 69 is clocked by the voltage controlled oscillator output VCOO and thus generates a top count (TC) output pulse train TC2 in a line 71, as shown in Figure 6(G). The pulse output in line 71 is a replica of the input in line 63 except that it is delayed an integer number of VCOO periods N2. N2 is determined by the counter 69 preset signals in the lines 73.

The delayed pulses in line 71 are applied as one of two inputs to an OR gate 75 whose output is applied to a preset enable (P) input of the synchronous counter 77, acting as a dividing circuit, which is also clocked by the signal VCOO. Its top count (TC) output TC3 in a line 79 is the desired SCLK signal which is passed through a multiplexer (switch) 81. The line 79 is also connected as the second input to the OR gate 75. The circuit 77 divides the frequency of clock pulses VCOO by a factor N3, as set through control lines 83. Counter 77 is preset when a pulse occurs either in line 71 or line 79, to assure synchronization of the pulses in these two lines. Thus, the circuit of Figure 4 generates a pulse train SCLK in output line 45 with a frequency that is an integer multiple of that of the system clock ECLK input in line 33. This integer multiple is equal to the factor Nl divided by N2. The delay and relative phase- control of the

SCLK clock output is controlled by both the delay circuit 61 and the delay synchronous counter 69. The counter 69 provides a coarse adjustment of the delay factor, while the delay circuit 61 provides a fine adjustment of that delay. The counter 69 is adjustable to delay the clock pulses by multiples of the VCOO period, while the delay circuit 61 is designed to adjust that delay within about one period of the VCOO signal.

For this purpose, a preferred delay circuit 61 is an analog circuit illustrated in Figure 5. A digital- to-analog converter 85 is set to produce a constant current output in a line 87 whose value is set through control lines 89. An inverter 91 has a bipolar open emitter output connected to the line 87 and across a capacitor C. When ELCK 33 goes positive the base of this output transistor goes negative, and the capacitor C discharges linearally at a rate determined by the current in the line 87. A second inverter 93 is connected across the voltage VC of the capacitor C in a manner that its output is low while the voltage across the capacitor C is high, but then goes high when the voltage across the capacitor C decreases to a certain threshold amount. The amount of current in the line 87, as set through the digital to analog converter 85, thus determines the amount of delay D illustrated in Figure 6(B).

The settings for the digital-to-analog con¬ verter 85, the preset count of the counter 65, the preset count of the counter 69, the preset count of the counter 77, and the switch settings of the multiplexers 57 and 81, are stored in a number of registers 95 as digital words which are loaded through the internal address/data bus 29. The circuit of Figure 4 provides for additional, alternatives, one of which is to pass the input clock signal ECLK in line 33 directly to the output line 45 by selecting the alternative position of the multiplexer 81. This allows the system to be implemented with a synchro- nous instrument clock having the same frequency as the clock of the system under test. Also, through the alternate setting of the multiplexer 57, an internal oscillator 97 may be connected to drive the phase locked loop circuit, thus providing asynchronous operation at a frequency which is a multiple or submultiple of the internal oscillator.

An example set of parameters for the circuit of Figure 4 will now be given. The repetition frequency of the ECLK signal (fECLK) will be in the range of 0.4 MHz to 10 MHz. Therefore, the voltage controlled oscillator 47 is selected to have an output frequency (fVCOO) range slightly beyond 100 MHz to 50 MHz. Commercially avail¬ able VCOs tend to have a usable frequency range only slightly greater than 2 to 1. Counters 65, 69 and 77 have selectable ranges of Nl = 2 to 256, N2 = 2 to 256, and N3 = 2 to 128, respectively. When fECLK is at its minimum value, 0.4 MHz, Nl can be selected as any integer from 125 to 250, and a combination of Nl and N3 can be selected to make N1/N3 any desired integer in the range of 1 to 125. When fECLK is at its maximum value, 10 MHz, Nl can be selected as any integer from 5 to 10, and a combination of Nl and N3 can be selected to make N1/N3 any desired integer in the range of 1 to 5. The integer N1/N3 is the number of samples taken during each period of the external clock (ECLK) of the system being tested. The time interval between ECLK and the next sample clock (SCLK) can be set to within + or - 50 picoseconds of its desired value by selecting N2 and the 8 bit word which sets the current in line 87.

Although the various aspects of the present invention have been described with respect to a preferred embodiment, it will be understood that the invention is to be protected within the full scope of the appended claims.

Claims

IT IS CLAIMED;

1. An instrument adapted to simultaneously acquire a plurality of logic signals from a digital system under test, comprising: means responsive to a clock signal from the system under test for generating within the instrument a sampling clock signal having a frequency that is a multiple of said system clock signal and synchronized with it, and means receiving said plurality of logic signals and responsive to said sampling clock for acquiring data points of said logic signals at a rate determined by the frequency of said sampling clock signal.

2. The instrument according to claim 1 wherein said sampling clock generating means includes a phase locked loop driven by the clock signal from the system under test, thereby to generate said sampling clock signal.

3. The instrument according to claim 2 wherein said phase locked loop includes means for adjusting the phase of said sampling clock signal relative to that of said system clock signal.

4. The instrument according to claim 3 wherein said sampling clock generating means additionally in¬ cludes means in the path of said system clock signal for controllably delaying the system clock signal before driving the phase locked loop therewith, whereby the sampling clock is delayed in phase relative to said system clock an amount determined by both said phase locked loop phase adjusting means and said delaying means.

5. The instrument according to claim 1 wherein said sampling clock generating means includes means for adjusting the phase of said sampling clock signal relative to that of said system clock signal.

6. The instrument according to claim 1 wherein said sampling clock generating means is characterized by said frequency multiple being an integer.

7. An instrument adapted to simultaneously acquire a plurality of logic signals from a digital system under test, comprising: means responsive to a clock signal from the system under test for generating within the instrument a sampling clock signal synchronized therewith, means associated with said generating means for controlling a phase relationship of said clock signal relative to that of said system clock signal, and means receiving said plurality of logic signals and responsive to said sampling clock for acquiring datum points of said logic signals at a rate determined by the frequency of said sampling clock signal.