WO1986006186A1

WO1986006186A1 - Wafer scale integrated circuit

Info

Publication number: WO1986006186A1
Application number: PCT/GB1986/000211
Authority: WO
Inventors: Ivor Catt
Original assignee: Sinclair Research Limited
Priority date: 1985-04-15
Filing date: 1986-04-15
Publication date: 1986-10-23
Also published as: GB2174518A; GB8509632D0; EP0217905A1; GB2174518B

Abstract

An integrated circuit wafer comprises an array of chips (10A, 10B) provided with logic enabling the chips to connect up to each other under the control of commands sent along a forward path through the already connected chips and back through a return path. Growth is attempted in the directions NE, S, W and D, in turn where D is a diagonal direction which is NW for chips 10A and SE for chips 10B. Tests are made as each chip is added to the grown path. Defective chips are avoided by changing the growth direction to select another chip. In order to increase efficiency of growth to include all or virtually all good chips, a form of branching growth is permitted. Growth may take place in more than one direction from a single chip but the path of interconnection remains a single path. More particularly, when branching growth takes place from a chip, the return path thereto is directed into the forward path of another chip whose return path is directed into the return path leaving the chip from which the branching growth has occurred. The potential upstream chips and the potential downstream chips for any given chip from two mutually exclusive groups. For example a 10A chip has potential upstream chips in direction NE, S, W and NW but has potential downstream chips in directions N, E, SE relative to the 10 chip.

Description

WAFER SCALE INTEGRATED CIRCUIT

The present invention relates to a wafer scale integrated (WSI) circuit comprising a plurality of undiced and interconnected chips. A major problem in the way of attempts to extend integrated circuits from large scale integration (LSI) to WSI is the impossibility of producing perfect wafers. In the case of simple, highly regular LSI circuits, i.e. memory chips, it is well known to provide redundant memory cells which can be switched in in place of defective cells. Such an approach is not suitable for more complex circuits.

An alternative approach is described in British Patent Specification 1 377 859 (emanating from the same inventor as the present application). The wafer is formed with an array of undiced chips which include logic enabling the chips to be interconnected in a long spiral. At switch-on the spiral is grown in such a way as to avoid defective chips. A problem with the particular implementation described in GB 1 377 859 is that the grown spiral may reach an impasse (when the spiral has to be regarded as fully grown) while large numbers of good cells remain unused. In other words the growth mechanism is inefficient.

The present invention is concerned with improved architectures and control systems whereby more efficient growth mechanisms may be achieved.

Before defining the invention it is desirable to clarify various matters of terminology. A chip means one of the individual integrated circuits which are interconnectable by way of what will be called growth logic, to distinguish from the chips' function circuits which perform whatever are the intended storage and/or processing functions of the WSI circuit. The present invention is not concerned with the nature of the function circuits themselves. Examples are described in the aforementioned GB 1 377 859 and also in an improvement thereon GB 1 525 048.

Each chip comprises at least one set of chip terminals. There may be four such terminals identified as IN, OUT, RET and ROUT. IN receives signals from an upstream chip and OUT passes signals to a downstream chip. RET receives signals in the return direction from a downstream chip and ROUT passes signals in the return direction to an upstream chip. In practice there may be more than one set of chip terminals and RET and ROUT may coalesce into a single terminal.

As described in the aforementioned specifications there may be a

"fast line" and a "slow line" each passing through and returning through the interconnected chips. Each such line needs its own set of four chip terminals. In the more detailed description below it will be convenient to identify these as FIN, FOUT, FRET and FROUT for the fast line and SIN, SOUT, SRET and SROUT for the slow line.

In more generally terminology it may be said that there are sets of chip terminals of different kinds.

Each chip also comprises a plurality of sets of direction terminals, one set for every chip terminal. The direction terminals are the terminals connected to neighbouring chips. The growth logic is interposed between the chip terminals and the direction terminals which are so called because they are associated with directions to the connected neighbouring chips.

By way of example and explanation, the preferred embodiment of GB 1 337 859 uses the connection directions N, S, E, W between chips in a rectangular array and the set of direction terminals for FIN would, in the terminology of the present application, be FIN FROM S, FIN FROM N, FIN FROM W and FIN FROM E. The set of direction terminals for FOUT would be FOUT TO N, FOUT TO S, FOUT TO E, FOUT TO W and so on.

In order to reduce the risk of the spiral reaching an imposse, it is desirbale to maximize the number of possible directions in which the spiral may grow from the chip currently at the tip of the spiral.

It will thus be seen that the potential upstream chips for any given chip and the potential downstream chips for any given chip form two mutually exclusive groups.

The chips are preferably arranged in a rectangular array and the connection directions are a mixture of rectilinear and diagonal directions.

In GB 1 377 859 and 1 525 048, the group of potential upstream chips for any given chip is the same as the group of potential downstream chips. Accordingly, when a chip is added to the spiral, the group of potential downstream chips immediately loses one member. In the specific example described in detail in GB 1 337

859, the group is cut from 4 to 3 members. In the present invention the group remains intact. This leads to a greater probability of being able to continue growth if both the potential upstream and potential downstream chips are relatively large in number.

In a rectangular array, a chip has only 4 edge adjacent physical neighbours but it has 8 neighbours if diagonal adjacency is also permitted and it is possible to use mutually exclusive groups of 4 potential upstream chips and 4 potential downstream chips. Detailed examples are given below.

The growth logic permits a chip to be interconnected to more than one downstream chip but in such a way that the chip terminals of any one kind are all interconnected in one non-branching path. The growth pattern is branching but the fast line and slow line are non-branching.

Thus the single spiral growth of GB 1 377 859 is now converted into a form of branching growth but the chips nevertheless remain functionally in a single non-branching path (as distinct from tree structures such as are mentioned in a paper "An Approach to Highly Integrated, Computer-Maintained Cellular Arrays" F B Manning, IEEE Transactions on Computers Vol C-26 No 6 June 1977 pp 536-552). The branching growth greatly increases the chances of efficient usage of non-defective chips but the retention of a non-branching path maintains the simplicity of usage of the chips as in GB 1 377 859. Efficient usage is more likely firstly because there is less chance of the spiral getting "boxed in", so that growth is terminated prematurely, and secondly because it is not necessary to remove good chips from the path in the search for a usable avenue of growth. Both in this reference and in the present invention the chips are identifiable simply by their number, starting from the initial chip which is a physically identifiable chip (it may be called chip A) to which external connections are made. After this chip, chip 0 = chip A, the chips along the path are accessable as chip 1, chip 2 and so on, although there is no ready way of knowing the physical location of any chip other than chip A; such knowledge is not required to use the chain of chips along the path.

Consider the operation of the growth logic in GB 1 377 859 and in the present invention when chip (n) is making its first downstream connections to chip (n + 1), which is assumed to be in direction one = DIR1. The requisite connections to be set up on chip (n) are OUT connected to OUT TO DIR1 and RET FROM DIR1 connected to RET. Consider then when, in accordance with the present invention, connections are now to be made from chip (n) (not chip (n + 1)) to chip (n + 2), which is in direction two = DIR2. On chip (n), OUT remains connected to OUT TO DIR1 but RET FROM DIR1 is now connected to OUT TO DIR2 and RET FROM DIR2 is connected to RET.

It can be understood from this example that, although the growth has taken place in a branching manner, the functional path through the chips is a non-branching path identified by the sequential chip numbers (addresses) chip (n), chip (n + 1), chip (n + 2).

The way in which the growth is controlled is an extension of the techniques described in GB 1 377 859. In this reference a STEP command is addressed to the current last chip, chip (n), to cause it to connect to the next chip, chip (n + 1). A start is made with a particular connection direction and STEP is re-sent as necessary to try the connection directions in turn until a good chip (n + 1) is found. Each time STEP is re-sent it does not merely establish the connection in the new direction; it clears the previously established connection. In implementing the present invention, two addressed commands are used and these may be called STEP and OPEN. OPEN enables the next available connection direction, without clearing the previously established connection. STEP however acts as in GB 1 377 859 to establish the new connection and clear the previous connection.

Various strategies may be employed in controlling the growth. One possibility is for the first chip to try to make all its connections. If the possible next downstream chips are four in number, and there are no defects at this stage, the growth will immediately branch in four directions to create the chain chip (1) to chip (5). Next chip (2) tries all its possibilities, chip (3) tries all its possibilities and so on. The growth pattern will tend to spread out densely from the initial chip and this may be the most efficient way of ensuring that all or most good chips are used. However it may be difficult for the control circuit to work out efficiently the correct sequence of addressed OPEN and STEP signals to send.

An alternative is to follow the technique of GB 1 377 859 until an impasse is reached and then use OPEN to try a branch growth direction. This will tend to produce a spiky growth pattern which will eventually fill in the good chip areas efficiently. Algorithms for controlling the growth are reasonably simple and a detailed example is given below.

The invention will be described in more detail, by way of example, and with reference to the accompanying drawings, in which:

Fig 1 is a diagram of a block of chips with the potential connections therebetween.

Fig 2 illustrates the connection directions of a single chip from Fig 1.

Figs 3 and 4 illustrate the connection directions of alternative chips.

Fig 5 illustrates possible paths through a chip of the type shown in Fig 2.

Fig 6 is a block diagram of a chip.

Figs 7(a) to 7(c) shows examples of specific connections made within the chip of Fig 6, by way of the growth logic.

Fig 8 is a diagram of a first part of the growth logic of the chip.

Figs 9 to 11 show three embodiments of a second part of the growth logic.

Fig 12 is a diagram of a third part of the growth logic.

Fig 13 shows instruction decoding circuits of the growth logic.

Fig 14 is a diagram of a control chip connected to three further chips.

Fig 15 is a flow chart of a chip-addressing operation.

Fig 16 is a flow chart for control of the growth process.

Fig 17 shows a growth pattern created by the algorithm of Fig 16.

Fig 1 is a highly schematic representation of chips 10A and 10B in a rectangular array. The chips are of two different kinds, chips 10A and chips 10B, and the two kinds alternate along both rows and columns so that they form a chequerboard pattern - the 10A chips are "black squares" say and the 10B chips are "white squares".

The potential connections between chips in the direction of growth are represented by arrows in the directions W, S, NE and D. D stands for diagonal and is NW in the case of chips 10A but SE in the case of chips 10B. The D arrows are drawn heavily to emphasize that, unlike the other arrows, they alternate in direction. This is the difference between the two kinds of chips. As said above, the arrows represent connections in the direction of growth. Each such connection is actually two physical connections in the preferred embodiment, one for the fast line, one for the slow line, and is accompanied by return connections in the opposite direction.

So far as the growth pattern is concerned, as distinct from the connections which are the actual means of growth, growth from any given chip may always be to any one or more of W, S, NE and D (subject to obvious restrictions in the case of chips at the edge of the array). On the other hand a chip can be entered or grown into from a preceding chip in a single one of the directions from E, N, SW and from D. The two groups of 4 directions each comprise 2 rectilinear directions and 2 diagonal directions, one of which alternates between opposite directions (NW and SE) as between the two kinds of chips. This has been found to give good chances of efficient growth patterns. As an alternative, two fixed diagonal directions could be used and one of the rectilinear directions could alternate between the two kinds of chips. The four directions of each group are well spread over the compass. This is not essential and in some applications more tightly bunched groups may be employed in order to reduce interconnection distances and save on layout space and speed.

Fig 2 shows the connection directions for chips 10 (either 10A or 10B) the incoming and outgoing connection directions being shown at (a) and (b) respectively. Figs 3(a) and (b) similarly show bunched directions for different chips 11A. In order to avoid a strong directional bias across the wafer the chips 11A may alternate with chips 11B whose incoming and outgoing connection directions are shown in Figs 4(a) and (b).

Fig 5 illustrates various possible paths through a single chip 10A for a single line (i.e. the fast line or the slow line), the forward and return paths being both shown. At Fig 5(a) the chip is entered from the SW and exits solely to the NE. At Fig 5(b) the chip is entered from the SW and exits both to the NW and to the S.

Dotted line loops indicate the connections from the forward to the return paths via downstream chips and show that there is always a single continuous path. No example is illustrated of opening up to three directions but Fig 5(c) shows the chip when it has opened up to all four exit directions.

Fig 6 is a schematic block diagram of a single chip 10A or 10B, not intended to carry any implications as to chip layout in general or location of terminals in particular. The chip circuits consist of function circuits 12 and growth logic 13. Internally the chip has two sets of chip terminals 14 which are the means of communication with the function circuits themselves. The two sets serve the fast line and the slow line respectively and the terminals are those already identified above, namely:

FIN, FOUT, FRET, FROUT

SIN, SOUT, SRET, SROUT

Externally the chip has no less than 32 direction terminals 15, four for every chip terminal. These are all identified down the right hand side of the drawing. D meaning diagonal is to be interpreted as SE or NW as appropriate depending on whether the chip is a chip 10A or a chip 10B. The growth logic 13 establishes the connections between the chip terminals 14 and selected direction terminals 15 and also connections between pairs of direction terminals. Until a chip has opened up connections to a downstream chip, two connections 16 are made by the growth logic. These connect FOUT to FRET and SOUT to SRET to complete the fast and slow line paths.

Within the function circuits 12, data entering at FIN is processed and passed with minimal delay to FOUT as symbolized by a broken connection 17. Data entering at SIN is processed and passed with greater delay to SOUT as symbolized by a broken connection 18. It is assumed that no processing is effected in the return line and FRET is permanently connected to FROUT while SRET is permanently connected to SROUT, by connections 19. Accordingly RET and ROUT actually coalesce into one terminal, and this is in turn connected directly to all of the corresponding ROUT TO terminals. This is because the selection of the return path actually used is made by the RET routing in the upstream chip.

Permanent connections through OR gates 23 are also made on the input side between each set of IN FROM terminals and the corresponding IN terminal. This is perfectly satisfactory because, as explained below, the growth algorithm prevents a chip being entered from more than one upstream chip.

Fig 7(a) shows the connections which are effective when a chip has been entered from the SW but has not made connection to any downstream chip. The connections 16 remain, the IN terminals from SW are connected to the chip IN terminals (connections 20) while ROUT terminals to SW are connected to the chip ROUT terminals (connections 21). The fast and slow circuits of the function circuits 12 have been brought into the fast and slow lines respectively.

Fig 7(b) shows the connections established in the case of Fig 5(a). It can be seen that FIN FROM SW is connected via FIN, the fast line function circuitry and FOUT to FOUT to NE while FRET FROM NE is connected back via FRET, FROUT to FROUT TO SW. Similarly for the slow line.

Fig 7(c) shows the connections established in the case of Fig 5(b). FRET FROM NE is now passed to FOUT TO S while FRET FROM S is connected via FRET, FROUT to FROUT TO SW. Similarly for the slow line. Note the connections 24 between FRET/SRET FROM NE to FOUT/SOUT TO S.

The connections within the growth logic are made by way of various gates which are enabled by direction enable signals OPEN NE, OPEN S, OPEN W and OPEN D. OPEN NE means "enable the connections to the downstream chip in the NE direction", and so on. The four direction enable signals are provided by corresponding bistables 24 to 27. These, like a CLEAR bistable 28 are composed in conventional manner of cross coupled gates and the specific properties of bistable 28, formed of a NOR gate and an AND gate with inverted inputs, are as follows.

When the bistable is SET with its output equal to 1 = logical HIGH the state of the input marked A is immaterial. The state can only exist with the second input B = 0. B = 1 resets the bistable.

When the bistable is RESET (output = 0), so long as A = 0 the state of B is immaterial but with A = 1, the state can only exist with B = 1. B = 0 sets the bistable.

The A input of the bistable 28 is connected to a conventional hardware clear circuit comprising a differentiating circuit 29 connected to the power line V_dd. Although not shown in the drawings it will be appreciated that, as in GB 1 337 859, the wafer is traversed by grids of power supply and clock lines. The circuit 29 may be individual to the chip or one such circuit may be shared among a group of adjacent chips, e.g. a square of 4 chips. At switch-on, B = 0 and there is a 1 pulse on A, so the bistable sets to provide the signal CLEAR. This clears the chip circuits in general and ensures in particular that the bistable 24 to 27 are all reset.

Input lines 30 and 31 for the aforementioned pulse signals OPEN and STEP are connected to the direction enable bistables 24 to 27 through an array 32 of AND and OR gates. Small delays are inserted as needed and as indicated merely at one location 33, in accordance with conventional practice, for the avoidance of race-away conditions.

It is unnecessary to describe the gate array 32 in detail. It suffices to say that, as can readily be checked from the drawing, the first OPEN pulse will set the bistable 24, the second will set the bistable 25, and so on. A STEP pulse, however, will reset the last-set bistable and set the next. The first OPEN pulse resets the CLEAR bistable 28, thereby to remove inhibiting inputs from the AND gates of the direction bistables 24 to 27.

It is possible to set up the following combinations of direction enable signals:

OPEN NE

OPEN NE and S

OPEN NE, S and W

OPEN NE, S, W and D

OPEN S

OPEN S and W OPEN S, W and D

OPEN W

OPEN W and D

OPEN D

The way in which these enable signals are used will be described with reference firstly to Fig 9. Each of the signals enables a corresponding two AND gates 35, 36 and disables a third AND gate 37. These gates and OR gates 38 are so interconnected that FOUT is correctly routed, FRET is connected to the correct FRET FROM terminal and connections such as the connections 24 in Fig 7(c) are correctly made.

For example, if just OPEN NE is TRUE FOUT is connected to FOUT TO NE and FRET FROM NE is connected through a chain of gates to FRET. Thus the Fig 7(b) connections are set up. If both OPEN NE and OPEN S are TRUE, the AND gates marked with an asterisk are enabled; FOUT is still connected to FOUT TO NE but FRET FROM NE is now connected to FOUT TO S while FRET FROM S is connected through to FRET. This is as in Fig 7(c).

Fig 9 is drawn for the fast line. A duplicate circuit is provided for the slow line. A one-bit delay may be desirable at the output of each of the OR gates 38. In any event the simple, serially arranged circuit of Fig 9 introduces appreciable signal delays. More complex arrangements are possible which achieve greater speed at the expense of more gates and hence more chip area devoted to the growth logic.

Fig 9 has just 16 gates. Fig 10 shows a parallel logic circuit which reduces propagation delays but requires 29 gates. It can be checked by inspection that the various combinations of OPEN signals establish the required paths. For example, when both OPEN NE and OPEN S are true, gate 40 connects FOUT to FOUT TO NE, gates 41, 42 and 43 connect FRET FROM NE to FOUT to S, and gates 44, 45 and 46 connect FRET FROM S to FRET. Gate 46 is a final gate on FRET which is disabled by CLEAR. Such a gate may be included in Figs 9 and 11 also.

A one-bit or half-bit delay may be introduced at the intermediate point 59 in Fig 11.

Fig 11 is the preferred embodiment of the routing gates. It is a mixed serial-parallel circuit which only uses 18 gates but which reduces the maximum number of gates through which a signal has to pass appreciably. When only OPEN NE is TRUE gate 50 connects FOUT to

FOUT TO NE. Gates 51, 52, 53 and 54 connect FRET FROM NE to FRET.

When both OPEN NE and OPEN S are TRUE, gate 50 still connects FOUT to FOUT TO NE, gates 55, 56 and 57 connect FRET FROM NE to FOUT TO

S, and gates 58, 52, 53 and 54 connect FRET FROM S to FRET.

Connection routes consist of from 1 to 4 gates as against from 1 to

11 gates in Fig 9 and 1 to 3 gates in Fig 10.

The circuits described with reference to Figs 8 to 11 handle all of the switchable connections required in Fig 6 with the exception of the connections 16. These merely require AND gates 60 and 61 (Fig 12) which are enabled by CLEAR. The connections are therefore broken as soon as the first OPEN signal is applied to the circuit of Fig 8.

Fig 13 shows the fast line circuits symbolized by the broken line 17 in Fig 6, plus the OR gate 23. As previously mentioned the wafer is traversed by clock lines as well as power supply lines. Fig

13 shows a bit line 64 connected to a recycling binary counter 65 which establishes the fast line instruction cycle on each chip. The counter is connected to a decoder 66 which decodes various timing signals t_o, t_m, t_n etc of which to makes the start of the cycle, to is applied to two cascaded flip-flops 67 and 68 which have FIN applied to the second inputs. If a long chain of zero's is sent on the fast line, long enough to ensure that the counter will have clocked to the state decoded as t_o = 1, the counter will be cleared and held clear until the chain of zero's ceases, which marks the start of the fast line cycle.

The fast line circuits comprise a chain of four flip-flops 70-73 cascaded to form a shift register connected to an instruction decoder 74. FOUT is taken from the output of the first flip-flop 70. Among the instructions which can be decoded are STEP and OPEN. These are provided via AND gates 75 and 76 when these are enabled by t_n which marks the bit interval during which a complete four-bit instruction is in the shift register 70-73.

The AND gates 75 and 76 also required an enabling CHIP ADDRESSED signal. This is provided from the fast line circuits 17 essentially in the manner described in GB 1 377 859. The basic idea is to send an address number which is decremented by each chip through which it passes. The chip which receives address 0 (or, if preferred, the chip which creates address 0 by decrementing 1) is the addressed chip.

Fig 14 is a diagram showing a control chip 80 connected to a first chip, chip 0 and thence to chips 1 and 2. This is an early stage in the growth process. Fig 14 does not indicate physical locations of chips 10, nor which direction terminals thereof have been used in connecting them up, nor whether they are type 10A or type 10B. So far as the control chip 80 is concerned they are simply a series of chips identified by addresses 0, 1, 2. The fast and slow lines are shown going out through the chips and returning to the control chip, with the fast and slow circuits indicated at 17 and 18 respectively, as in Fig 6.

The control chip 80 may be on the same wafer as the chip 10 and is essentially a dedicated microprocessor which can send commands both on the fast line (to the circuits described above) and the slow line. As described in GB 1 525 048 the slow line circuits 18 can act as a simple serial processor and the commands sent down the fast line can include conventional elementary operations such as ADD, SUB, INC, DEC and so on. The commands include an address field, used as described below.

One of the commands sent along the fast line is a command to compare the address with 0 and, if there is no match, to decrement the address (and pass the command on). If there is a match, the chip 10 latches the aforementioned CHIP ADDRESSED signal. This is shown in the flow chart of Fig 15. A chip 10 is always addressed in this way before an OPEN or STEP command is sent thereto.

Fig 16 is a flow-chart showing how the growth of the path of interconnected chips is controlled by the control chip 80. This chip incorporates three counters:

X = DISTANCE TO BRANCH. This is the number of chips along the path to the point at which the growth is to branch, i.e. X is the address to use when a branch is made in the growth,.

Y = TOTAL LENGTH, i.e. Y is the address of the current last chip in the path. Z = NUMBER OF BRANCHES, that is to say the number of branches existing at the chip whereat branching is taking place.

The flow chart starts by clearing all the counters to zero, block 81. Then the current last chip is tested by sending various test routines thereto. These include a test of the status of the clear bistable 28 which should still be set. If it is not, the chip is already part of the grown path and cannot be re-entered, so the test routines fail.

Consider first what happens when the tests all succeed. Y is transferred to X so that the current last chip will become the potential branching chip, Y is incremented, Z is cleared and the command OPEN is sent to chip X, as shown in section 83 of the flow chart. Therefore the chip to the NE of chip X will become chip Y. this chip is now tested (block 82). Until a chip fails the tests, growth will take place in the diagonal NE direction.

When the test routines 82 are not successfully completed, a test 85 is made to see if Z is greater than or equal 4 to see whether there remains a possibility of growth from chip X. Assuming Z is less than 4, section 84 of the flow chart is followed whereby Z is incremented and a STEP command is sent to chip X. This opens up the next growth direction while closing the old. Thus, if growth has been proceeding NE, when such growth is halted, STEP causes an attempt to grow S, i.e. chip Y will be to the S of chip X. If necessary tries are made for the chip to the W and to D.

If all avenues fail, test 85 will be met (Z = 4) and X is decremented (block 86) ready to try branching back at the preceding chip. If the preceding chip in question is before chip 0 it is nonexistent and test 87 leads to termination of the growth process. If X is greater than or equal to 0, Z is incremented (block 88) and OPEN is sent to chip X (block 89). If chip X was already open just to the NE it will now open additionally to the S, so creating a branch in the growth pattern.

Fig 17 shows a nine by ten array of chips 10 including five chips which are defective. The control chip 80 of Fig 14 is connected to a particular one of the chips 10 identified by the numeral 0. It will be recalled that the order in which growth directions are tried is NE, S, W and D. (In fact D never has to be used in the example illustrated.) Growth occurred in the direction

NE from chip 0 through chips 1, 2 and 3. At chip 3 an abortive attempt to grow NE is made and successful growth is subsequently made in the direction S to chip 4, using the part 84 of the flow chart of Fig 16. More specifically, after the OPEN command has first been sent to chip 3, the tests 82 will fail becuase there is actually no chip to the NE into which to OPEN. Therefore a STEP command will have to be sent to chip 3 to cause the chip to step on instead to the S. Growth continues along these lines until chip 9 which will find that it can neither open to the NE or to the S, because of a defective chip to the S. Accordingly it eventually opens to the W because two STEP commands will have to be sent to it, after the initial OPEN command. Growth continues without further incident up until chip 42 which is completely boxed in by chips already in the path, namely chips 16, 17, 18, 19, 20, 39, 40 and 41.

After OPEN and three STEP commands have been sent to chip 42 and the test routines 82 are still failed, Z will have reached a count of four so X will be decremented and an attempt will be made to open additionally from chip 41. The algorithm of Fig 16 will cause Z to count up to four again because the chip 41 is also already boxed in.

X will be decremented again (block 86) and block 89 will cause the chip 40 to open up successfully to the W so that growth can now continue from the first branch point B1 through chips 43, 44 etc.

The remainder of the growth pattern can be followed through the numbered chips and branch points B2, B3 etc numbered in the order in which the branches occur. It will be seen that all 85 good chips have been included in the growth pattern.

In the algorithm of Fig 16, block 88 always sets Z to 1 although there will be occasions on which, because of an existing branch, Z should really be set to a higher number. The only consequence of this is that wasted attempts are made to branch from a chip from which branching is actually not possible. This adds to the time taken to grow the pattern which is regarded as an acceptable penalty to pay for the simplicity of the algorithm.

The time taken to grow the pattern can actually be quite long, taking perhaps 2 to 5 minutes from switch-on. This may not be acceptable for some equipment which the user expects to be functional virtually instantaneously. This problem may be overcome by providing the wafer with battery back-up (so that growth of the pattern only takes places on a fresh energisation, following switch-off not only of the mains supply but also of the battery supply). An alternative approach is to program the control chip 80 to memorise the pattern of OPEN and STEP commands used in creating the growth pattern at an initial switch-on. At subsequent switch-on times, this pattern of commands will be sent out without performing any tests on the assumption that a satisfactory pattern will again be achieved. A brief test sequence for the whole wafer may then be performed. On a failure, due to chip degradation for example, it will be possible to revert to the initial growth process, testing at every stage, in accordance with the agorithm of Fig 16.

Claims

1. A wafer scale integrated circuit comprising a plurality of undiced interconnected chips each provided with chip terminals connected to function circuits of the chip, direction terminals connected to direction terminals of other chips, and growth logic for effecting connections among the chip and direction terminals, characterised in that the chip-to-chip connections of the direction terminals are such that the potential upstream chips for any given chip and the potential downstream chips for any given chip form first and second mutually exclusive groups.

2. A wafer scale integrated circuit according to claim 1, characterised in that the chips are in a rectangular array and each said group of chips includes chips in both rectilinear and diagonal directions relative to the given chip.

3. A wafer scale according to claim 2, characterised in that chip-to-chip connections may be made between chips which are not physically adjacent.

4. A wafer scale integrated circuit according to claim 1, characterised in that the chips are arranged in a rectangular array and the chips to which any given chip may make connection include chips in both rectilinear and diagonal directions relative to the given chip.

5. A wafer scale integrated circuit according to claim 2, 3, or 4, characterised in that the chips are of first and second kinds, each chip of either kind having for edgewise neighbouring chips of the other kind, each first kind chip has two oppositely adjacent chips in first and second directions pertaining to the first and second mutually exclusive groups respectively, and each second kind chip has two oppositely adjacent chips in the first and second directions pertaining to the second and first mutually exclusive groups respectively.

6. A wafer scale integrated circuit according to any of claims 1 to 5, characterised in that the growth logic is capable of establishing connections such that a non-branching path through interconnected chips passes through a first one of the chips to a second one of the chips, returns to the first chip, passes thence to a third one of the chips and returns again to the first chip.

7. A wafer scale integrated circuit according to claim 6, characterised in that the chip terminals include at least one OUT terminal for extending the non-branching path to a next chip, and a RET terminal for receiving the path returning from a chip, the direction terminals include a set of OUT direction terminals and a set of RET direction terminals, and the growth logic is capable of assuming at least one first state in which the OUT terminal is connected to one OUT direction terminal and the corresponding RET direction terminal is connected to the RET terminal and at least one second state in which the OUT terminal is connected to one OUT direction terminal and the corresponding RET direction terminal is connected to a second OUT direction terminal and the RET direction terminal corresponding to the second OUT direction terminal is connected to the RET terminal.

8. A wafer scale integrated circuit according to claim 7, characterised in that the growth logic is capable of assuming a further state in which the OUT terminal is connected directly to the RET terminal.

9. A wafer scale integrated circuit according to claim 7 or 8, characterised in that the growth logic is capable of assuming a further state in which the OUT terminal is connected to one OUT direction terminal and the corresponding RET direction terminal is connected to a second OUT direction terminal and the RET direction terminal corresponding to the second OUT direction terminal is connected to a third OUT direction terminal and the RET direction terminal corresponding to the third OUT direction terminal is connected to the RET terminal.

10. A wafer scale integrated circuit according to any of claims 5 to 9, characterised in that the chips have fast and slow function circuits connected in fast and slow non-branching paths, each established by way of corresponding set of chip terminals and direction terminals therefor on each chip.,

11. A wafer scale integrated circuit according to any of claims 5 to 10, characterised in that each chip is capable of opening up connections in a plurality of predetermined directions to adjacent chips to include such chips as downstream chips in the non-branching path.

12. A wafer scale integrated circuit according to claim 11, characterised in that the plurality of predetermined directions of each chip are in a predetermined order and the growth logic is responsive to an OPEN command sent to that chip to cause the chip to open up to the next available predetermined direction and is responsive to a step OPEN command sent to that chip to cause the chip to open up to the next available predetermined directionand also to clear the previously established connection to a downstream chip.