WO1985000711A1 - Power metering system and method - Google Patents

Abstract

The metering system and method provides an electronic power meter for simultaneously producing digital pulse trains proportional to power and to VARS or Q. In the preferred embodiment, the metering system employs delta-minus-sigma modulation of the voltage signal which produces a modulated output signal used for gating the analog current signal, multiplying voltage and current. The product of voltage and current is then supplied to another delta-minus-sigma modulator (90), which serves as a convertor outputting a pulse train. The converter (90) produces separate pulse trains for each polarity of the power being measured. VARS or Q readings are produced by delaying the output of the modulator (30) by a selected amount to produce the necessary voltage lag, after which the delayed modulated signal is supplied to another multiplying gate. A second converter (90) is used to output VARS and Q. A metering method is also disclosed, as well as an offset compensation system (70, C1) for use with metering systems.

Description

Description

Power Metering System And Method

Technical Field

The invention relates generally to circuits for producing one or more signals proportional to power or to another selected measurement parameter, and more particularly to an improved power metering circuit and method which employs delta-minus-sigma modulation and an offset compensation system.

Background Art

Meters which accurately measure electric energy flowing on a line are an essential part of an electric utility system. The most common type of meter used by the electric utility industry today is the rotating disc meter, which in its basic form is accurate and reliable but provides only limited information to the utility about power usage. In addition to total power consumption in kilowatt-hours, utilities often need to measure other parameters to properly determine the cost of supplying certain loads. Some highly reactive loads, for example, are more expensive to supply because they induce a current/voltage phase mismatch known as power factor. To determine power factor, utilities have devised certain standard power measurements. Two widely used measurements are VARS (for reactive volt-amperes) and Q. Both are power measurements proportional to the product of line current and voltage, with the voltage phase lagging the current by 90" for VARS, and by 60° for Q. Together with overall power consumption, readings of VARS and Q allow the utility to measure power factor for which a penalty is usually charged. Another parameter of interest to utilities is polarity, or the direction of power flow, since some applications both consume power and feed power back into the distribution system. There is a continuing need in the electric utility industry for metering systems which are able to measure such parameters as VARS, Q and polarity, in addition to total power consumption.

Various electronic metering systems have been designed or proposed to replace the rotating disc meter. Examples of prior art electronic metering systems include those shown in the following patents: U.S. 3,875,508; U.S. 3,955,138 and U.S. 4,182,983. Those systems all employ modulators which produce a pulse-width modulated signal proportional to either current or voltage, and then use time-division or markspace multiplication, which gates or reverses the polarity of the other signal, to obtain a product signal. The product signal pulses vary in amplitude with respect to one analog value (current or voltage), and varies in width with respect to the other analog value. A low pass filter extracts the DC component of the product signal, which is proportional to power consumption. It would be advantageous to have a highly accurate metering system which is electronic and which is capable of producing power readings continuously in both kilowatt-hours and VARS or Q, at the lowest possible cost. It would also be advantageous if such a metering system could separately measure net power flow in each direction. The metering system should also be substantially free of errors due to voltage offsets in the active circuit elements. The system should therefore more advantageously include an offset compensation system which can economically compensate for errors in multiple amplifier elements. Disclosure of Invention

Accordingly, a metering system and method are provided for measuring electrical power carried on a line. The system includes means for monitoring current and voltage signals on the line. A first signal transducer produces a first analog signal proportional to one of the current and voltage signals and a second signal transducer produces a second analog signal proportional to the other of the current and voltage signals. A modulator modulates one of the analog signals to produce a first modulated signal which is changeable between two levels at predetermined first clock intervals, such that the first modulated signal has an average level over any sufficient interval proportional to the selected one of the analog signals. First multiplying means are provided to gate the other of the analog signals in response to changes in the level of the first modulated signal, multiplying the analog signals together, to produce a product signal which is proportional to the power transported on the line. A convertor then converts the product signal to a first output signal which in the preferred embodiment is changeable between two levels at predetermined convertor clock intervals in a manner which is proportional to the product signal and to the power carried on the line.

The preferred metering system of the present invention includes a convertor which separately measures the power at each polarity on the line and includes digital means for changing the phase relationship between the analog signals to produce a product signal proportional to a selected phase relationship power value, such as VARS or Q. The system also includes an offset compensation system which corrects for voltage offsets in the various operational amplifiers of a metering system to eliminate offset errors and provide high accuracy. The offset compensation system described will correct for voltage offset between the inputs of N amplifier elements. The offset compensation system includes N offset storage elements which are connected respectively to one input of each of the amplifier elements for receiving a compensating voltage which substantially reduces the offset error at the other input of the amplifier element. Any difference between the compensating voltage and the voltage offset of the amplifier element is termed an error voltage, which appears at the other amplifier input. The system includes a nulling circuit which can be connected sequentially to each of the N amplifier elements and to the offset storage element associated therewith so that each of the amplifier elements sequentially becomes the selected amplifier element being offset compensated. The nulling circuit first is connected to the other input of the selected amplifier element during an intermittent transfer period to determine the error voltage. Then the nulling circuit is connected to the offset storage element connected to the one input of the selected amplifier element during an intermittent charging period which follows the transfer period. The offset compensation system includes means for sequentially providing the transfer and charging period for each of the N amplifier elements such that offset errors in the metering system are substantially eliminated.

Brief Description of the Drawings

FIG. 1 is a schematic block diagram of a metering system for measuring power on a line according to the present invention. FIG. 2 is a schematic circuit diagram of the first modulator portion of the metering system shown in FIG. 1.

FIG. 3 is a schematic circuit diagram of the first output convertor portion of the metering system shown in FIG. 1.

FIG. 4 is a series of graphical illustrations, designated FIGS. 4a through 4g, showing certain selected internal and output signals produced during the operation of the metering system of FIGS. 1 through 3.

FIG. 5 is a series of graphical illustrations, designated FIGS. 5a through 5i, showing various internal and output signals produced by the convertor of FIG. 3, during the measurement of signals of different polarities.

FIG. 6 is a schematic circuit diagram of an alternative embodiment modulator for use in the subject power metering system which provides a phase lead in the modulated output signal.

FIG. 7 is a series of graphical illustrations, designated FIGS. 7a through 7g, showing certain selected internal and output signals produced by the FIG. 6 modulator. FIG. 8 is a schematic block diagram of a metering system according to the present invention which includes apparatus for producing measurements of VARS and Q.

FIG. 9 is a schematic diagram of a signal multiplier which can be used in the metering system of FIG. 8 and which includes digital circuitry for phase adjustment to enable the production of VARS and Q measurements.

FIG. 10 is a series of graphical illustrations, designated FIGS. 10a through 10h, showing certain selected internal and output signals produced in the FIG. 9 multiplier.

FIG. 11 is a schematic diagram showing further details of the digital phase adjustment circuitry of FIG. 9.

FIG. 12 is a series of graphical illustrations, designated FIGS. 12a through 12d, showing a selected phase adjustment of a modulated signal produced by the multiplier of FIG. 9. FIG. 13 is a schematic diagram of one embodiment of a voltage offset compensation system for use in the present invention.

FIG. 14 is a graphical illustration of the change in error voltage produced by the FIG. 13 compensation system.

FIG. 15 is a schematic diagram of a voltage offset compensation system of the type shown in FIG. 13 for an entire power measuring system.

FIG. 16 is a timing diagram illustrating the operation of the offset compensation system of FIG. 15.

FIG. 17 is a schematic diagram of a second embodiment modulator for use in the FIG. 1 power measuring system.

FIG. 18 is a series of graphical illustrations, designated FIGS. 18a through 18e, showing various signals produced by the FIG. 17 modulator.

FIG. 19 shows the FIG. 17 modulator with an alternative embodiment voltage offset compensation system. FIG. 20 is a timing diagram showing the control signals for operating the voltage offset compensation system of FIG. 19.

FIG. 21 is an alternative embodiment of a modulator for use with the FIG. 1 measuring system which includes voltage offset compensation circuitry. FIG. 22 is a timing diagram showing the control signals for operating the offset compensation system of FIG. 21.

FIG. 23 shows an alternative embodiment modulator and associated dual polarity output circuitry.

FIG. 24 is a series of graphical illustrations, designated FIGs. 24a through 24j, showing various signals produced by the FIG. 23 modulator and associated output circuitry.

Best Mode For Carrying Out The Invention

Referring to FIG. 1, the metering system of the present invention is schematically illustrated as a means for measuring the electrical power carried on a power line 10, from a source 12 to a load 14. The current on line 10 is indicated generally as I_L, and the voltage as V_L. The system includes a signal monitoring and conditioning means such as transformers 16 and 18, for monitoring V_L and I_L, respectively. Transformer 16, designated the first signal means, produces a first analog signal I_A1 proportional to V_L on line 20. Transformer 18, designated the second signal means, produces a second analog signal I. proportional I_L on line 22. A shunt resistance 24 is connected across the secondary winding of transformer 18, through which most of the current on line 22 flows. Shunt resistance 24 provides a low impedance current path and may be selected to control the overall range of the current signal I_A2 on line 22.

The metering system and method of the present invention operates to multiply together the first and second analog signals I_A1 and I_A2, carried respectively on lines 20 and 22, and then to convert the multiplied product signal to a suitable digital form. Broadly, this is accomplished by modulating one of the signals and then gating, or switching, the other of the signals to yield a composite or product signal having an average value proportional to power. It will be understood by those skilled in the art that either the current or voltage could be modulated, and the resultant modulated signal used to gate the other of the two analog signals, to produce the product signal. Accordingly, the designation of the first and second analog signals as the voltage and current signals, respectively, could be reversed without altering the fundamental operation of the metering circuit shown in FIG. 1. Similarly, the designations for the first and second signal monitors could likewise be reversed.

The metering system provides a multiplying means for multiplying signals I_A1 and I_A2 together to produce a product signal which is proportional to the power transported on the line. To provide the necessary multiplication, the voltage signal I_A1 is first supplied to a first modulator circuit 30. Modulator 30 constitutes a modulator means for converting the analog voltage signal I_A1 to a first modulated signal, which is changeable between two levels at predetermined clock intervals. In accordance with the principles of delta-minus-sigma modulation, the first modulated signal output has an average level over any sufficient interval which is proportional to the first analog signal supplied to modulator input 32.

Referring to FIG. 2, the analog (voltage) signal I_A1, is supplied to a summing node 36, through an impedance 38. Modulator 30 includes modulator feedback means for producing a feedback signal I_F, which is also supplied to summinq node 36. I_F is controlled by the modulator output, called the first modulated signal, which appears on line 34. One or the other of a pair of reference sources V1+ and VI- are alternately connected to summing node 36 through an impedance 40 in response to the level of the first modulated signal. Feedback signal I_F switches between the positive and negative reference sources in a manner which balances the first analog signal I_A1 over time. Instantaneous differences between I_F and the first analog signal result in a difference signal l_diff out of summing node 36. The instantaneous difference between the input and feedback signals, namely l_diff is integrated and measured by a modulator measuring circuit 42.

Measuring circuit 42, includes an active integrator having a capacitor 44 as the feedback element of an inverting operational amplifier 46. The signal at amplifier output 48 ramps up or down, depending on the polarity of l_diff. The integrated signal at 48 is compared against a modulator threshold level by a comparator 50, which goes high when the signal is above the modulator threshold level and low when the signal is below the modulator threshold level. The output of comparator 50 is supplied to the D input of a modulator bistable circuit 52. The Q output of bistable circuit 52 is the first modulated signal. Bistable circuit 52 changes only at predetermined first clock intervals which are determined by an external clock. A suitable clock for this purpose is provided by a conventional oscillator 54 and frequency divider circuit 56, shown in FIGS. 1 and 2. For simplicity, the time interval between the pulses produced by frequency divider 56 will be referred to as the first clock. Bistable circuit 52 has a Q output as well as Q, with Q being the inverse of Q. Both the Q and Q outputs are used to control feedback signal I_F by operating a pair of switches 58 and 60, respectively. Since Q and Q are understood to be the inverse of one another, only the Q output is referred to herein as the first modulated signal. It should be understood. however, that both the Q and Q outputs contain the information represented by the term "first modulated signal", and line 34 designates the lines carrying both the Q and Q signals. Because the first modulated signal is output through bistable circuit 52, the first modulated signal on line 34 is changeable between two levels at the predetermined first clock intervals. Although the level may not change at each clock interval, the modulator circuit provides that when the first modulated signal does change levels, such change occurs only at the predetermined first clock intervals, and at no other times. Changes between the high and low levels of the first modulated signal produce simultaneous switching of switches 58 and 60, and corresponding reversals in the polarity of feedback signal I_F to summing node 36. As the integrated difference signal ramps either up or down across the threshold level of comparator 50, changes in the level of the output of the comparator are produced. At each clock interval, bistable circuit 52 determines whether the output of comparator 50 has changed, and if so, produces a corresponding change in the Q and Q outputs. The magnitude of the analog input signal causes a direct proportional change in the amount of time the first modulated signal is at a given level. Consequently, the first modulated signal has an average level or amplitude which lies either at or between its two levels and, over any sufficient interval, such average amplitude is porportional to the analog input signal.

As an example of the operation of modulator 30, if the input signal at input 32 is zero, the Q output of bistable circuit 52 will be high exactly the same amount of time it is low, producing an average level exactly midway between the high and low levels of Q. If the inputs signal, at input 32 has a positive value, the positive current into summing node 36 must be balanced by a larger negative current supplied to the summing node by negative reference VI-, through switch 58. Consequently, Q will be low proportionately longer than it is high and switch 58 will be closed and switch

60 will be open a greater amount of time than vice versa. If the input signal is negative, the positive feedback reference will need to be supplied more of the time in order for I to balance the input signal, and Q will be high more than it is low. It is a feature of the modulator of the present invention that Q can remain high or low for however long it takes I_F to balance the input signal at the summing node. To produce a current signal for multiplication with the modulated voltage signal, the system includes means for providing inverted and non-inverted representations of the line current I_L. Referring to

FIG. 1, the current analog signal I_A2 is first supplied to a gain amplifier 70, after which the signal is supplied to a signal inverter circuit 72. The illustrated inverting circuit includes an operational amplifier 74 and gain setting resistors 76 and 78. The amplified signal I_A2 is supplied to the inverting input of amplifier 74, which is configured to produce a gain of -1. The inverted signal is then supplied to one of two switches, which together form first gating means 80. The inverted signal goes to switch 82, and a second line 84 carries the non-inverted amplified signal, I_A2 ^to switch 86. It will be understood that a suitable center tap transformer could be used in place of second transformer 18, in which case the signals to switches 82 and 86 could be supplied directly from the transformer. The Q and Q outputs of modulator bistable circuit 52 are used to operate switches 82 and 86, to gate the second analog signal I_A2 in response to the first modulated signal. Since Q is the inverse of (2, switches 82 and 86 are switched in alternate fashion, such that the output of gating means 80, at 88, is an analog signal switched in a modulated manner between positive and negative polarities. Such a gating operation is generally termed time division or amplitude-markspace modulation. Switches 82 and 86 accomplish the multiplication of the two analog signals representing the current and voltage of the power carried on line 10. The resultant signal, termed a product signal, appears at first gate output 88, and is proportional to the power carried on power line 10.

As shown in FIG. 1, the product signal output from the first gating means is supplied to a first convertor circuit 90. The convertor circuit converts the product signal to a first output signal, on line 92, which is changeable between the two levels at predetermined convertor clock intervals in a manner proportional to the product signal. Convertor 90 operates essentially as a low pass filter which extracts the DC component or average value of the product signal. The resultant first output signal is proportional to the power carried on line 10. Referring to FIG. 3, convertor 90 is essentially a delta-minus-sigma modulator of a type similar to modulator 30, which is designed to produce separate modulated output signals proportional to each polarity of the input signal. To simplify the description, convertor 90 and its operation will initially be described with respect to a first polarity of operation. The components within box 94 encompass all the elements used in single polarity operation. In the following example it will be assumed that the product signal to be converted is predominantly positive, which will be assumed to correspond with power flow on line 10 from source 12 into load 14. As in the modulator 30, the input signal to convertor 90, designated I (product signal), is initially supplied to a summing node 96 through an impedance 95. A feedback means supplies a second signal I₂ to the summing node from one of a plurality of reference sources. For positive polarity operation, the reference sources will alternate between a negative reference source 98 (VR-), supplied through a switch 100, and a ground connection 102, supplied through a switch 104. Since only positive values of the product signal are being considered, switching I between ground and a negative value will be sufficient to balance the product signal at summing node 96, over time. As previously described for modulator 30, any difference between product signal I_p and I₂ is a difference signal, which is supplied to a measuring circuit 106. The measuring circuit integrates the difference signal and compares the difference signal to a first threshold level. The preferred embodiment measuring circuit shown in FIG. 3 includes an active integrator 107 consisting of amplifier element 108, and a capacitor 110 as a feedback element. The voltage at amplifier output 112 ramps upward or downward, depending on the polarity of the difference signal at summing node 96. The integrated difference signal at 112 is supplied to a first comparator 114, which has a threshold set at a selected first threshold level. When the integrated difference signal at 112 is above the first threshold level, the output of comparator 114 is high. When the integrated difference signal is below the first threshold level, the output of comparator 114 is low.

The comparator output, termed a first control signal, is supplied to the D input of a bistable circuit 118, by way of line 116. The Q output of bistable circuit 118 is changeable only, at predetermined convertor clock intervals, which are preferably longer than the first clock intervals for modulator 30. The convertor clock intervals can be produced by adding a second frequency divider 120 to first clock 56. The time intervals between the pulses produced by frequency divider 120 will be referred to as convertor clock intervals, and the frequency divider will be referred to as the convertor clock. The Q output of bistable circuit 118 is the first output signal, which controls switches 100 and 104 to determine the operation of the feedback system which supplies second signal I₂ to summing node 96. Switch 104 is operated through a gate 122, which outputs a high signal to close the switch only when both inputs 124 and 126 are low. Gate 122, as shown, is a conventional negative AND gate. During periods of positive product signals, input 126 will remain low, as will be described below. Consequently, whenever Q is high, switch 100 is closed, connecting VR- to summing node 96, and when Q is low, switch 100 is open and switch 104 is closed.

The operation and method of the metering system of the present invention will now be described with reference to FIGS. 1-4. For simplicity, it will be assumed that power on line 10 flows predominantly in the positive direction. The voltage on line 10 is shown in FIG. 4a as a sinusoidal AC waveform. Current I_L is shown in FIG. 4f as an increasing value, represented by curve 128. The first step is for transformers 16 and 18 to monitor the current and voltage signals and to produce analog signals I_A1 and I_A2, which are proportional to line voltage and current, respectively. One of the analog signals, voltage signal I_A1 in the preferred embodiment, is then supplied first to first modulator 30. Fig. 4c shows the integrated difference signal produced within modulator 30 by the delta-minus-sigma modulation technique described above. The integrated difference signal is supplied to measuring circuit 42. Fig. 4b illustrates the first clock intervals produced by first clock 56. As can be seen, the slope of the integrated difference signal in FIG. 4c changes only at the predetermined clock intervals determined by the first clock signal. Since bistable circuit 52 clocks on the leading edge of each upwardly moving pulse, the predetermined first clock intervals are shown to begin at the points identified as a, b, c, d, etc. in FIG. 4b. The integrated difference signal is then supplied to comparator 50. Line 130 in FIG. 4c represents the modulator threshold level in comparator 50. Note that the integrated difference signal reverses slope at the beginning of each clock interval after threshold 130 has been crossed. The output of comparator 50 is shown in FIG. 4d. Whenever the integrated difference signal is below threshold 130 the comparator output is low and when the integrated difference signal is above threshold 130 the comparator output is high. The comparator output is then supplied to the D input of bistable circuit 52, which produces the Q, or first modulated signal output, illustrated in FIG. 4e. The Q output is the result of modulating the voltage signal and is changeable between two levels at the predetermined first clock intervals.

Because the bistable circuit is changeable only at the predetermined clock intervals shown in FIG. 4b, the changes in Q slightly lag changes in the comparator output shown in FIG. 4d. Depending on the level of accuracy required in the signal multiplication system, it may be desirable to compensate for the slight lag in the modulated signal introduced by bistable circuit 52. Such correction can be accomplished by inserting an RC network in line 20 to introduce a small.phase lead in signal I_A1 as it enters modulator input 32. Another technique would be to induce a slight lag in the current analog signal I_A2 A tnird alternative, utilizing a delta-minus-sigma modulator having digital phase lead circuitry will be subsequently described. The phase adjustment introduced, which will only be a fraction of one first clock interval, should be the average of the delay induced by the lag of Q relative to the comparator output.

FIG. 4f illustrates equal and opposite analog signals proportional to line current I_L. Line 128 is representative of a growing current signal and line 129 is the inverse signal produced by inverter 72. The next step is to gate the current analog signal using gating means 80. The output of gating means 80 is the product signal, curve 131, shown in FIG. 4g. Curve 131 is generated by switching between signals 128 and 129, in response to the first modulated signal shown in FIG. 4e. The average level or DC component of curve 131 is represented by line 132 of FIG. 4g.

In the example given, power is assumed to be flowing predominantly in one direction, into load 14. Consequently, the product signal 131 shown in FIG. 4g is predominantly of a positive polarity, represented by line 132. It will be assumed, for the purpose of describing the operation of convertor 90 below, that the product signal has a predominant and average value which is positive. Although the actual polarity of the product signal is a matter of design choice, the product signal will be predominantly of a first polarity when power on line 10 is of a first polarity, with power flow in one direction, and will be predominantly of a second polarity when power on line 10 is of a second and opposite polarity, with the power flowing in the other direction. The next step is to convert the product signal I_P to a first output signal changeable between two levels at predetermined intervals in a manner proportional to I_P. Reference will be made to FIGS. 3, 4 and 5. P Product signal I_P, as shown in FIG. 4g, is supplied to convertor 90. Both I_P and second signal I₂, are supplied to summing node 96, where the instantaneous difference is integrated in integrator 106. The time constant of integrator 106 is selected to be long in comparison to the switching frequency of first modulator 30. Converter 90 can therefore act as a low pass filter, responding only to the DC component, or average value, of product signal I_p. For this reason, I_P is depicted in FIG. 5a as a smooth analog curve, although it will in fact vary in the manner shown in

FIG. 4g. FIG. 5a shows only the average value of I_P.

The time scale of FIG. 5a is considerably compressed, compared with the scale in FIG. 4g. For the purpose of illustration, it will be assumed that interval 134 of FIG. 5a is equivalent to the entire length of curve

132, shown in FIG. 4g. FIG. 5b shows the convertor clock intervals produced by clock 120.

Considering only positive power flow, illustrated between t₀ and t₁, in Fig. 5a., integrator 106 will output an integrated difference signal (IDS) as shown in FIG. 5c. The integrated difference signal ramps up and down around the first threshold level TL1 of comparator 114. The integrated difference signal (IDS) is supplied to comparator 114, where it is compared to first threshold level TLl. Comparator 114 outputs a control signal 133 on line 116 as shown in FIG. 5d.

The next signal generated is the first output signal shown in FIG. 5e, which is output through bistable circuit 118. Control signal 133 changes levels depending on the level of the integrated difference signal relative to threshold TLl. When IDS is above TLl, signal 133 is high and when IDS is below TLl, signal 133 is low. The next step is to output the first output signal shown in FIG. 5e through first bistable circuit 118. The first output has an average level proportional to a first polarity of power on line 10 over any sufficient interval. It is changeable only at the predetermined convertor clock intervals illustrated as w, x, y and z in FIG. 5b.

Single polarity operation of convertor 90 involves switching the feedback signal I between first reference source 98 and a second reference source 102, depending on the level of the first output signal (FIG. 5e). Since the second reference source 102 is a ground connection, the portion of convertor 90 thus far described will not accommodate negative power flow on line 10. When power flow (I_P) goes negative, as it does between times t₁ and t₂ in FIG. 5a, additional circuitry in convertor 90 is employed. Referring to FIG. 3, convertor 90 includes a second comparator 140 which receives the output of integrator 107.

Comparator 140 has a second threshold level TL2 which is different from the first threshold level of comparator 114. The threshold levels should be set far enough apart to accommodate the widest anticipated variations in the integrated difference signal output from integrator 107, without crossing the threshold levels of both comparators simultaneously. The integrated difference signal is supplied to the non- inverting input of comparator 114 and to the inverting input of comparator 140, so that their outputs will be of opposite polarity. The output of comparator 140 goes high when the integrated difference signal is below the second threshold level in comparator 140 and goes low when the integrated difference signal is above the second threshold level in comparator 140. The output of comparator 140 is supplied to the D input of a second bistable circuit 142. Second bistable circuit 142 outputs a second output signal from its Q output. The second output signal is at one of two levels, depending on the level of the integrated difference signal relative to the second threshold level at each of the convertor clock intervals. The second output signal is supplied to input 126 of negative AND gate 122 and to a switch 146 for connecting a third reference source VR+ to summing node 96. The feedback signal I₂ is thus governed by the level of the second output signal, which has an average level proportional to the second polarity power carried on power line 10. Second polarity operation of convertor 90 will be described with reference to FIGS. 3 and 5. After time t₁ the direction of power flow reverses and product signal I_P begins drawing charge from summing node 96. Referring to FIG. 5c, just prior to time t₁ the integrated difference signal is descending, meaning that the negative reference source VR- is connected to the summing node through switch 100. At the clock pulse following the crossing of the first threshold level TLl, switch 100 will open and switch 104 will close, connecting the summing node to ground. Since the product signal I_P is negative after t₁, the integrated difference signal will continue integrating downward until reaching the second threshold level TL2 of comparator 140, when its output 135 will go high (see FIG. 5g). At the next comparator clock interval after convertor 140 goes high, the Q output of bistable circuit 142 (the second output signal) will go high, as shown in FIG. 5h. When the second output signal goes high, a switch 148 connected to third reference source 146 (VR+) is closed. The third reference source supplies a positive current I₂ to summing node 96 to counterbalance the negative product signal I_P and drive IDS back across TL2. When TL2 is crossed, signal 135 again goes low, causing the second output signal to go low at the next clock interval. During second polarity operation the first output signal (FIG. 5e) remains low and, whenever the second output signal (FIG. 5h) is low, both inputs to gate 122 are low and its output goes high. When the output of gate 122 goes high, switch 104 is closed and the ground connection reference source 102 is connected to summing node 96. When switch 104 is closed, IDS is allowed to recross TL2 in the other direction. During the interim between times t₁ and t₂, when the power flow is negative, the integrated difference signal is maintained in the vicinity of second threshold level TL2.

The convertor 90 shown in FIG. 3 is provided with three different reference sources, the second of which is a connection to the common ground for the metering circuit. Because of the configuration of circuit elements, the ground connection is used whenever the integrated difference signal is in the region between the first and second thresholds TLl and TL2. It is not essential that the second reference source be a ground connection. Separate positive and negative reference sources could be used for each polarity of operation, if desired. In such a case, the first and second reference sources would be used to supply the second signal I₂ to summing node 9^6 when the product signal I_P is of a first polarity and separate third and fourth reference sources could then be used to supply the second signal I₂ to summing node 96 when product signal I_P is of the other polarity. In practice, the selection of the values for the reference sources is governed by the necessity of maintaining the integrated difference signal in the vicinity of the threshold level of the comparator in use. The magnitudes and polarities of the reference sources are otherwise entirely a matter of design choice.

Using reference sources in converter 90 which include at least one ground connection improves the overall accuracy of the modulated signals output.

While variations may occur in the positive and negative voltage reference sources, the ground connection remains fixed. If one or both of the positive and negative reference sources is above or below its correct value, an error will be at one level slightly longer or shorter than it should be, since during the time the voltage reference source supplies the feedback signal it will supply slightly too much or too little current. The closer the input signal is to ground (zero) the smaller will be the error. Equal and opposite reference sources, such as those used in the feedback system of modulator 30, have a greater potential for error if there is mismatch between the reference voltages V1+ and VI-. Since the feedback system of modulator 30 always switches between V1+ and VI-, any error resulting from a reference voltage mismatch will tend to cause the modulated output to be at one or the other level an incorrect amount of time regardless of the magnitude of the input signal. This does not present a problem in the case of modulator 30 because it is modulating the line voltage signal, which generally varies by only a small amount. Accuracy, therefore, need only be maintained over a narrow range. Converter 90, however, requires greater accuracy because of the wide variations in the product signal representing line power. For this reason, the separation of the convertor operations between positive and negative polarities of power has distinct advantages. Since only one polarity is measured by each comparator, the reference sources can use a ground connection to provide the feedback signal, improving overall convertor accuracy. The information provided about power flow of each polarity is also desirable since it provides additional data about the nature of the load and its power requirements. The first and second output signals output on lines 92 and 144 from convertor 90 (see FIG. 1) are changeable between two levels at the convertor clock intervals. To provide a suitable digitized output in which pulse density is proportional to power flow, a system for converting the output signals to pulse trains is provided. Referring to FIGS. 1 and 5, the first and second output signals are supplied to respective first and second AND gates 150 and 152. A second input to the AND gates is supplied from convertor clock 120. FIG. 5f shows the pulse train produced for first polarity power from AND gate 150. The pulse train has a pulse density proportional to the magnitude of power flow in one direction on line 10. Similarly, for power flow in the opposite direction, FIG. 5i shows a pulse train for second polarity power from AND gate 152. Various means are available for processing the first and second digital output signals shown, respectively, in FIGS. 5f and 5i. For example, it would be convenient to supply the digital signals to a counter means for counting the positive and negative polarity pulses. The counter could then output a display, or record total power consumption. Counter 154 is illustrative of such a display concept. If, in addition, a gate signal is supplied to counter 154, measurements of power in appropriate units, such as kilowatts, could be readily obtained. Separate readings of power flow in each direction could also be obtained.

As previously noted since bistable circuit 52 (FIG. 2) is changeable only at predetermined clock intervals, a slight lag is introduced in the modulated output signal. FIG. 6 shows a novel delta-minus-sigma modulator 30' having digital phase lead circuity to compensate for the phase lag. Like elements in the FIG. 2 and FIG. 6 modulators are designated by like reference numerals. It should be noted that such digital phase lead circuitry has applications other than power metering systems. Moreover, if desired, phase lead can be provided which is more than sufficient to compensate for the phase lag caused by the output bistable 52 of FIG. 2.

The modified modulator 30' of FIG. 6, like the modulator of FIG. 2, includes a bistable circuit 52 controlling a source of feedback current I_F through switches 58 and 60. A summing node 36 receives the input signal I_A1 through input resistor 38.

Instantaneous differences between the feedback and input signals are represented by l_diff and that difference signal is measured by measuring circuit 42. The control signal output from comparator 50 is high when the integrated difference signal is above the threshold of the comparator and is low when the integrated difference signal is below the threshold.

Modulator 30' differs from modulator 30 in FIG. 2 in that it includes a digital shifter between measuring circuit 42 and bistable circuit 52. The digital shifter introduces a time delay in the control signal output from comparator 50. In FIG. 6, the digital shifter is a bistable circuit 59, which receives the control signal output from the comparator at its D input. For the purposes of the example given below, bistable circuit 59 is clocked at the same rate as bistable circuit 52, but one-half clock interval out of phase.

Operation of the modulator shown in FIG. 6 to achieve phase lead in the modulated output signal will be described with reference to FIG. 7. Input signal I to modulator 30' is shown in FIG. 7a. The output, of first clock 56 is shown in FIG. 7b. First clock 56 also supplies the signal to bistable circuit 59 through an inverter 57, and the second clock signal is shown in FIG. 7c. If I_A1 is positive at clock pulse a and the Q output of bistable circuit 52, shown in FIG. 7g, is initially high, I_F will be positive into summing node 36. That will produce a positive l_diff which is supplied to the inverting input of integrating amplifier 46, causing the integrated difference signal at point 47 to initially ramp downward, at 21 of FIG. 7d. Line 22 in FIG. 7d represents the threshold of comparator 50. When the integrated difference signal crosses threshold 22, the control signal shown in FIG. 7e goes from high to low. Assuming bistable circuit 59 clocks on upwardly moving pulses a', b', c', d', e', etc., the output of bistable circuit 59 will go from high to low at clock pulse a'. The output of bistable circuit 59 (Q') is referred to herein as the delayed control signal, which is subsequently supplied to the D input of bistable circuit 52. FIG. 7f shows the delayed control signal and FIG. 7g shows the Q output of bistable circuit 52. When Q' goes from high to low, the Q output of bistable circuit 52 will go from high to low at its next clock pulse b. The change in Q opens switch 60 and closes switch 58, causing I to go negative. The integrated difference signal then ramps upward, crossing comparator threshold 22 and again causing the control signal to go high. At clock pulse d' of the second clock, the Q' output of bistable circuit 59 again goes high. That causes the Q output of first bistable circuit 52 to go high at its subsequent clock pulse e.

The process described above will continue, with the Q output of bistable circuit 52 providing the signals for controlling the feedback loop of the modulator. Assuming the time delay introduced by. the digital shifter represented by bistable circuit 59 is not large enough to create instability in the feedback loop, modulator 30' will produce a modulated signal equivalent, but not identical to that output from modulator 30. By equivalence, what is meant is that the Q output of bistable circuit 52 will be a modulated signal changeable at predetermined first clock intervals in a manner proportional to the signal input to the modulator. The Q' output bistable 59 will lead the Q output of first bistable circuit 52 by an amount dependent on the differences in the clock signals supplied to the two bistable circuits. This lead occurs as a natural consequence of the fact that the Q output of bistable circuit 52 will change only at the next clock pulse following a change in the Q' output of bistable 59. The Q' output thus is a true "leading" signal to the Q output.

The output signal on line 34 will have a phase lead of one-half of a first clock interval, as compared with the Q and Q outputs of bistable circuit 52. Since the clock intervals supplied to both bistable circuit 59 and bistable circuit.52 are the same, the delayed control signal output on lines 34 will be changeable at the same intervals as the Q and Q outputs of bistable circuit 52 and will otherwise resemble any other delta-minus-sigma modulated signal. The clock signal supplied to bistable circuit 59 in effect becomes the determining clock signal governing changes in the output of the modulator. It would be possible to substitute another type of digital shifter, such as a multi-stage shift register, for bistable circuit 59, if the delay introduced is not so long as to destabilize the feedback loop. The digital shifter used might also be clocked at a different rate than the first bistable circuit 52, although that would change the characteristics of the delayed control signal. If, for example, a multi-stage shift register clocked at a high rate were inserted in place of bistable circuit 59, it would delay the control signal by a selected number of short intervals. The output of such a shift register would be a delayed control signal which is changeable at the higher clock rate. A shift register could also be employed, having different stages clocked at different rates. In such a configuration, the longest clock interval used to clock any of the stages would determine the intervals at which the final delayed control signal would be changeable. Any system for delaying the control signal should include at least one bistable circuit clocked at discrete intervals in order that the modulated output of the modulator (the delayed control signal) will be changeable at those discrete intervals.

The phase lead produced in modulator 30' can be selected. Such selection is accomplished by adjusting the clock signals supplied to bistable circuits 52 and 59. Assuming a first clock signal producing pulses at first clock intervals is supplied to bistable circuit 52 and a second clock signal producing pulses at second clock intervals is supplied to the digital shifter (bistable circuit 59), and both first and second clock intervals are equal, the phase offset between the clock signals will determine the amount of lead in the modulator output. In the example discussed with respect to FIG. 7, the second clock was the inverse of the first clock and the total offset was one-half a clock interval. If the clock pulses supplied by the second clock to bistable circuit 59 were three-quarters of a clock interval ahead of the pulses supplied to bistable circuit 52, a phase lead of three-quarters of a clock interval would be produced. It is the amount of delay between a change in the Q' output of bistable circuit 59 and the Q output of bistable 52 which determines the amount of lead time in the signal output on lines 34.

The amount of phase lead that can be achieved by the FIG. 6 modulator is dependent on the degree of delay that can be introduced into the feedback loop of a delta-minus-sigma modulator without causing it to destabilize. It is known, however, that a delay of a fraction of a clock pulse in the manner described in the example above is functional and produces the phase lead in the modulated signal as described.

FIG. 8 shows a metering system according to a further embodiment of the present invention which provides additional output power measurement in either VARS or Q. As described in the background section above, VARS and Q represent power measurements in which a specified phase relationship is introduced between the current and voltage signals. VARS is obtained by multiplying current with a voltage signal which lags by 90 degrees; Q is obtained by multiplying current with a voltage signal which lags by 60 degrees. In the metering system of this embodiment of the present invention, VARS, Q or any other desired phase relationship power value can be readily obtained by delaying the output of modulator 30 by a selected amount. The delay can be conveniently produced using time delay means such as a shift register, in the manner described below.

The Q output of modulator 30 of the Figure 8 embodiment is supplied both to gating means 80 and to a shift register 160. Shift register 160 delays the output of modulator 30 by a selected delay interval. The amount of delay depends on the selected phase relationship power value desired (VARS or Q), and also on the frequency of the AC waveform being measured (50 or 60 Hz). To simplify the circuit, only the Q output of modulator 3-0 is supplied to shift register 160. The time delayed output of the shift register is then supplied to an inverter 161, and both the inverted and non-inverted signals become the time delayed signal on line 162. As used herein, the term "time delayed signal" is used interchangeably with "phase modified signal" and it should be understood that the phase modification introduced is accomplished by means of a time delay introduced in the signal. Further processing of the time delayed modulated signal is exactly the same as for the first modulated signal of the embodiment of FIG. 1. The time delayed modulated signal is supplied to a second gating means 164, which includes a pair of switches 166 and 168 controlled by the time delayed modulated signal. The inverted and non-inverted current analog signal I_A2 is supplied to switches 166 and 168. The phase modified modulated signal alternately closes switches 166 and 168 to multiply the current and voltage signals together and produce a second product signal, at 170. The second product signal is then supplied to the input of a VARS/Q convertor 172, which is exactly like convertor 90 shown in FIG. 3. VARS/Q convertor 172 outputs first and second output signals, depending on the polarity of the power on line 10, in exactly the same manner as convertor 90. The outputs of convertor 172 are first and second output signals changeable between two levels at the convertor clock intervals in a manner proportional to the second product signal and to the selected phase relationship power value (VARS or Q, 50 or 60 Hz) of the power on line 10. Subsequent processing of the first and second output signals from VARS/Q convertor 172 is exactly the same as for the outputs from convertor 90 shown in FIG. 1, including use of counter means suitable for outputting selected power values. A selector (not shown) can be provided for selecting either VARS or Q as the second output of the metering system. The selector will adjust shift register 160 to produce the voltage lag needed to generate the selected phase relationship, and simultaneously select an appropriate display.

The exemplary and novel digital phase selection technique depicted in FIG. 8 is not limited to power metering applications. The technique may be used in any signal multiplication applications where the phase relationship between input signals may be adjusted in order to measure selected phase relationship product values.

FIG. 9 depicts a multiplier similar to the multiplier used in the power metering system of FIG. 8. Like elements are designated by like reference numeral signals. I_A1 and I_A2 are the signals to be multiplied together and are assumed to be periodic waveforms, not necessarily sinusoidal, having a predetermined phase relationship to one another. As with the FIG. 8 power metering system, multiplication is accomplished by the technique known as time-division or markspace multiplication, in which one of the signals I_A2 is modulated and then used to gate or reverse the polarity of the other signal I to obtain a product signal. Signal I_A2 is supplied to a gating means in both inverted and non-inverted forms. A conventional inverter 72 supplies the signal to switch 82. The non-inverted signal is supplied to switch 65. The modulated signal for controlling switches 65 and 66 is supplied to the gating means by way of line 34.

Modulator 30 of FIG. 9 is equivalent in construction and operation to corresponding modulator 30 of FIGS. 1 and 2. In order to achieve a selected phase relationship between signal I_A1 and I_A2 , a digital shifter 160 is used which introduces a selected delay in the output of modulator 30. Digital shifter 160 can take numerous forms, a simple version being illustrated in element 198 of FIG. 11. The operation of a shift register can be illustrated conveniently as a series stages made up of bistable circuits 200 through 204 connected so that the Q output of one bistable circuit is supplied to the D input of the adjacent bistable circuit. A clock signal supplied to each of the bistable circuits via line 196 causes each stage to be clocked simultaneously. A digital pulse on line 53 into shift register 198, either going from low to high or from high to low, will be delayed one input clock interval by each bistable circuit it passes through. For example, if the signal on line 53 goes from low to high, the Q output of bistable circuit 200 will go from low to high at the next clock pulse. Because of inherent switching delays, when the Q output of bistable circuit 200 goes from low to high and that signal is supplied to the D input of bistable circuit 201, its Q output must wait for the succeeding clock pulse to go high. In this manner, digital signals can conveniently be delayed by any desired number of discreet intervals simply by providing enough delaying stages in the shift register. Customarily, shift registers are provided with a plurality of output lines 206 at which the signal can be extracted. The location of the pin determines the overall delay introduced, as a function of the clock frequency.

The digital time delay means 160 of the multiplier system shown in FIG. 9 is assumed to be a conventional shift register such as shift register 198 of FIG. 11. The multiplier system calls for the introduction of a selected time adjustment in one of the signals to be multiplied using a digital shifter to introduce a delay which is a selected number of discrete intervals.

Shift register 198 is a suitable digital shifter for producing such. a delay. Referring now to FIG. 10, it will be assumed that signals I_A1 and I_A2 are to be multiplied together and that a 90 degree phase lag will be introduced into signal I_A2. FIG. 10a shows an exemplary first input signal I_A1 (V_L) and FIG. 10g shows an exemplary second input signal I_A2 to be multiplied together. FIG. 10b shows the clock signal provided by clock 56 and FIG. 10c shows the output signal of the integrator 42 which results from input signal I_A1 . FIG. 10d shows the resultant output of comparator 50. The output of modulator 30 is shown in FIG. 10e, and is carried on line 53 of FIGS. 9 and 11. The clock signal from modulator clock 56 is supplied to shift register 198 via line 196. In the example given, the clock intervals, shown in FIG. 10b, are twenty-four times the frequency of signal I_A2. A 90 degree phase lag will therefor require a delay of six clock intervals. Assuming pin 206' of shift register 198 to be the sixth pin, signal I_A2 , modulated and delayed by 90 degrees, will thus have been delayed by a total of six clock intervals output from clock 56. The pin 206' output of shift register 198 is illustrated in FIG. 10f. The delayed modulated signal shown in FIG. 10f is an exact reproduction of the modulated Q output of modulator 30, shown in FIG. 10e, moved to the right six clock intervals.

Signal multiplication is accomplished by supplying the delayed modulated signal shown in FIG. 10f to the signal gating means, via line 34. Line 34 includes both inverted and non-inverted versions of the delayed modulated signal by supplying the signal to a conventional digital inverter 161. Signal I_A1 is that shown in FIG. 10g both in inverted and non-inverted forms. Multiplication is carried out by means of switches 82 and 86, which are opened and closed alternately from one another, switching point 88 of FIG. 9 between the non-inverted and inverted versions of signal I_A1. The resultant signal is shown in FIG. 10h. The signal in FIG. 10h can then be passed through a suitable low pass filter 90 to produce an averaged or D.C. value, as shown with line 132 of FIG. 10h. Line 132 represents a product signal proportional to the product value of I_A1 and I_A2 with a phase lag of 90 degrees introduced in I_A2. If, for ex-ample, signal I_A1 was proportional to current carried on a power line and signal I_A2 was proportional to line voltage, the product signal represented by line 132 of FIG. 10h would be proportional to VARS.

A particular advantage of using a delta-minus- sigma modulator such as modulator 30 in conjunction with the subject multiplier is that the modulated signal is changeable only at predetermined clock intervals. Digital time delay techniques necessarily divide an incoming signal into discrete units or intervals. The length or duration of those intervals is a matter of design choice. Digital-type signals carry information at pulse edges, when the signal goes from low to high or high to low. A shift register made up of a series of bistable circuits will "look" for such pulse edges each time it is clocked. The higher the clock frequency, the more frequently is the incoming signal sampled for a pulse edge. Since the delay introduced in a signal at each stage of a shift register depends on the clock frequency, shift registers clocked at a high frequency require more stages to produce a given delay than shift registers clocked at a low frequency. Of course, clocking a shift register at a low frequency means that the incoming signal is sampled less often for pulse edges, and this can be a disadvantage if the location of the pulse edges is not known, as is the case with conventional pulse width modulated signals. Modulator 30 outputs a signal having pulse edges which occur only at predetermined clock intervals. By synchronizing the clock signals supplied to the modulator and to shift register 198, the shift register will "look" for pulse edges only at the times required. This means that fewer shift register stages are needed to introduce a given delay in a modulated signal than would be the case if the location of the pulse edges were not precisely known. In fact, in the example given above, the shift register can be clocked at the same rate as modulator 30, with no loss of information whatsoever. It is therefore possible to use an economical shift register, possessing relatively few stages, to produce a given delay in a delta-minus-sigma modulated signal, which when a far larger shift register would be needed to produce a comparable delay in a signal having pulse edges at random locations. Even if a relatively high frequency shift register was employed to delay a substantially lower frequency randomly modulated signal, some loss of information would occur whenever a pulse edge was not precisely synchronized with the shift register clock. No such loss of information occurs in the embodiment of the present invention described above since the modulator and shift register are synchronized with one another and pulse edges are therefore not displaced.

The clock intervals by which the shift register is clocked need not be exactly the same as the first clock intervals of the modulator 30. It is, however, preferable that the shift register clock be synchronized with the modulator clock. To avoid loss of information, the shift register clock should operate at a frequency no lower than that of the modulator, but may operate at higher rates to achieve virtually any desired time delay. A convenient way of increasing the frequency of the shift register clock while maintaining synchronization with the first clock intervals of the modulator is to use a frequency divider for the modulator clock. While in the example described above, the desired time delay in the modulated signal corresponded with an integer number of first clock intervals, that may not always be the case. In order to achieve additional flexibility in the. selection of a time delay it may be desirable to include either a second shift register or additional stages within a single shift register which are clocked at a higher frequency and which therefore introduce incremental delays in the modulated signal. The shift register states within element 212 of FIG. 11 illustrates a technique for providing further selectivity in the digital time adjustment of the present invention. In this example, the delayed signal output from any selected stage of shift register 198 is supplied to a second group of shift register stages shown in FIG. 11 as a second shift register 212. A plurality of bistable circuits 216 make up shift register 212. The delayed signal from shift register 198 is supplied to the input 214 of shift register 102. A clock signal, via line 208 preferably.having a higher frequency than first clock 56, is supplied to the bistable circuits which form shift register 212. The higher clock frequency can conveniently be provided by means of an oscillator 220 operating at a higher frequency than first clock 56. Through use of a suitable frequency divider 210, clock signals of different frequencies can be supplied to the various shift register stages, as well as to modulator 30, if desired.

As used herein, the term first clock intervals generally refer to the clock signals output from first clock 56 and second clock intervals will be those output from second clock 220. In addition, the shift register stages illustrated in Figure 11 can be thought of either as a first shift register 198 and a second shift register 212, or a single shift register having a plurality of stages which are clocked at various selected frequencies. Either through use of separate oscillators or a single oscillator with a frequency divider, the provision of different clock signals increases the flexibility of the digital shifting techniques used in the present invention. Delaying a signal with a shift register having a number of stages all clocked at the same rate allows a signal to be delayed by any number of discrete intervals, up to the maximum number of stages in the shift register. By providing additional stages clocked by a different clock signal, additional selected delay intervals can be provided. A signal can be passed through a first shift register and delayed a certain number of first intervals, and then passed through a second set of shift register stages and delayed an additional number of second intervals. Thus, a delay of virtually any desired whole and fractional increments of the first intervals can be provided. Similar flexibility in signal delays by digital means can be achieved by using a second clock which operates at the same frequency as the first clock, but is offset in time by a selected amount. For example, if a signal is passed through a first shift register clocked at first intervals and then supplied to an additional stage clocked with the inverse of the first interval clock signal, an additional delay of one-half of a first clock interval will be introduced. Depending on the offset between the clock signals supplied to the first and second group of shift register states, almost any amount of delay can be introduced.

An example of the operation of the modulator and digital time delay means of FIGS. 9 and 11 is given in FIG. 12. Assuming a first clock signal supplied by clock 56 to be that shown in FIG. 12b and a second clock signal supplied by second clock 220 to be that shown in FIG. 10a, a modulated signal input to the shift register will be delayed in the manner described below. In this example, second clock 220 is exactly twice the frequency of first clock 56. If, for example, a delay in the modulated signal of two-and-a- half first clock intervals is desired, the shift register will be configured so that otuput pin 206'' is connected to the second shift register input 214. In that way, a modulated signal input via line 53 will pass through two first shift register stages 200 and 201 and into the first stage of second shift register 212, after which the signal is output at pin 218. The signal will be delayed two full first clock intervals and an additional second clock interval by such a system. Assuming a modulated signal as appears in FIG. 12c is input to the configuration described above, the output at pin 218 will be the signal shown in FIG. 12d. The delayed modulated signal shown in FIG. 12d is exactly the same as the modulated signal shown in FIG. 12c, delayed by two-and-a-half first clock intervals.

The digital shifting technique of the subject multiplier has the advantage inherent in digital electronics of being relatively drift-free and error- free. Furthermore, the time adjustment is made in a manner independent of the signal being adjusted. In other words, it is not dependent on the frequency of the signal being adjusted in time. The system shown in FIG. 9 allows for phase adjustment in the multiplication of two analog signals without the use of R.C. networks and their associated signal perturbations. If delta-minus-sigma modulation is employed in the multiplication, the size of the shift registers employed need not be prohibitively large, while yielding a high level of accuracy. In order to achieve high accuracy from the subject power metering system of the present invention over a wide dynamic range, it is important that offset errors be eliminated from the active circuit elements. Offset errors of sufficient magnitude to adversely affect measurement accuracy are commonly found in low cost operational amplifiers. The term voltage offset is generally defined as the voltage difference between a pair of inputs to an active circuit element, such as an operational amplifier, when the output is zero. It is a mismatch between the amplifier inputs, and the metering system of the present invention incorporates offset compensation means which correct for such mismatch. FIG. 13 illustrates a novel offset compensation system, as applied to a single amplifier. The basic theory of the offset compensation system involves use of a capacitor or other storage element which is connected to one input of the amplifier and then charged to a compensating voltage. It will be understood that other equivalent systems for storing and supplying a voltage to an amplifier input could be used in place of a capacitor. Operational amplifiers often have more than two inputs, and sometimes include one or more inputs specifically designed for offset compensation purposes. The present invention will work equally well to offset compensate amplifiers having additional inputs. Whichever input is designated to receive a compensating voltage to correct for voltage offset will be the input to which the capacitor is connected. The system further includes means for charging the capacitor to an offsetting voltage which substantially cancels out the effect of the voltage offset another amplifier input. For simplicity, only amplifier 70 (FIG. 1) is shown in FIG. 13, although the offset compensation means of the present invention can sequentially correct a plurality of amplifiers, as set forth below.

The amplifier offset compensation means as applied to amplifier 70 includes an offset storage element, such as capacitor C₁, connected to a first selected input 181 of the amplifier. A nulling circuit 182, connected through switches to both the offset storage element and the second selected input 183 of amplifier 70, is also provided. Nulling circuit 182 includes a charging amplifier 184 connected to the second input of amplifier 70, through a switch A1. The nulling circuit also includes a temporary storage element, capacitor 186, and a series of switches, B, D and E, which connect capacitor 186 in to charging amplifier 184 as described below. Additional switches G₁ and H₁ connect charging amplifier 184 in a charging circuit, which adjusts the voltage stored on capacitor C₁.

The line current signal I_A2 is supplied to the inverting input 183 of amplifier 70, which is ideally a virtual earth. Any voltage offset in amplifier 70 will appear initially as a voltage at inverting input 183. As capacitor C₁ becomes charged, the voltage at inverting input 183 will decrease until a virtual earth condition is reached. The difference between the compensating voltage V_comp on C₁ and the actual voltage offset of amplifier 70 is termed an error voltage

V_error. It is V_error which appears at input 183. It is the purpose of the offset compensation means of the present invention to reduce V_error to a minimum. The offset compensation means includes control means for accomplishing the functions set forth in box 190. Essentially, the control means operates switches A1, B, D, E, G1, and H1 to produce a series of transfer and charging periods, sequentially. During an initial transfer period, switches A1, B and D are closed and switches E, G1 and H1 are open. With switch A1 closed. V_error is supplied to the non-inverting input of charging amplifier 184, which is configured as a unity-gain amplifier. Switch B, which is closed during the transfer periods, makes a feedback connection between the Output 192 of charging amplifier 184 and the non-inverting input 226. A first terminal 228 of temporary storage capacitor 186 is also connected to inverting input 226. Switch D, when closed, connects a second terminal 230 of capacitor 186 to ground. Thus, during the transfer pJ.eriod, Verror appears at amplifier output 192 and is stored on temporary storage capacitor 186, together with the voltage offset of charging amplifier 184 (V_{offset-Amp 184} ).

During a subsequent charging period, control means 190 opens switches A1, B and D and closes switches E, G1 and H1. That serves to disconnect the second terminal 230 of capacitor 186 from ground and connects it to amplifier output 192, in a second feedback loop. The result is that a voltage -V_error appears at amplifier output 192. The internal offset of charging amplifier

184 (V_{offset-Amp 184}) is cancelled by the equal and opposite value of the component -V_{offset-Amp 184} which is supplied to output 192 from capacitor 186. The closure of switch G1 and the opening of switch A1 during the charging period also supplies the voltage V_comp on offset storage capacitor C1 to the non-inverting input of charging amplifier 184. With - V_error at charging amplifier output 192 and V_comp at its input (during the charging period), a current - I_error is set up through impedance 224 and switch H1 which adjusts V_comp in the direction necessary to reduce V_error during the next transfer period.

FIG. 14 illustrates the operation of the offset compensation means during startup conditions. Assuming the voltage V_{offset-Amp 70} represents the voltage offset between the inputs of amplifier 70, and the charge on capacitor C₁ (V_comp) is initially zero, then

V_error, during the initial transfer period will equalV_{offset-Amp 70}. During the subsequent charging period a voltage - V_error will appear at amplifier output 192. A current -I_error will then be supplied to capacitor

186, increasing the value of V_comp. The voltage V_comp on capacitor C₁ will serve to substantially reduce the offset error of amplifier 70 until the next transfer period. The values of resistor 224 and capacitor C1 are chosen to produce a current -I_error which will not excessively change the voltage on capacitor C₁ during any single charging period. Capacitor C₁ will therefor not become charged to the full offsetting voltage during the first few transfer and charging cycles. As V_comp approaches (V_{offset-Amp 70}) V_error will become progressively smaller. Eventually, V_error will approach a stable minimum value sufficient to correct for leakage currents and other transient signals present in the circuitry. At that point the offset errors will be virtually eliminated.

Subsequent transfer and charging periods can either follow immediately after previous transfer and charging periods, or be separated by a time delay. In the preferred embodiment, where additional amplifiers are being offset compensated using the same nulling circuit 182, the transfer and charging periods associated with any one amplifier are separated by predetermined time intervals. Referring to FIG. 14, the next transfer period shows a Verror which is smaller, as shown at 222. As before, V_error is first stored on capacitor 186 and then, during the following charging period, appears at charging amplifier output 192 an - V_error. During this charging period the current - V_error is added to the charge on capacitor C₁, further reducing the magnitude of V_error during the following transfer period. During subsequent cycles. Vcomp on capacitor C1, will approach the actual voltage offset of amplifier 70, reducing V_error to approximately zero.

The offset compensation system described above with respect to amplifier 70 can similarly offset compensate a plurality of amplifier elements. FIG. 15 shows the preferred embodiment of the offset compensation system used to provide offset compensation for five different amplifiers. The five amplifiers to be offset compensated by the compensating means of the metering system are as follows: current signal gain amplifier 70, current signal inverting amplifier 74, first, modulator integrating amplifier 46, Watts output convertor integrating amplifier 108 and VARS/Q output convertor integrating amplifier 180. Each of the amplifiers is similar to gain amplifier 70 discussed with respect to FIG. 13 in that all have virtual earth inverting inputs to which a signal is supplied. Each of these amplifiers is provided with respective offset storage elements, capacitors C₁ through C₅. The non- inverting inputs of the amplifiers are connected to the charging amplifier 184 of nulling circuit 182 through respective switches A1 through A5, as shown in FIG. 15. Pairs of switches equivalent to G1 and H1 of FIG. 13, namely G1 through G5 and H1 through H5, connect charging amplifier 184 to the respective offset storage capacitor of each amplifier.

A single nulling circuit 182 will store the error voltage and charge the offset storage capacitor of each amplifier, by means of the sequence described below. For clarity, the control circuitry for operating the various switches shown in FIG. 15 is omitted. A conventional controller of any suitable type can be used to control the switches in accordance with the timing diagram illustrated in FIG. 16. The controller first closes switches A1 , B and D during an initial transfer period for amp 70, then open switches A1, D and B and closes switches E, G1 and H1 during a charging period. The controller then provides additional successive transfer and charging period for each of the other amplifiers being offset compensated. After the charging period of amplifier 70 the transfer period of amplifier 74 begins, with the controller closing switches A2, D and B and then opening those switches and closing switches E, G2 and H2 during the subsequent charging period. For amplifier 46, switches A3, B and D are closed during the transfer period and switches E, G3 and H3 are closed during the charging period. For amplifier 108, switches A4, B and D are closed during the transfer period and switches E, G4 and H4 are closed during the charging period. Finally, for amplifier 180 switches A5, B and D are closed during the transfer period and switches E, G5 and H5 are closed during the charging period.

After a transfer and charging period has been completed for an amplifier, all the switches associated with the amplifier, namely switches A, G and H, are left open. The charge stored on the respective offset storage capacitors will remain until the controller sequence produces a new charging period associated with that capacitor. Although some charge decay will occur, errors due to voltage offset are substantially reduced for each of the amplifiers. The frequency of operation of the controller for opening and closing the switches associated with the offset compensation means is a matter of design choice, but can be substantially slower than the clocks associated with the metering system.

The disclosed offset compensation system can be used to correct for offset errors in any number of amplifier elements associated with a metering system. A single nulling circuit like circuit 182 can be sequentially connected to up to N amplifier elements and to their associated storage elements during a sequence of transfer and charging periods. Such an offset compensation system is economical, and is ideally suited to the use of CMOS integrated circuitry where offset errors can present problems. Although described with respect to the metering system of the present invention, the offset compensation system can be applied equally well to other types of power metering circuits employing operational amplifiers.

Such a metering circuit might include, for example, any suitable means for multiplying the analog signals representing current and voltage, as well as any suitable converter or filter circuit for producing an output signal from the product signal. Assuming that the metering system employs up to N amplifier elements in its various components, the offset compensation system of the present invention can substantially eliminate offset errors in the manner described below. The N amplifier elements, each will include plurality of inputs. A first selected input in any such amplifier is the input for receiving a compensating voltage to correct for voltage offset. N offset storage elements, such as capacitors, are also provided. One of the N offset storage elements is connected to the first selected input of each of the N amplifier elements. The offset storage elements receive compensating voltages which substantially reduce the offset error at another input of the amplifier element to which it is connected, the other input being designated the second selected input. Any difference between the compensating voltage on the offset storage element and the voltage offset of the amplifier element is an error voltage which appears at the second selected input of the amplifier element. A nulling circuit such as circuit 182 is also provided for the power metering system. The nulling circuit can be connected sequentially to each of the N amplifier elements and to the offset storage element associated therewith. In the description below, the amplifier element to which the nulling circuit is connected, including its associated storage element, is termed the selected amplifier element. In the same manner as the system described above, the nulling circuit is first connected to the second input of the selected amplifier element, during an intermittent transfer period. The nulling circuit is then connected to the offset storage element associated with the selected amplifier element during the intermittent charging period following the transfer period. A control system then connects the nulling circuit sequentially to the remaining of the N amplifier elements to provide transfer and charging periods for each of the amplifier elements. The sequence is continuously repeated, whereby all of the amplifier elements are offset compensated and the offset errors in the metering system are substantially eliminated.

Through incorporation of the offset compensation means described above, the metering system of the present invention meters power to a high degree of accuracy over a wide dynamic range. The need for relatively high cost calibrated or error-free amplifiers is eliminated, which makes the metering system relatively inexpensive. The system provides continuous parallel readings of power in both Watts and in VARS or Q. Because the modulator output from modulator 30 is clocked precisely at the first clock intervals, it is possible to manipulate the signal with digital logic. A shift register can be conveniently employed to introduce the time delay necessary to provide an appropriate phase shift for the VARS and Q measurement. By simply selecting the appropriate stage in the shift register, the delay in the modulated signal can be adjusted to produce the desired output

(VARS or Q, 50 or 60 Hz). The invention thus eliminates the need for tuned analog phase shifters to produce the desired voltage lag. Because the output of the modulator can be supplied both to a power and a

VARS/Q converter, simultaneous readings can be produced with only a single modulator. The system further provides digital outputs for each polarity of power flow on the line. Maximum information is therefore provided to a high degree of accuracy in an efficient and economical manner.

FIG. 17 shows a portion of an alternative embodiment modulator which is somewhat simpler in construction than modulator 30 shown in FIG. 2. In this emobdiment, a capacitor 44 is connected between the summing node 36 and ground. Capacitor 44 serves as the modulator integrator. The inverting input of a comparator 50 is also connected to node 36 with the non-inverting input being connected to ground.

Comparator 50 develops a control signal in response to voltage changes on node 36 which is coupled to a bistable circuit 52. Circuit 52 is used to control a pair of switches which supply a feedback signal to node 36, as will be subsequently described.

FIG. 18 illustrates several of the signals produced by the FIG. 17 modulator. Input signal V_L is represented in FIG. 18a. Of course, in A.C. power metering applications, V_L will be sinusoidal. Initially, switch 58 is assumed to be closed, and a negative reference current is applied to summing node

36 through resistor 40. The values of V1- and resistor

40 are chosen to produce a current I_F which is large relative to input signal I_A1 . l_diff will therefore have a net negative value, with current being drawn from capacitor 44. Consequently, the integrated difference voltage signal initially decreases, as shown in FIG. 18c.

Clock 56 outputs signal shown in FIG. 18b. Bistable circuit 52 clocks on the leading edge of each upwardly-moving pulse. At clock pulse a, the integrated difference signal of FIG. 18c has not yet crossed the threshold of comparator 50, so Q remains low and Q high and the difference signal continues to integrate downward. Since the difference signal is supplied to the inverting input of comparator 50, when the signal crosses the threshold, the comparator output switches from low to high. The control signal shown in FIG. 18d represents the output of comparator 50. Consequently, at clock pulse b, bistable circuit 52 will change states and Q will go from low to high.

When Q goes high Q goes low and switch 60 is closed and switch 58 is open. A positive reference signal is then supplied to summing node 36, causing integrated l_diff to increase until the next clock pulse at c. Between clock pulses b and c, the integrated difference signal again crosses the threshold level of comparator 50, causing the first control signal to go low. Q then goes low at the next clock pulse, causing the reference signal supplied to summing node 36 to again go negative. As V_L increases, the slope of the difference signal changes and its value decreases until again crossing the threshold level. Q remains low until detecting a change in the first control signal at clock pulse f. Q then goes high, again switching the reference signal from negative to positive.

The above-described circuit and method operates as a delta-minus-sigma convertor in which only the difference between the input and reference signals is integrated and measured. The circuit always maintains the integrated difference signal around the threshold level of comparator 50. The Q output of bistable circuit 52 is chosen as the first output signal, having an average level or amplitude over time which is proportional to the magnitude of V_L.

FIG. 19 shows a modulator circuit as in FIG. 17 which incorporates an alternative offset compensation system. In this embodiment, comparator 50, which is an operational amplifier element, is provided with compensating means for substantially eliminating any offset error resulting from a voltage offset existing between fehe amplifier inputs 306 and 308. As described above, a voltage offset is generally defined as the voltage required between inputs of an amplifier to produce a zero output. Ideally, voltage offset is zero, but in most real-world operational amplifiers an offset of unknown value is usually present. With the present invention, a first storage element, such as capacitor 302 is connected to one of the amplifier inputs, and an offsetting voltage substantially equal to the voltage offset of the amplifier is stored on the storage element to compensate for the voltage offset. In the example shown in FIG. 19, capacitor 302 is located in the electrical path between summing node 36 and inverting amplifier input 306. It should be understood that capacitor 302, like capacitor 44 and the other storage elements used in the embodiments described below, represent one type of storage element which can be used, and that other types of circuit elements, such as registers with D to A convertors and the like, could be used for the various storage elements of the present invention.

The offset compensation system also includes a feedback loop 300, which is intermittently connected around amplifier 50, between inverting input 306 and the amplifier output through a switch, C. When Switch C is closed, the voltage offset appears at a low impedance at input 306. In order to store the voltage produced by the feedback loop on capacitor 302, switches A and B are provided to disconnect one end of the capacitor from summing node 36 and connect it to common ground 305. The means for controlling the offset compensation system shown in FIG. 19 is clock 56, and FIG. 20 illustrates the control function. Bistable circuit 52 clocks at the leading edge of each clock cycle, as indicated by arrows 312. Each upward moving pulse represents one clock pulse. Just as the clock signal begins to go from low to high, switches B and C are off and switch A is on, meaning that the feedback loop around amplifier 50 is disconnected and capacitor 302 is connected to summing node 36. As soon as the clock pulse begins, switches B and C turn on and switch A turns off, connecting the feedback loop around amplifier and connecting one terminal of capacitor 302 to ground. During this period, called the nulling period, the voltage offset +V_offset ^of amplifier 50 appears at input 306. Since capacitor 302 is connected between input 306 and ground, the voltage +V _offset is stored on the capacitor. During the last half of each clock cycle, called the measuring period, switches B and C again turn off and switch A turns on. With non- inverting input 308 tied to ground, the error at inverting input 306 is the negative value of the voltage offset -V_offset Consequently, the signal being compared to the threshold level by comparator 50, when A is closed and B and C are open, is the voltage at summing node 36, the integrated difference signal, plus +V_offsetplus -V_offaet . The voltage offset of comparator 50 is therefore cancelled, and the error it would otherwise produce in the threshold measurement is essentially eliminated. Another embodiment of a modulator utilizing an offset compensation system is shown in FIG. 21. In this embodiment, measuring means 298 has first and second amplifier elements 328 and 336, respectively, which serve as comparators and are alternately connected between summing node 36 and bistable circuit 52. First amp 328 is provided with a switchable feedback loop 324 connecting output 330 with inverting input 326 through switch D. A first storage element in the form of capacitor 316 is connected in the electrical path between summing node 36 and inverting input 320 through switch E. A path is provided between one terminal 318 of capacitor 316 and ground, through switch F. Second amplifier element 336 also includes a switchable feedback loop 332 connected between output 338 and inverting input 334 through switch G, and a storage element such as capacitor 320 is in the electrical path between inverting input 334 and summing node 36, through switch H. A path between one terminal 322 of capacitor 320 and ground is provided, through switch J. The embodiment of FIG. 21 is designed to provide two parallel offset compensated comparator circuits for measuring the integrated difference signal at summing node 36. When switches E and K are closed, first amplifier element 328 supplies the first control signal to bistable circuit 52 and when switches H and L are closed, second amplifier element 336 supplies the first control signal to bistable circuit 52. By closing switches E, G, J and K and opening switches D, F, H and L, first amplifier element 328 is in a measuring mode supplying the control signal to bistable circuit 52, and second amplifier element 336 is in a nulling mode in which the voltage offset of amplifier element 336 is stored on capacitor 320. Storage of V_offset on capacitors 316 and 320 is accomplished in exactly the same manner as with amplifier element 50 and capacitor 302 in the embodiment of FIG. 19. By reversing all the switches, i.e., closing switches D, F, H and L and opening switches E, G, J and K, amplifier 328 is in the nulling mode and amplifier 336 is in the measuring mode in which the integrated difference signal at summing node 36 is supplied to inverting input 334 through capacitor 320, compensating for the voltage offset of amplifier 336 and providing an error-free first control signal to the D input of bistable circuit 52.

One advantage of the embodiment shown in FIG. 21 over that shown in FIG. 19 is that one offset compensated amplifier is available at all times in its measuring mode. Furthermore, switching between measuring and nulling modes in the embodiment of FIG. 19 occurred at the clock frequency of clock 56. If the sampling frequency, as determined by the frequency of clock 56, is sufficiently high, the amplifier elements which serve as comparators will be unable to stabilize after each nulling period, and errors will be introduced. The embodiment of FIG. 21, which uses conventional control logic for operating switches D, E, F, G, H, J and L, represented by element 340, can be operated at a frequency different from clock 56. A conventional frequency divider can be used to reduce the frequency of the control operations, for example. In order to insure that adequate time is provided for the amplifiers in the embodiment of FIG. 21 to stabilize after each nulling period, control logic 340, which serves as control means for operating switches D, E, F, G, H, J, K and L, extends the measuring period for each amplifier element to allow time for stabilization. FIG. 22 shows the timing diagram for the operation of switches D, E, F, G, H, J, K and L by control logic 340. Switches K and L, which connect the outputs of the first and second amplifier elements, respectively, to bistable circuit 52, are operated out of phase with one another. Switch K is on half the time, and off half the time and switch L being off when K is on, and vice versa. In addition to controlling the switches which connect the amplifiers to bistable circuit 52, control logic 340 also controls the switches which determine the nulling and measuring periods of amplifiers 328 and 336. Switches D, E and F serve to connect a feedback loop around amplifier 328 and connect the one terminal 318 of capacitor 316 to ground, in exactly the same manner as the embodiment of FIG. 19. Switches G, H and J perform the same function for amplifier 336. As can be seen from FIG. 22, the amplifier nulling and measuring periods of each amplifier element are not of the same duration. The nulling period for first amplifier 328, for example, begins when switch K turns off and ends before switch K again is turned on. Similarly, the nulling period of second amp 336 begins when switch L turns off and ends before switch L turns on again. Consequently, the nulling period of each amplifier is shorter than the measuring period by a predetermined interval. This is done to allow time for the amplifiers to stabilize before being connected to bistable circuit 52.

It should be noted that, in addition to allowing extra time for amplifier stabilization before connecting either the first or second amp to the bistable circuit, control logic 340 operates inherently slower than clock 56. As can be seen from FIG. 22, the clock signal, which is not drawn to scale, operates at a substantially higher frequency than any of the switches in FIG. 21. Control logic 340 preferably includes a frequency divider for this purpose. The embodiment shown in FIG. 21 can thus employ a relatively high frequency clock, for example 10 KHz, to provide frequent sampling and relatively high resolution, while nulling and offset compensating the amplifier elements at a low enough frequency to minimize errors due to slow amplifier response. The method of the present invention, performed by the embodiment of FIG. 21 includes an additional step in the measuring step, for switching between the first and second amplifier elements, 328 and 336, respectively. The compensating step includes measuring with the first amplifier element and nulling the second amplifier element and then measuring with the second amplifier element and nulling the first amplifier element, in a continuous cycle, such that at least one of the offset compensated amplifier elements is connected to the summing node at all times. In the preferred embodiment of the method, the nulling periods and measuring periods are different, and preferably slower than the clock intervals. Further, the nulling periods are shorter than the measuring periods for each amplifier element, in accordance with the timing diagram of FIG. 22. The measuring period of one amplifier element is begun prior to ending the measuring period of the other amplifier element such that any errors due to slow comparator response of the first of the amplifier elements as it is initially switched from nulling to measuring is eliminated.

Operation of the embodiment of FIG. 21 will produce the results illustrated in FIG. 18. Assuming V_L is as shown in FIG. 18a, the integrated difference signal appearing at summing node 36 will be that shown in FIG. 18c. Both the first control signal of FIG. 18d and Q output of FIG. 18e will be unaffected by the intermittent operation and cyclical nulling and measuring periods of amplifiers 328 and 336. The embodiment of FIG. 21 provides greater accuracy at higher clock frequencies, but is otherwise functionally identical to the embodiment of FIG. 19.

Modulator 30 used in the Figure 1 metering system can be used in other applications where it is necessary to provide modulated output signals which are indicative of the polarity of the input signal. Referring now to Figure 23, an alternative embodiment modulator which provides such output signals may be seen. Input signal I_A1 is supplied to summing node 36 through resistor 38. One of the two reference signals, which are preferably of equal magnitude and opposite polarity, are also supplied to the summing node through resistor 40. The reference voltages VI- and V1+ are connected to the summing node through a pair of switches 58 and 60, respectively, which are controlled by the modulator output. Instantaneous differences between input current I_A1 and feedback current I_F at node 36 are supplied to an integrator, which produces an ascending or descending ramp voltage. The integrated signal is then compared against a threshold level by a comparator 50, which outputs a control signal indicating whether the output of the integrator is above or below the threshold level. The output of comparator 50 is supplied to a bistable circuit, such as flip-flop 52.

The bistable circuit changes states only at predetermined clock intervals, as determined by clock 56. When the integrated signal crosses the threshold level of comparator 50, the outputs of bistable circuit 52 reverse states at the next clock pulse. The Q output of bistable circuit 52, which is the first modulated signal of the present invention, controls switch 60, which connects the positive reference voltage V1+ to summing node 36. The Q output, which is always the inverse of the Q output, operates switch 58, connecting the negative reference voltage V1- to summing node 36. Switches 58 and 60 are always operated alternately, meaning that one or the other of the reference signals is always supplied to summing node 36. The Q output of bistable circuit 52 is connected to the D input of a second bistable circuit 53 and both receive clock signals from the same clock 56. Because of gating delays, changes in the Q output of bistable circuit 53 will always follow changes in the Q output of bistable circuit 52 delayed by one clock pulse. An AND gate 350 is also provided to receive the Q outputs from both bistable circuits 52 and 53, as well as a clock signal from clock 56. The AND gate serves as means for outputing a first digital signal which is proportional to the magnitude of one polarity of the input signal.

FIG. 24 illustrates the operation of the abovedescribed circuit elements. Assuming, for illustrative purposes that the voltage waveform at node 32 supplied to the alternative embodiment modulator is as depicted in FIG. 24a, the signal is converted to a first modulated signal at the Q output of bistable circuit 52 in the manner described above. The Q output of bistable circuit 52 is assumed to be that shown in the waveform of FIG. 24d. The output of clock 56 is represented by the waveform of FIG. 24b. The output of second bistable circuit 53 is termed "delayed Q" and is depicted by the waveform of FIG. 24e. Delayed Q is substantially equal to Q, but delayed in time by one clock interval. The present invention calls for combining Q, Delayed Q and a clock signal at an AND gate 350 (see FIG. 23).

Although not necessary in idealized circuits in which component delays are nonexistent, for real-world components it is preferable to include an inverter 57 between clock 56 and AND gate 350. Inverter 57 inverts the clock signal to yield an inverted clock signal shown in FIG. 24c. The reason for supplying an inverted clock signal to the AND gate is because propagation delays in bistable circuits 52 and 53 will tend to cause their outputs to lag slightly behind the output of clock 56, and will produce short simultaneous "high" conditions in all three signals at the wrong time. The result of not inverting the clock is an extraneous spike output from AND gate 350, which would represent an error pulse. For this reason, inverter 57 is included in FIG. 23. The resultant waveform output by AND gate 350 is shown in FIG. 24f.

The FIG. 24f waveform is essentially a digital representation of the amount by which the time Q is high exceeds the time Q is low. In the example of FIG. 24, waveform 24f contains only two pulses, generated successively, and appearing at the right side of the illustration. Those two pulses roughly coincide with the region where the FIG. 24a input is most negative. Preferably, the frequency of the clock will greatly exceed the variations of the analog input signal, to produce higher resolutions than that shown in FIG. 24. The principle of operation is exactly the same, however. In essence, combining a delayed modulated signal with the original modulated signal at an AND gate produces an output which will go high only when Q remains high for at least two successive clock pulses. The clock signal causes the AND gate output to be a pulse train, having pulses at intervals of not less than the clock intervals of the clock signal. In the example just described, the AND gate outputs pulses only when all signals supplied to it are high. If Q is low for two or more successive clock pulses, it will have no effect on the output of AND gate 350 since only high inputs are measured. Thus, the output of the AND gate is a representation of the magnitude of only one polarity of the input signal. The output is, in effect, a half wave rectified signal, represented digitally. In order to produce a digital output proportional to the other polarity of the input waveform, the alternative embodiment modulator utilizes the Q outputs of bistable circuits 52 and 53 as first and second inverse modulated signals, respectively. Assuming the same input signal and clocks as shown in FIG. 24, Q will be as shown in the waveform of FIG. 24g. Bistable circuit 53 provides a delayed Q signal as shown in FIG. 24h. Both signals are supplied to a second AND gate 352 (FIG. 23), together with the inverted clock signal shown in FIG. 24c. The output of second AND gate 352 is shown in the waveform of FIG. 24i and is termed a second digital signal. The second AND gate serves as means for outputting a second digital signal which contains pulses in proportion to the amount of time by which one level of said first inverse modulated signal exceeds the other level. When all three inputs to the AND gate are high, pulses are produced at intervals of not less than the clock intervals of clock 120. In the present example, the waveform 24i represents the positive polarity component of the input signal. As can be seen, the location of the pulses roughly corresponds with the regions where the FIG. 24a input signal is high. The FIG. 24i waveform provides a digital representation of the magnitude of the positive half wave components of input signal.

Referring back to FIG. 23, the present invention can be further employed to produce a digital signal proportional to the magnitude of the full waveform of input signal. This is accomplished by supplying the first digital signal output of AND gate 350 and second digital signal output of AND gate 352 to an OR gate 351, which serves as gate means for combining the digital signals and for outputting a summation digital signal shown in FIG. 24j. The FIG. 24j waveform is proportional to the magnitude of the full input signal. including both polarities, which is termed herein "absolute magnitude". The outputs of AND gates 350 and 352 are coupled up and down inputs of an up/down counter 354 so that the number of positive and negative pulses can be compared over any selected time interval.

Claims

1. A metering system for measuring electric power carried on a line, comprising: means for monitoring current and voltage signals on said line, including first signal means for producing a first analog signal proportional to one of said current and voltage signals and second signal means for producing a second analog signal proportional to the other of said current and voltage signals; modulator means for converting one of said analog signals to a first modulated signal changeable between two levels at predetermined first clock intervals in a manner proportional to said one of said analog signals; first multiplying means including means for gating the other of said analog signals in response to said first modulated signal to multiply said analog signals together and produce a product signal proportional to the power transported on the line; and first convertor means for converting said product signal to a first output signal which is modulated in a manner proportional to the value of said product signal and to the power carried on said line.

2. A metering system as in claim 1 in which said modulator means outputs said first modulated signal through a bistable circuit changeable at said first clock intervals, said modulator means further including modulator feedback means for producing a feedback signal that changes values simultaneously with changes in said first modulated signal and which balances said one of said analog signals over time, and a modulator measuring circuit for measuring instantaneous differences between said feedback signal and said one of said analog signals and for supplying a signal indicating such difference to said bistable circuit such that said first modulated signal changes levels in response to the measured difference between said one of said analog signals and said feedback signal.

3. A metering system as in claim 2 in which said modulator means includes a modulator summing node at which said one of said analog signals and said feedback signal are combined, said modulator measuring circuit including an integrator for integrating the signal at said modulator summing node and a comparator for comparing the integrated value produced by said integrator to a predetermined modulator threshold level.

4. A metering system as in. claim 2 in which said first converter means outputs said first output signal through a bistable circuit having an output changeable between two levels at predetermined converter clock intervals, said first converter means further including means for supplying said product signal to a summing node, feedback means responsive to said first output signal for supplying a second signal to said summing node which balances said product signal over time, said second signal being determined by the level of said first output signal, wherein any instantaneous difference between said product signal and said second signal is a difference signal appearing at said summing node, and a measuring circuit for integrating said difference signal and for comparing the integrated difference signal to a first threshold level, the output of said measuring circuit being supplied to said bistable circuit thereby causing said first output signal to be at one of said two levels depending on the level of said integrated difference signal relative to said first threshold level at each said converter clock interval, such that the average level over time for said first output signal is proportional to said product signal and to the power carried on said line.

5. A metering system as in claim 1 in which said first analog signal is proportional to said voltage signal and said second analog signal is proportional to said current signal.

6. A metering system as in claim 1 in which said first convertor means outputs said first output signal through a bistable circuit changeable at said converter clock intervals, said first converter means further including means for supplying said product signal to a summing node, feedback means responsive to said first output signal for supplying a second signal to said summing node which balances said product signal over time, said second signal being determined by the level of said first output signal, wherein any instantaneous difference between said product signal and said second signal is a difference signal appearing at said summing node, and a measuring circuit for integrating said difference signal and for comparing the integrated difference signal to a first threshold level, the output of said measuring circuit being supplied to said bistable circuit thereby causing said first output signal to be at one of said two levels depending on the level of said integrated difference signal relative to said first threshold level at each said convertor clock interval, such that the average level over time for said first output signal is proportional to said product signal and to the power carried on said line.

7. A metering system as in claim 6 in. which said product signal is of predominately a first polarity when power on said line is of a first polarity in which the predominant direction of power flow is in a first direction, said feedback means including a first reference source used when power on said line is of said first polarity, said first reference source having a polarity opposite said first polarity and a magnitude sufficient to balance said product signal, said first reference source being intermittently used as said second signal when said first output signal is at one level to drive said integrated difference signal across said first threshold in one direction, and further including a second reference source which is alternately used as said second signal when said first output signal is at the other of said two levels to permit said integrated different signal to cross said first threshold level in the other direction, such that said integrated difference signal is maintained in the vicinity of said first threshold level when power on said line is of said first polarity.

8. A metering system as in claim 7 including first digital gate means for receiving said first output signal and for producing a first pulse train having a pulse rate proportional to said first output signal.

9. A metering system as- in claim 7 in which said product signal is of predominantly a second polarity opposite said first polarity when power on said line is of a second polarity in which the predominant direction of power flow is in a second direction opposite said first direction, said convertor means including means for comparing said integrated difference signal to a second threshold level, said convertor means including a second bistable circuit for outputting a second output signal at one of two levels depending on the level of said integrated difference signal relative to said second threshold level at each said convertor clock interval, said feedback means including a third reference source used when power on said line is of said second polarity, said third reference source having a polarity opposite said second polarity and a magnitude sufficient to balance said product signal, said third reference source being intermittently used as said second signal when said second output signal is at one level to drive said integrated difference signal across said second threshold level in one direction, and further including a fourth reference source which is alternately used as said second signal when said second output signal is at the other of said two levels to permit said integrated difference signal to cross said second threshold level in the other direction, such that said integrated difference signal is maintained in the vicinity of said second threshold level when power on said line is of said second polarity.

10. A metering system as in claim 9 which said second and fourth reference sources have the same value.

11. A metering system as in claim 10 in which . said second and fourth reference sources both are connections to a common ground for said metering system, and said first output signal is proportional to said first polarity of power flow and said second output signal is proportional to said second polarity of power flow on said line.

12. A metering system as in claim 9 including second digital gate means for receiving said second output signal and for producing a second pulse train having a pulse rate proportional to said second output signal .

13. A metering system as in claim 12 including first digital gate means for receiving said first output signal and for producing a first pulse train having a pulse rate proportional to said first output signal and including counter means for receiving said first and second pulse trains and for counting the pulses therein to determine the power flow on said line.

14. A metering system as in claim 1 including means for producing said other of said analog signals in both inverted and non-inverted forms, wherein said inverted and non-inverted forms of said other of said analog signals are supplied to said multiplying means, said multiplying means further including switch means for supplying said inverted and non-inverted forms of said other analog signal to a common point alternately in response to said first modulated signal to form said product signal.

15. A metering system as in claim 1 including phase shifting means for adjusting the phase relationship between the signals supplied to said multiplying means such that said product signal is proportional to a selected phase relationship power value of the power carried on said line.

16. A metering system as in claim 15 in which said phase shifting means is a time delay means which delays one of the signals supplied to said multiplying means by a selected time interval.

17. A metering system as in claim 1 including a shift register for delaying said first modulated signal by a selected time interval such that the phase relationship between the signals multiplied together in said metering system is modified to measure a selected phase relationship power value, said shift register receiving said first modulated signal and outputting a delayed first modulated signal which is delayed in time by a selected interval.

18. A metering system as in claim 17 in which said delayed first modulated signal and said other of said analog signals are supplied to a second multiplying means which includes means for gating the other of said analog signals in response to said delayed first modulated signal to multiply said signals together and produce a second product signal proportional to a selected phase relationship power value of the power transported on said line, and including second converter means for converting said second product signal to a phase relationship first output signal which is modulated in a manner proportional to the value of said second product signal and to the selected phase relationship power value of the power carried on said line.

19. A metering system as in claim 1 in which at least one of said monitoring means, modulator means and first convertor means incorporates N amplifier elements each having a plurality of inputs, said system including offset compensation means for substantially eliminating errors due to voltage offset between selected inputs of each of said N amplifier elements, said offset compensation means including N offset storage elements connected respectively to a selected first input of each said amplifier element for receiving a compensation voltage which substantially reduces the offset error at a selected second input of the amplifier element, wherein any difference between said compensating voltage and the voltage offset of the amplifier element is an error voltage appearing at said second input, and including a nulling circuit which can be connected sequentially to each of said N amplifier elements and to the offset storage element associated therewith such that each said amplifier element sequentially becomes the selected amplifier element being offset compensated, said nulling circuit first being connected to said second input of said selected amplifier element during an intermittent transfer period to determine said error voltage and then being connected to said offset storage element connected to said first input of said selected amplifier element to transfer charge to said offset storage element during an intermittent transfer period following said charging period, said offset compensation means including means for sequentially providing said transfer and charging periods for each of said N amplifier elements such that offset errors in said metering system are substantially eliminated.

20. A metering system as in claim 19 in which said nulling circuit includes a charging amplifier, a temporary storage element connected to said charging amplifier, and means for transferring said error voltage from said second input of said selected amplifier element through said charging amplifier to said temporary storage element during said transfer period.

21. A metering system as in claim 20 in which said temporary storage element has first and second terminals, and said offset compensation means includes means for connecting said first terminal of said temporary storage element to a feedback loop between an input and the output of said charging amplifier and for connecting said second terminal of said temporary storage element to a common ground during each said transfer period such that said error voltage is transferred to said temporary storage element, and including means for disconnecting said second terminal from said common ground and for connecting said second terminal to the output of said charging amplifier during each said subsequent charging period, such that a voltage proportional to the error voltage of said selected amplifier element appears at said output of said charging amplifier during said charging period.

22. A metering system as in claim 21 in which said offset compensation means further includes means for connecting the output of said charging amplifier to said offset storage element connected to said selected amplifier element during said charging period, such that a current is supplied to said offset storage element proportional to said error voltage of said selected amplifier element to thereby adjust the voltage on said offset storage element in a direction which reduces said error voltage during the next transfer period of said selected amplifier element.

23. In a metering system for measuring electric power carried on a line, which includes means for monitoring current and voltage signals on said line and for producing a first analog signal proportional to one of said current and voltage signals and a second analog signal proportional to the other of said current and voltage signals, means for multiplying said first and second analog signals together to produce a product signal proportional to the power transported on the line, and means for converting said product signal to an output signal which is proportional to the value of said product signal and to the power carried on said line, and which includes N amplifier elements each having a plurality of inputs in at least one of said monitoring, multiplying and converting means, an offset compensation system for substantially eliminating errors due to voltage offset between selected inputs of each of said N amplifier elements, said offset compensation system comprising: N offset storage elements one of which is connected respectively to a selected first input of each said amplifier element for receiving a compensating voltage which substantially reduced the offset error at a selected second input of the amplifier element,, wherein any difference between said compensating voltage and the voltage offset of the amplifier element is an error voltage appearing at said second input, and including a nulling circuit which can be connected sequentially to each of said N amplifier elements and to the offset storage element associated therewith such that each said amplifier element sequentially becomes the selected amplifier element being offset compensated, said nulling circuit first being connected to said second input of said selected amplifier element during an intermittent transfer period to determine said error voltage and then being connected to said offset storage element connected to said first input of said selected amplifier element to transfer charge to said offset storage element during an intermittent charging period following said transfer period, said offset compensation system including means for sequentially providing transfer and charging period for each of said N amplifier elements such that offset errors in said metering system are substantially eliminated.

24. In a metering system as in claim 23 in which said nulling circuit includes a charging amplifier, a temporary storage element connected to said charging amplifier, and means for transferring said error voltage from said second input of said selected amplifier element through said charging amplifier to said temporary storage element during said transfer period.

25. In a metering system as in claim 23, said temporary storage element in said offset compensation system including first and second terminals and said offset compensation system including means for connecting said first terminal of said temporary storage element to a feedback loop between an input and the output of said charging amplifier and for connecting said second terminal of said temporary storage element to a common ground during each said transfer period, such that said error voltage is transferred to said temporary storage element, and including means for disconnecting said second terminal from said common ground and for connecting said second terminal to the output of said charging amplifier during each said subsequent charging period, such that a voltage proportional to the error voltage of said selected amplifier element appears at said output of said charging amplifier during said charging period.

26. In a metering system as in claim 25, said offset compensation system further including means for connecting the output of said charging amplifier to said offset storage element connected to said selected amplifier element during said charging period, such that a current is supplied to said offset storage element proportional to said error voltage of said selected amplifier element to thereby adjust the voltage on said offset storage element in a direction which reduces said error voltage during the next transfer period of said selected amplifier element.

27. A system for offset. compensating a plurality of amplifier elements up to N amplifier elements, each having a plurality of inputs, to substantially eliminate errors due to voltage offset between selected inputs of each of said amplifier elements, comprising: N storage elements connected to said N amplifier elements such that one of said storage elements is connected to a selected input of each said amplifier element, wherein said storage elements are for receiving a compensating voltage which substantially reduces the offset error at a selected second input of the associated amplifier element and any difference between said compensating voltage and the voltage offset of the amplifier element appears as an error voltage at said second input, and including a nulling circuit which can be connected sequentially to each of said N amplifier elements and to the storage element associated therewith such that each said amplifier element sequentially becomes the selected amplifier element being offset compensated, said nulling circuit first being connected to said second input of a selected amplifier element during an intermittent transfer period to determine said error voltage and then being connected to said storage element connected to said first input of said selected amplifier element to transfer charge to said storage element during an intermittent charging period following said transfer period, said offset compensation system including means for sequentially providing transfer and charging periods for each of said N amplifier elements such that offset errors at said second input are substantially eliminated.

28. An offset compensation system as in claim 27 in which said nulling circuit includes a charging amplifier, a temporary storage element connected to said charging amplifier, and means for transferring said error voltage from said second input of said selected amplifier element through said charging amplifier to said temporary storage element during said transfer period.

29. An offset compensation system as in claim 27 in which said temporary storage element in said offset compensation system includes first and second terminals and said offset compensation system includes means for connecting said first terminal of said temporary storage element to a feedback loop between an input and the output of said charging amplifier and for connecting said second terminal of said temporary storage element to a common ground during each said transfer period such that said error voltage is transferred to said temporary storage element, and including means for disconnecting said second terminal from said common ground and for connecting said second terminal to the output of said charging amplifier during each said subsequent charging period, such that a voltage proportional to the error voltage of said selected amplifier element appears at said output of said charging amplifier during said charging period.

30. An offset compensation system as in claim 29 further including means for connecting the output of said charging amplifier to said storage element connected to said selected amplifier element during said charging period, such that a current is supplied to said storage element proportional to said error voltage of said selected amplifier element to thereby adjust the voltage on said storage element in a direction which reduces said error voltage during the next transfer period of said selected amplifier element.

31. A method of metering electric power carried on a line, comprising the steps of: monitoring current and voltage on said line and producing a first analog signal proportional to one of the current and voltage signals and producing a second analog signal proportional to the other of said current and voltage signals, modulating one of said analog signals to produce a first modulated signal proportional to said one of said analog signals, which is changeable between two levels at predetermined first clock intervals, gating the other of said analog signals in response to changes in the level of said first modulated signal to multiply said signals together and produce a product signal proportional to the power transported on the line, and converting said product signal to a first output signal which is modulated in a manner proportional to the value of said product signal and to the power carried on said line.

32. A method as in Claim 31 in which said modulating step includes producing a feedback signal which changes value simultaneously with changes in said first modulated signal and which balances said one of said analog signals over time, and measuring instantaneous differences between said feedback signal and said one of said analog signals and supplying a signal indicating such difference to a bistable circuit which outputs said first modulated signal at one of said two levels depending on the measured difference between said feedback signal and said one of said analog signals at each said first clock interval.

33. A method as in Claim 32 in which said modulating step includes supplying said one of said analog signals and said feedback signal to a summing node, and said measuring step includes integrating the signal at said summing node representing the difference between said one of said analog signals and said feed back signal, and then comparing the integrated value produced by said integrating step to a predetermined modulator threshold level 30.

34. A method as in claim 31 in which said step of converting said product signal includes producing said first output signal through a bistable circuit having an output changeable between two levels at predetermined converter clock intervals, supplying said product signal to a summing node, supplying a second signal to said summing node from a plurality of reference sources in response to the level of said first output signal, wherein said second signal balances said product signal over time and any instantaneous difference between said product signal and said second signal is a difference signal and comparing the integrated difference signal to a first threshold level, and then causing the bistable circuit to output said first output signal at one of said two levels depending on the level of said integrated difference signal relative to said first threshold level at each said converter clock interval .

35. A method as in claim 34 in which said product signal is of predominantly a first polarity when power on said line is of a first polarity in which the predominant direction of power flow is in a first direction, said converting step including supplying said second signal to said summing node from a first reference source having a polarity opposite said first polarity and a magnitude sufficient to balance said product signal, including using said first reference source as said second signal whenever said first output signal is at one level to drive said integrated difference signal across said first threshold level in one direction, and alternating said first reference source with a second reference source when said first output signal is at the other of said two levels to permit said integrated difference signal to cross said first threshold level in the other direction, such that said integrated difference signal is maintained in the vicinity of said first threshold level when power on said line is of said first polarity.

36. A method as in claim 35 in which said product signal is of predominantly a second polarity opposite said first polarity when power on said line is of a second polarity in which the predominant direction of power flow is in a second direction opposite said first direction, said converting step including comparing said integrated difference signal to a second threshold level different from said first threshold level, and outputting a second output signal through second bistable circuit which outputs said second output signal at one of two levels depending on the level of said integrated difference signal relative to said second threshold level at each said convertor clock interval, and including supplying said second signal from a third reference source when power on said line is of said second polarity, said third reference source having polarity opposite said second polarity and a magnitude sufficient to balance said product signal, said third reference source being used as said second signal whenever said second output signal is at one level to drive said integrated difference signal across said second threshold level in one direction, and alternating said third reference source with a fourth reference source when said second output signal is at the other of said two levels to permit said integrated difference signal to cross said second threshold level in the other direction, such that said integrated difference signal is maintained in the vicinity of said second threshold level when power on said line is of said second polarity.

37. A method as in claim 36 in which said second and fourth reference sources are the same, and said converting step included supplying said second signal to said summing node from one of said first, third and said equal second and fourth reference sources.

38. A method as in claim 31 including the step of inverting said other of said analog signals and supplying both said inverted signal and the non- inverted other of said analog signals to means for performing said gating step.

39. A method as in claim 31 including the use of N amplifier elements each having a plurality of input to perform at least some of the steps of the method, and including the additional steps of offset compensating said N amplifier elements to eliminate errors due to voltage offset between selected inputs of each of said N amplifier elements, each of said amplifier elements being connected respectively to an offset storage element at a first selected input thereof on which a compensating voltage is stored by the offset compensation steps of the method to substantially correct for any offset errors at a second selected input of the amplifier element, and wherein any difference between said compensating voltage on said offset storage element and the voltage offset of the amplifier element is an error voltage appearing at said second input, said offset compensation steps including sequentially connecting a nulling circuit to each of said N amplifier elements and to the offset storage element associated therewith to offset compensate each selected amplifier element in sequence by means of the offset compensation steps, including first connecting said nulling circuit to said second input of said selected amplifier element during an intermittent transfer period to determine said error voltage and then connecting said nulling circuit to said offset storage element connected to said first input of said selected amplifier element during an intermittent charging period following said transfer period to adjust the charge on said offset storage element during said charging period such that the error voltage during the next said transfer period of said selected amplifier element is reduced, and including the steps of sequentially providing for transfer and charging periods for each of said N amplifier elements in a continuous cycle.

40. A method as in claim 39 in which said nulling circuit includes a charging amplifier and a temporary storage element having first and second terminals, said offset compensation steps including connecting one input of said charging amplifier to said second input of said selected amplifier element and connecting said first terminal of said temporary storage element in a feedback loop between an input and output of said charging amplifier during each said transfer period, and simultaneously connecting said second terminal of said temporary storage element to a common ground during said transfer period, such that said error voltage is transferred through said charging amplifier to said temporary storage element, and then disconnecting said second terminal from said common ground and connecting said second terminal to said output of said charging amplifier during the subsequent charging period whereby a voltage which is proportional to said error voltage appears at said output of said charging amplifier during said charging period.

41. A method as in claim 40 in which said offset compensation steps further include connecting during each said charging period the output of said charging amplifier to said offset storage element connected to said selected amplifier element through an impedance such that a current is supplied to said offset storage element proportional to said error voltage to thereby adjust the voltage on said offset storage element in a direction which reduces said error voltage during the next transfer period of the selected amplifier element.

42. A method of metering electric power carried on a line by monitoring the current and voltage on the line, producing a first analog signal proportional to one of the current and voltage signals and a second analog signal proportional to the other of the current and voltage signals, multiplying the first and second analog signals together to produce a product signal proportional to the power transported on the line, converting the product signal to an output signal which is proportional to the value of the product signal and to the power carried on the line, wherein the metering system for accomplishing the method includes N amplifier elements each having a plurality of inputs, said N amplifier elements being used to perform at least some of the steps of the method, and including the additional steps of offset compensating said N amplifier elements to eliminate errors due to voltage offset between selected inputs of each of said N amplifier elements, each of said amplifier elements being connected respectively to an offset storage element at a first input thereof on which a compensating voltage is stored by the offset compensation steps of the method to substantially correct for any offset errors at a second input of the amplifier element, and wherein any difference between said compensating voltage on said offset storage element and the voltage offset of the amplifier element is an error voltage appearing at said second input, said offset compensation steps including sequentially connecting a nulling circuit to each of said N amplifier elements and to the offset storage element associated therewith to offset compensate each selected amplifier element in sequence, including first connecting said nulling circuit to said second input of said selected amplifier element during an intermittent transfer period to determine said error voltage, then connecting said nulling circuit to said offset storage element connected to said first input of said selected amplifier element during an intermittent charging period following said transfer period to adjust the charge on said offset storage element during said charging period, such that the error voltage during the next said transfer period of said selected amplifier element is reduced, and including the steps of sequentially providing for transfer and charging periods for each of said N amplifier elements in a continuous cycle.

43. A method as in claim 42 in which said nulling circuit includes a charging amplifier and a temporary storage element having first and second terminals, said offset compensation steps further including connecting one input of said charging amplifier to said other input of said selected amplifier element and connecting said first terminal of said temporary storage element in a feedback loop between an input and output of said charging amplifier during each said transfer period, and simultaneously connecting said second terminal of said temporary storage element to a common ground during said transfer period, such that said error voltage is transferred through said charging amplifier to said temporary storage element, and then disconnecting said second terminal from said common ground and connecting said second terminal to said output of said charging amplifier during the subsequent charging period whereby a voltage which is proportional to said error voltage appears at said output of said charging amplifier during said charging period.

44. A method as in claim 43 in which said offset compensation steps further include connecting during each said charging period the output of said charging amplifier to said offset storage element through an impedance such that a current is supplied to said offset storage element proportional to said error voltage to thereby adjust the voltage on said offset storage element in a direction which reduces said error voltage during the next transfer period of the selected amplifier element.

45. A method of offset compensating a plurality of amplifier elements up to N amplifier elements, each having a plurality of inputs, to substantially eliminate errors due to voltage offset between selected N inputs of each of said amplifier elements using a nulling circuit for measuring a voltage and for producing a current proportional to said voltage, wherein each of said amplifier elements is connected respectively to a storage element at a first input thereof on which a compensating voltage is stored by the steps of the method to substantially correct for any offset errors at a second input of the amplifier element, and wherein any difference between said compensating voltage on said storage element and the voltage offset of the amplifier element is an error voltage appearing at said second input, comprising the steps of sequentially connecting said nulling circuit to each of said N amplifier elements and to the storage element associated therewith to offset compensate each selected amplifier element in sequence, including first connecting said nulling circuit to said second input of said selected amplifier element during an intermittent transfer period to determine said error voltage, then connecting said nulling circuit to said storage element connected to said first input of said selected amplifier element during an intermittent charging period following said transfer period to adjust the charge on said storage element during said charging period, such that the error voltage during the next said transfer period of said selected amplifier element is reduced, and including the steps of sequentially providing for transfer and charging period for each of said N amplifier elements in a continuous cycle.

46. A method as in claim 45 in which said nulling circuit includes a charging amplifier and a temporary storage element having first and second terminals, said method further including the steps of connecting one input of said charging amplifier to said other input of said selected amplifier element and connecting said first terminal of said temporary storage element in a feedback loop between an input and output of said charging amplifier during each said transfer period, and simultaneously connecting said second terminal of said temporary storage element to a common ground during said transfer period, such that said error voltage is transferred through said charging amplifier to said temporary storage element, and then disconnecting said second terminal from said common ground and connecting said second terminal to said output of said charging amplifier during the subsequent charging period whereby a voltage which is proportional to said error voltage appears at said output of said charging amplifier during said charging period.

47. A method as in claim 45 further including connecting during each said charging period the output of said charging amplifier to said storage element such that a current is supplied to said storage element proportional to said error voltage to thereby adjust the voltage on said storage element in a direction which reduces said error voltage during the next transfer period of the selected amplifier element.

48. A modulator for converting an input signal to an output pulse train which varies between two levels and which has an average level over time proportional to the input signal, comprising: means for supplying said signals to a summing node, switch means for supplying a second signal to said summing node selected from at least two different reference signals having predetermined magnitudes, wherein the difference at any time between said input signal and said second signal is a difference signal, measuring means for integrating the difference signal at said summing node and for determining when the integrated difference signal reaches a threshold level, said measuring means including an amplifier element and offset compensation means for substantially eliminating any offset error resulting from a voltage offset existing between the amplifier inputs of said amplifier element, said compensation means including a first storage element connected to one said amplifier input and means for transferring an offsetting voltage to said first storage element to compensate for said voltage offset, a clock for producing clock pulses at predetermined clock intervals, a bistable circuit responsive to said measuring means and said clock and which produces a first output signal changeable at each said clock pulse between first and second levels whenever said integrated difference signal has crossed said threshold level during a clock interval, said switch means being responsive to said bistable circuit such that one of said reference signals is supplied to said summing node when said first output signal is at its first level and another reference signal is supplied to said summing node when said first output signal is at its second level, wherein the average value of the reference signals over time balances said input signal at said summing mode and the average level over time of said first output signal is proportional to said input signal.

49. A modulator as in claim 48 in which said second signal is selected from two said reference signals which are substantially equal in magnitude and opposite in polarity.

50. A modulator as in claim 48 in which said measuring means includes a second storage element connected between said summing node and a common ground, said second storage element providing part of a passive integration means for integrating said difference signal, the voltage on said summing node being said integrated difference signal.

51. A modulator as in claim 50 in which said amplifier element serves as a comparator for determining when a signal input to said amplifier element reaches a threshold level, said amplifier element having one input connected in an electrical path to said summing node and the output connected to said bistable circuit, said amplifier element outputting a first control signal which is high when said integrated difference signal is above said threshold level and low when said integrated difference signal is below said threshold level.

52. A modulator as in claim 51 in which said first storage element is in the electrical path between said summing node and the inverting input of said amplifier element, the non-inverting input being connected to said common ground, said offset compensation means including a feedback loop around said amplifier element between said inverting input of said amplifier element and the output thereof which is connected periodically during an intermittent nulling period such that any voltage offset appears at low impedance at said inverting input during said nulling period, together with means for simultaneously disconnecting one terminal of said first storage element from said summing node and connecting said one terminal to said common ground such that said voltage offset is stored on said first storage element during said nulling period, said nulling periods alternating with measuring periods in which said feedback loop around said amplifier element is disconnected and said one terminal of said first storage element is reconnected to said summing node whereby the voltage offset of said amplifier element is balanced by the voltage on said first storage element during the measuring period.

53. A modulator as in claim 52 including means for synchronizing said nulling and measuring periods with said clock pulses such that said nulling periods occur during a portion of each said clock interval and said measuring periods occur when said first output signal from said bistable circuit is changeable in response to said measuring means.

54. A modulator as in claim 50 in which said measuring means includes first and second amplifier elements which serve as comparators for determining when a signal input to said amplifier element reaches a threshold level, said amplifier elements each having one input connected in an electrical path to said summing node, together with offset compensation means which include a first storage element on which said offsetting voltage is stored connected in said electrical path to one input of each said amplifier element, the outputs of said first and second amplifier elements being connected to said bistable circuit alternately during respective first and second measuring periods in which the amplifier element connected to said bistable circuit outputs a first control signal which is high when said integrated difference signal is above said threshold level and low when said integrated difference signal is below said threshold level, and including means for charging the first storage element connected to said first amplifier element to said offsetting voltage during a first amplifier nulling period while said second amplifier element is connected to said bistable circuit and for changing the first storage element connected to said second amplifier element to said offsetting voltage during a second amplifier nulling period while said first amplifier element is connected to said bistable circuit, said first amplifier nulling periods occurring between first measuring periods and said second amplifier nulling periods occurring between second measuring periods.

55. A modulator as in claim 54 in which said one input of each said amplifier element connected in an electrical path to said summing node is the inverting input thereof, and said offset compensation means includes a switchable feedback loop around each said amplifier element which is selectively connected during each respective amplifier nulling period between the inverting input of the respective amplifier element and the output thereof such that any voltage offset appears at low impedance at said respective inverting input, and means for transferring during the nulling period of each said amplifier element the voltage offset of the amplifier element to the connected first storage element.

56. A modulator as in claim 54 in which said offset compensation means causes the nulling period of each said amplifier element to be shorter than the measuring period thereof, such that said first amplifier nulling period ends a predetermined interval before the measuring period of said first amplifier element begins and said second amplifier nulling period ends a predetermined interval before the measuring period of said first amplifier element begins so as to minimize errors due to slow comparator response.

57. A modulator as in claim 48 in which one terminal of said amplifier element is connected to said summing node and the other terminal of said amplifier element is connected to said first storage element on which said offsetting voltage is stored.

58. A modulator as in claim 57 in which said amplifier element is a first amplifier element of said measuring means, which also includes a second storage element connected in a negative feedback loop between the inverting input and output of said first amplifier element, said inverting input also being connected to said summing node such that said integrated difference signal appears across said second storage element, and including a comparator element connected between the output of said first amplifier element and said bistable circuit, said comparator element determining when said integrated difference signal on said second storage element reaches a threshold level.

59. A modulator as in claim 58 in which any difference between the offsetting voltage on said first storage element and the actual voltage offset of said first amplifier element is an error voltage which appears at the inverting input of said first amplifier element, said offset compensation means including means for intermittently connecting said inverting input of said first amplifier element to the non-inverting input of a second amplifier element during a transfer period, and including a temporary storage element having a first terminal connected during said transfer period to both the output and to the inverting input of said second amplifier element, and a second terminal connected to a common ground during said transfer period, said offset compensation means also providing a charging period during which said first storage element is connected to the non-inverting input of said second amplifier element and said output thereof is disconnected from said first and connected to said second terminal of said temporary storage element such that a negative voltage equal to said error voltage appears at the output of said second amplifier element, and means for connecting the output of said second amplifier element to said first storage element through an impedance during said charging period such that a current is supplied to said first storage element proportional to said error voltage to change the voltage on said first storage element in a direction which reduces said error voltage during the next transfer period.

60. A system for producing digital signals proportional to selected parameters of an input signal which has been converted to a first modulated signal varying between two levels in a manner proportional to the amplitude and polarity of the input signal, said system comprising: means for producing clock pulses at predetermined clock intervals, delaying means for receiving said first modulated signal and for outputting a second modulated signal substantially equal to said first modulated signal and delayed in time by one said clock interval, and means for outputting a first digital signal containing output pulses at intervals of not less than said clock intervals whenever said first and second modulated signals are simultaneously at predetermined levels, such that said first digital signal carries magnitude and polarity information relating to said input signal.

61. A system as in claim 60 in which said first modulated signal is changeable between first and second levels at said clock intervals in a manner which produces an average level over any sufficient interval proportional to said input signal, said means for outputting a first digital signal outputting pulses at not less than said clock intervals when said first and second modulated signals are simultaneously at said first level, such that said first digital signal contains pulses in proportion to the amount of time by which the first level of said first modulated signal exceeds the second level.

62. A system as in claim 61 including inverting means for producing a first inverse modulated signal which is the inverse of said first modulated signal and a second inverse modulated signal which is the inverse of said second modulated signal, and means for outputting a second digital signal containing pulses at not less than said clock intervals when said first and second inverse modulated signals are simultaneously at predetermined levels, such that said second digital signal contains pulses in proportion to the amount of time by which one level of said first inverse modulated signal exceeds the other level.

63. A system as in claim 62 in which said input signal is converted in a modulator that includes a first bistable circuit having Q and Q outputs, said first modulated signal being the Q output of said bistable circuit, said inverting means including using the (2 output of said first bistable circuit to provide said first inverse modulated signal, said delaying means being a second bistable circuit having Q and Q outputs, said second bistable circuit receiving said first modulated signal at its Q output which duplicates said first modulated signal with a time delay of one said clock interval, said inverting means including using said Q output of said second bistable circuit to provide said second inverse modulated signal.

64. A system as in claim 62 in which the amount of time by which one level of said first modulated signal exceeds the other over any sufficient interval is proportional to the magnitude of one polarity of said input signal, said system further including gate means for receiving said first and second digital signals and for outputting a summation digital signal which is the sum of said first and second digital signals and is proportional to the absolute magnitude of said input signal.

65. A system as in claim 60 in which said delaying means includes a bistable circuit which receives said first modulated signal at an input thereof and said clock pulses and produces an output which is said second modulated signal and which follows and duplicates any changes in said first modulated signal delayed in time by one said clock interval.

66. A system for producing digital signals proportional to selected output parameters of an input signal, comprising: means for producing clock pulses at predetermined clock intervals, a modulator for converting the input signal to a first modulated signal, said modulator including a first bistable circuit which outputs at a Q output thereof said first modulated signal changeable at said clock pulses between first and second levels in a manner which produces an average level over any sufficient interval proportional to said input signal, a second bistable circuit which receives said first modulated signal and said clock pulses and outputs a second modulated signal with a time delay of one said clock intervals, and means for outputting a first digital signal containing output pulses at intervals of not less than said predetermined intervals when said first and second modulated signals are simultaneously at said first level, such that said first digital signal carries pulses in proportion to the amount of time by which the first level of said modulated signal exceeds the second level and also in proportion to the magnitude of one polarity of said input signal.

67. A system as in claim 66 in which said first and second bistable circuits each have an additional Q output, the Q output of said first bistable circuit producing a first inverse modulated signal which is the inverse of first modulated signal and said Q output of said second bistable circuit producing a second inverse modulated signal which is the inverse of said second modulated signal, means for outputting a second digital signal containing output pulses at not less than said predetermined intervals when said first and second inverse modulated signals are simultaneously at said first level, such that said second digital signal carries pulses in proportion to the amount of time by which the second level of said first modulated signal exceeds the first level and also in proportion to the magnitude of the other polarity of said input signal.

68. In a system for multiplying a first and a second signal together to produce a product signal, means for adjusting the phase relationship between the first and second signals and for producing a product signal which is proportional to a selected phase relationship product value, said means comprising: digital shifter means for producing a selected time adjustment in at least one of said first and second signals to produce a selected phase relationship between said first and second signals, said digital shifter means including means for delaying a signal input thereto by a selected number of discrete intervals to produce said selected time adjustment in a manner independent of the signal being adjusted, and means for multiplying said first and second signals together to produce a product signal which is proportional to the product value of said first and second signals having said selected phase relationship.

69. Means as in claim 68 further including a modulator for modulating one of said first and second signals to produce a modulated signal changeable between two levels at predetermined clock intervals, wherein the modulated signal changes in a manner proportional to said one of said first and second signals and is used in said means for multiplying to produce said product signal.

70. Means as in claim 69 in which said digital shifter means receives said modulated signal and produces said selected time delay by delaying said modulated signal a selected number of discrete intervals.

71. Means as in claim 70 in which the discrete intervals by which a signal is delayed by said means for delaying are synchronized with said clock intervals of said modulator.

72. Means as in claim 70 in which said means for delaying includes a first shift register which is clocked at selected predetermined first intervals for delaying said modulated signal by a selected number of said first intervals.

73. Means as in claim 72 in which said first intervals are equal to said clock intervals of said modulator.

74. Means as in claim 72 in which said first intervals are shorter than said clock intervals of 4aid modulator.

75. Means as in claim 70 in which said means for delaying includes a plurality of shift registers clocked at selected predetermined intervals, including a first shift register clocked at first intervals for delaying said modulated signal by a selected number of said first intervals and a second shift register clocked at second intervals shorter than said first intervals for delaying said modulated signal by a selected amount which is shorter than one of said first intervals whereby a delay in said modulated signal which is the sum of a selected number of first and second intervals can be achieved.