WO1981002211A1 - Memoire a acces selectif servant d'interface aux controleurs d'impression et de format dans un systeme d'imprimante - Google Patents

Memoire a acces selectif servant d'interface aux controleurs d'impression et de format dans un systeme d'imprimante Download PDF

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Publication number
WO1981002211A1
WO1981002211A1 PCT/US1981/000065 US8100065W WO8102211A1 WO 1981002211 A1 WO1981002211 A1 WO 1981002211A1 US 8100065 W US8100065 W US 8100065W WO 8102211 A1 WO8102211 A1 WO 8102211A1
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WIPO (PCT)
Prior art keywords
control
printing
print
memory means
memory
Prior art date
Application number
PCT/US1981/000065
Other languages
English (en)
Inventor
D Yeomans
R Buba
K Boulanger
Original Assignee
Centronics Data Computer
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Filing date
Publication date
Application filed by Centronics Data Computer filed Critical Centronics Data Computer
Publication of WO1981002211A1 publication Critical patent/WO1981002211A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/12—Digital output to print unit, e.g. line printer, chain printer
    • G06F3/1297—Printer code translation, conversion, emulation, compression; Configuration of printer parameters

Definitions

  • the present invention relates to data formatt ⁇ ing and more particularly to a novel data formatting device for use in controlling a printer employing a print controller through a communications memory which is shared by the aforesaid print controller and the formatting device to control the format of the line to be printed.
  • dot matrix printers typically employ a microprocessor and a memory which is preferably comprised of a random access memory for storing input data received over a data bus controlled by the micro ⁇ processor and which outputs data directly to the data bus of a microprocessor.
  • the binary codes representing either characters to be printed or control codes are loaded into a memory. Each binary word is examined to determine whether it is a control code or a character code. If the binary word received is a character code, it is loaded into memory and a character counter is incremented.
  • the printer When the character counter reaches a count representative of receipt of a full line of print, the printer is activated to print the line, typically serial by dot column and serial by character, as is conventional with single print head printers of both the unidirectional and bidirec ⁇ tional type. Printing is initiated when the character counter indicates loading of a number of characters equivalent to a full line of print or upon receipt of a print command code.
  • the character counter indicates loading of a number of characters equivalent to a full line of print or upon receipt of a print command code.
  • it is conventional to transmit one line of character information and a control code for each different characteristic of the line of print.
  • code words are loaded into memory under control of the printer and not under control of the remote facility.
  • the remote facility has no knowledge of the status of the printer other than the fact that it is busy or that it is free to accept data.
  • the present invention is characterized by comprising a peripheral device, a printer in the present case, having a print controller and a communica ⁇ tions memory adapted to be selectively accessed by- the print controller and the format controller of a host
  • C::PI system which is adapted to receive and store a complex combination of character and format data during a single transmission per line of characters thereby signi icantly reducing the time required for transmission of a line of print having a complex format and further significantly increasing the versatil ⁇ ity of the system to the needs of the host system which may require a wide variety of complex formats.
  • the printer communicates with the remote facility through the communications memory to provide detailed information regarding printer status .
  • the printer of the present invention is a bi-directional printer of the logic seeking type in which the print head is brought to a halt upon completion of the last line of print while maintaining a count of the print head position.
  • the present position of the head is compared against the end points of the next full line or partial line of characters to be printed in order to determine the shorter distance the print head may travel to begin printing the next -line.
  • the printer is of the dot matrix type designed to successively print adjacent vertical dot colu ns and has an additional dot printing position for underlining purposes . Both the print head and the paper are advanced by stepper motors.
  • Communication RAM (hereinafter "Communications RAM” ) is shared by a format controller, which is a part of the host system controll ⁇ ing the printer, and a print controller comprising the logic for effecting printing and other related opera- tions.
  • the said memory is adapted to store status information, control codes and data codes.
  • Printer status information is generated by the print controller and indicates whether a fault has occurred, any event has been aborted or partially - aborted and the precise status of the printer up to the moment of the failure, which information is made immediately available to the host system the next time it accesses the memory for purposes of undertaking remedial action.
  • the format controller and print controller gain access to the Communications RAM in an alternating fashion whereby the format controller loads the Communications RAM in accordance with the next step or group of steps to be carried out at which time the format controller relinquishes control of the Communica ⁇ tions RAM to the print controller carries out the operations called for in memory and updates the appropri ⁇ ate status information.
  • the Communications RAM is adapted to receive and store the following types of information:
  • Print command data codes sufficient in number to print a full line of characters which in the present example consists of a 132 character line 7x8 dot matrix characters whose character width enable printing of twelve characters per inch. . Forward paper movement after printing
  • OM events may be carried in the printer each time it assumes control of the Communications RAM.
  • the paper feed events are controlled by a control code calling for a paper feed and the appropriate direction of paper feed and an argument representing the number of steps which the paper is to be advanced or reversed.
  • the printing control code is comprised of a mult-bit binary word capable of controlling the printer to: 1. Print a line or partial line of standard size characters.
  • the Communications RAM has a portion of its memory allocated to storage of code words.
  • the 8-bit word allows up to 256 different codes.
  • the Print controller detects the presence of a print command, the Communications RAM is examined for printable codes .
  • the print controller employs a logic seeking routine for selecting the shorter head movement between print lines. As printable codes are removed for printing they are replaced by space codes. Upon completion of printing, the Communications RAM is reset in readiness for receipt of a new data transfer.
  • the print controller When printing characters of ten character per inch size, 132 characters per line, the print controller interrogates all 132 bytes in the character block portion of the Communications RAM for printable codes. When expanded characters are called for, only the first 66 characters in the Communications RAM are interrogated.
  • the print controller is provided with character generators comprised of memories, each having a capacity sufficient to store dot information for at least 128 characters. Consecutive locations in said memories are utilized to store the 7x8 dot matrix for each character.
  • character generators comprised of memories, each having a capacity sufficient to store dot information for at least 128 characters. Consecutive locations in said memories are utilized to store the 7x8 dot matrix for each character.
  • the versatility of the system of the present invention allows a wide variety of printing formats including, but not'limited to, printing full or partial lines of standard size characters; full or partial lines of standard size characters underlined; full or partial lines of elongated characters or underlined elongated characters; mixed lines of normal and elongated charac ⁇ ters; mixed lines of characters which are not underlined with characters that are underlined; partial lines of characters having subscripts/or superscripts, to name just a few of the possible formats.
  • the print controller continuously updates printer status to provide continuously updated information regarding the status of the printer at any given time to allow the host system to take any appropriate remedial action.
  • Loading of the communications memory is totally under control of the format controller. Reading of the communications memory is totally under control of the print controller. Decoding circuitry is totally elimin- ated since the activity requested is determined by examining the memory locations allocated for this purpose. Although the read out sequence is fixed, loading of the communications memory may take place in any order.
  • Still another object of the present invention is to provide a novel electronic solid state control of the type described and having a print controller which continuously monitors and updates printer status in order to share status information with the host system through the insertion of said data into said shared memory by the host system which gains access to said shared memory through its format controller.
  • Still another object of the present invention is to provide for the two-way interchange of data between a host system and one or more input/output devices by means of a shared memory.
  • Another object of the present invention is to provide for the interchange of information between a host system and a peripheral device through a shared memory which is alternately controlled exclusively by said host system and the controller of the peripheral device.
  • Still another object of the present invention is to provide for the interchange of data between a host system and a peripheral device through a shared memory wherein the requested operations are determined by the presence of data in predetermined locations in said memory.
  • Figure 1 shows a simplified block diagram of a system configuration in which the host system comprises a format controller and the peripheral device comprises a print controller and shared Communications RAM. '
  • FIG. 2 shows a block diagram in which the major solid state circuits employed in the printer print controller are shown in greater detail.
  • Figure 3 shows the basic block diagram of a printer in the interface between the mechanical components and the printer electronics.
  • Figure 4 shows a more detailed block diagram of the printer control electronics of Figure 3.
  • Figure 5 shows the data format of the Communica ⁇ tions RAM of Figure 1.
  • Figure 6 shows the format of the Print Status byte.
  • Figure 6a shows the Self-Test Error Kap for the
  • Figure 7 shows the format of the Print Command byte.
  • FIG. 8 shows the ASCII standard character set. DETAILED DESCRIPTION OF THE INVENTION
  • I/O input/output
  • printer system 10 shown in Figure 3 which is comprised of a microprocessor control, memory and support logic designated by box 11.
  • One preferred printer is described in detail in the publication entitled TECHNICAL MANUAL MODEL M-703 PRINTER, Copyright 1976 by Centronics Data Computer Corporation, the assignee of the present application.
  • the Model M-703 printer described in the last mentioned TECHNICAL MANUAL and shown in block diagram form in Figure 3, is a single head, 132 column, 7x8 dot matrix serial-type, bidirectional impact printer capable of printing 180 characters per second and utilizing a microprocessor 11, stepper motor 21 for moving the carriage upon which the print head 19 is mounted and stepper motor 23 for advancing the paper upon which the print head 19 prints to perform line feed formatting and form feed stepping operations .
  • Bidirectional printing coupled with the ability" to logically seek the shorter path in printing the next line of print after completing the last line of print maximizes the throughput printing rate.
  • the 180 character per second print speed is obtained for the standard 7x7 dot matrix.
  • the printer operates at a rate of 165 cps.
  • Standard 7x7 character matrix structure can be replaced by a -5x7, 7x9, 9x9, or 9x7 character matrices.
  • a 64, 96 or 128 (7x7, 9x7, 9x9, 7x9, 5x7 dot matrix) character set can be selected.
  • the printer 10 is preferably capable of printing 64 characters in accordance with the USASCII format.
  • An optional print density of either twelve characters per inch (12 CPI) or 15 CPI at 180 cps (characters per second) can be substituted in place of the standard 10 CPI .
  • the printer 10 is composed of three basic modules, i.e. the print module, the electronics module and the paper handling module.
  • the print module consists of the carriage and paper drive systems 20-21 and 22-23; and the print head 19.
  • the carriage drive system comprises a stepper motor 21 driven by the carriage drive control electronics 20.
  • Carriage stepper motor 21 drives a continuous closed loop belt that transports the print head carriage assembly which supports print head 19, back and forth along the printer platen.
  • a carriage and print head (as well as said platen) which are advantageous for use in the present application is set forth in the afore ⁇ mentioned Technical Manual and is further disclosed, for example, in U.S. Patent No. 4,165,490 issued on August 28, 1979.
  • Printer control signals for operating the print module are developed, by microprocessor 11.
  • Electronic vertical format control is obtained by a stored program stored in a programmable read only memory (PROM) and related support logic 24 including the logic utilized for coupling the data and conditions to the microprocessor 11 and for coupling signals from the output of micro ⁇ processor 11 to the devices to be controlled thereby.
  • the carriage drive control circuit 20 and the paper drive control circuit 22 control the carriage stepper motor 21 and the line feed stepper motor 23, respectively.
  • the paper handling module typically comprises a rotatable platen (not shown) for positively advancing a paper web through the printer.
  • the aforementioned TECHNICAL MANUAL discloses a pin feed assembly per Figure 1-7, page 1-8.
  • the microprocessor 11 of printer 10 controls printer operations through a programmable read only memory (PROM) forming part of the block 11.
  • PROM programmable read only memory
  • Micro ⁇ processor 11 which may, for example, be an INTEL Model M-8085, is controlled to receive parallel data at input 12 and also monitors the status of switches provided at control panel 13.
  • Microprocessor 11 also controls movement of the print head carriage (not shown) support ⁇ ing print head 19 by operation of stepper motor 21 and movement of the paper by operation of the stepper motor 23..
  • Microprocessor 11 monitors signals from the limit switches 14 and 15, the video system 17 and the paper empty switch 16 to effect proper execution of the motion commands.
  • the microprocessor 11 maintains an up-to-date record of the position of the print head 19 at all times and performs other "housekeeping" functions.
  • printer functions can be grouped into one of three categories, namely character printing, paper motion and auxiliary functions such as automatic motor control, audio alarm, etc.
  • characters are printed by selectively activating eight print wires aligned in a vertical column within print head 19.
  • a ninth wire is provided for underlining.
  • the appropriate print wires are momentarily activated, driving them against the conven ⁇ tional ribbon, paper and platen (not shown) to form the specified dot pattern. Printing takes place "on the fly", i.e. while print head 19 is moving along the paper document.
  • the print commands to the print wires of print head 19 are developed by character generators comprised of programmable read-only memory (PROM'S) or read-only memories (ROM'S) of suitable compatibility.
  • PROM'S programmable read-only memory
  • ROM'S read-only memories
  • character generator 34 which will be described in connection with Figure 4.
  • the microprocessor 11 addresses the PROM memory location storing each dot column within the dot matrix character.
  • the movably mounted carriage assembly (not shown) supporting print head 19 is moved by the afore ⁇ mentioned rotating belt (not shown) which is driven by carriage stepper motor 21.
  • Said carriage assembly . is driven in the forward direction or in the reverse direction by carriage stepper motor 21 which rotates the aforesaid belt in the appropriate direction.
  • the movement of the carriage assembly and print head 19 is detected by the video system and timing fence assembly 17 comprised of a timing fence incorporated in circuit assembly 17.
  • the timing fence has a pair of arrays of registration slits (not shown) which arrays are staggered relative to one another.
  • Cooperating light sources and light sensitive elements make up the video system and sense the passage of light through the arrays having slits which are shifted 90° (i.e. staggered) relative to one another.
  • the light sensing elements sense the presence of the transparent and opaque areas of the arrays of the fence which are transformed into electrical signals by the optical pick-up systems each consisting of an optical block that houses one light emitting diode and one phototransistor cooperating with each array.
  • the apparatus for performing this technique is disclosed in U.S. Patent No. 3,970,183 issued July 20, 1976 and assigned to the assignee of the present application.
  • the direction of motion of print head 19 is determined by the phase relationship and order of occurrence of the video signals produced by the two optical blocks.
  • the pulses developed by at least one of the optical blocks are utilized to establish the timing within microprocessor 11 for enabling the print wire • solenoids which are selected to print the particular dot column pattern, the particular dot column pattern being determined by the character code and the timing pulses.
  • the character code and the aforementioned timing pulses comprise two groups of control data applied to the printer character generator (34 - see Figure 4) which is preferably a prograirimable read-only memory (PROM) having
  • the paper web (not shown) can be moved either manually by manipulating a manually operable platen (not shown) or tractor assemblies, or automatically by control of stepper motor 23.
  • the paper stepper motor 23 moves the paper web through the desired distance which may, for example, be for purposes of performing a line feed, for printing superscripts or subscripts, or for slewing to provide a form feed or top of form operation.
  • Auxiliary functions of the printer 10 include the ' capability of deenergizing the carriage assembly and paper stepper motors 21 and 23 when no data is received and automatically turning these motors back on whenever a print or paper motion command is detected.
  • the microprocessor 11 of printer 10 preferably includes a stored sub-program to perform a self-test routine for automatically printing the entire character set of characters stored in the character generator(s) .
  • An audible alarm 18 is energized by microprocessor 11 to alert an operator of the presence of a special condition such as paper empty condition or other jam conditions.
  • FIG. 4 shows a more detailed block diagram of the electronics for printer 10, incorporating program memory PROM 25 which stores the operating program for printer 10.
  • Microprocessor 11 defines all printer - operations and calls out preprogrammed instructions from the program memory PROM 25 which provides microprocessor 11 with its power and flexibility. As microprocessor 11 executes the steps of the program, it selectively receives data from the various input ports and stores data in memory or reads data out of memory and sends it to the various output ports. Microprocessor 11 also performs other operations on the data between input and output instructions and makes logical decisions concern ⁇ ing the data or the advancement to a different portion of the program.
  • Microprocessor 11 steps through the main program which controls microprocessor 11 to periodically scan the control panel switches of control panel 13, perform output commands for operating the mechanical portions of printer 10; and provide observable indica ⁇ tions on control panel 13 as well as taking care of certain "housekeeping" functions.
  • - microprocessor 11 shifts from the main program to a subroutine which functions to receive the inputted action control character, decode it and perform the operation identified by the control character.
  • Microprocessor 11 thereafter returns to the same location in the main program at which it was interrupted in order to resume normal processing.
  • the program controlling microprocessor 11 is comprised of a series of coded instructions that provide the microprocessor 11 with its decision- making capability. Microprocessor 11 initiates the printing operation when the input data memory 48 contains valid printable characters. Microprocessor 11 then examines the head position counter.
  • the split timing fence and dual video channels which are described in detail in U.S. Patent No. 3,970,183 issued on July 20, 1976 assigned to the assignee of the present application, enables microprocessor 11 to determine the direction of movement and the position of the print head 19.
  • the registration slits of the staggered timing fence arrays cooperate with first and second optical sensing means to generate signals amplified by video amplifier 36. These signals are interpreted by logic circuits to determine the direction of movement of print head 19 and also to maintain an accurate up-to-date count representing the position of print head 19 relative to the platen at any given moment.
  • the character code of the character or symbol to be printed is extracted from the random access memory 48 and applied to one set of inputs of character generator 34 which, as was previously mentioned, is preferably a programmable read-only memory containing a predetermined group of bytes collectively forming the dot matrix pattern of the character to be printed, each byte representing one dot column pattern.
  • the character code - determines which group of bytes is accessed from the character generator 34 and the video signals are applied to a second set of inputs of the character generator 34 to determine which byte of the group of bytes is extracted from character generator 34 at any given instant. Printing of the selected dot column pattern occurs only when the print wires of print head 19 are in alignment vith a registration slit to assure the neat, uniformly spaced printing of dot column patterns upon the paper.
  • Microprocessor 11 responsive to said stored program, initially moves the print head 19 to the proper starting position before applying the character code to the character generator 34 to access the correct dot matrix pattern for that character.
  • the solenoid drive signals developed at the output of character generator 34 are coupled to solenoid driver circuits 76 through output latch circuit 75.
  • the data bits supplied to output latch circuit 75 are coupled through the output latch 75 to the solenoid driver circuit 76 by means of an enabling signal ENB0P2 derived from command decoder circuit 30 and applied to enabling input 75a by command decoder circuit 30, under control of microprocessor 11.
  • the solenoid driver circuits 76 amplify the drive signals to a level sufficient to drive the solenoids in print head 19.
  • Print head 19 is preferably of the type described, for example, in the above-mentioned U.S. Patent No. 4,165,490 issued August 28, 1977.
  • the solenoids (not shown) activate their associated print wires when energized to selectively form a predetermined pattern of vertically aligned dots on the paper, by impacting an inked ribbon against the paper to transfer ink in the form of a pattern of dots to the paper.
  • the printer 10 Before the printer 10 accepts input data, it is first initialized in accordance with a sub-routine forming part of the program stored in PROM 25. During initialization, the printer 10 develops a busy signal to prevent the printer from being accessed at that time.
  • the printer 10 is ready to receive data and microprocessor 11 resets busy line 50d to remove a busy condition and further transmits an Acknowledge pulse over Acknowledge line 50c enabling the system interfaced with the printer such as, for example, a large or small scale computer, communications link or the like, to transfer data to printer 10 in the form of control codes and/or character codes.
  • the data transfer to printer 10 includes the placing of an appropriate code on the data lines 43 and the application of a data strobe pulse to line 50a which is used to clock data received from the system interfaced with the printer 10 into memory 48.
  • the data word is loaded into the input memory RAM 48 and simultaneously therewith is also fed to the input data PROM 46 which examines each
  • _0' ' code word to look for the presence special function codes.
  • the codes are employed as addresses to memory locations in PROM 46. The appropriate printer action for every function code is thus determined by PROM 46 which evaluates the input code; determines if it is a printable character, acknowledges its receipt and causes the character counter, which forms part of input parallel control circuit 50, to be incremented.
  • the character counter output represents the address in memory 48 where a character code is written. If the input code is a non-active control code, it is acknowledged by developing an acknowledge signal in output 50c although the character counter is not incremented. If the code is an action control code, it is not acknowledged, does not increment the character counter, and is acted upon by microprocessor 11 which develops the acknowledge signal after completion of the requested activity.
  • Input codes causing an interrupt to the microprocessor 11 which in turn acts upon said code and generates an Acknowledge signal include, but are not limited to, Line Feed, Vertical Tab, Form Feed, Carriage Return, and Select and Delete codes.
  • Microprocessor 11 is preferably an eight bit parallel central processor unit which transfers data and internal s.tate information over an eight bit bidirectional data bus 40. Memory and device addresses are transmitted over a separate 16 bit address bus 54. Instructions for operating microprocessor 11 are located in memory 25 and are fetched and executed in a sequential fashion.
  • Timing is developed from a high frequency clock generator 26 which generates a two-phase clock signal output.
  • Address bus 54 contains the binary address of the device currently being accessed.
  • Buffer 32, input data RAM 48 , memory 32 , PROMS 35 and 34 and Transceiver 56 are also connected directly to data bus 40 for bidirectional transfer of data between microprocessor 11 and circuits 28, 30, 32, 25 and 34.
  • Transceiver 56 connects data bus 40 to the bidirectional buffered data bus 61 which is connected to all of the input/output ports and latches 62, 64, 71, 75 and 77, as well as transceiver 58 and bus driver 60.
  • each external condition is interrogated by enabling an input port of up to eight lines through a transceiver, such as, for example, the transceiver 58.
  • Conditions transferred to input ports are comprised of switch closures and optical interrupt module signals.
  • microprocessor 11 in order to read the control panel pushbuttons, microprocessor 11 generates an address which is decoded by- address decoder 28 to develop a select signal which activates the transceiver 58 to enable transfer of the switch conditions of the front panel pushbuttons (not shown) of control panel 13 to microprocessor 11 through data bus 40.
  • the microprocessor 11 accepts binary levels representing the switch conditions at its input port, which is coupled to bus 40, for evaluation and appropriate action.
  • Microprocessor 11 establishes external conditions at its output port by placing such data on its data bus 40; and supplies a clock signal to latch such data presented to the output port which data is typically comprised of front panel indication signals, solenoid drive signals and motor control signals. For example, to activate motor 21, microprocessor 11 sets a data word on its data bus 40 through its output port and causes an enable signal to be developed by address decoder 28 to strobe this data word into a quad latch 64 upon the occurrence of the output signal OUTLAT from decoder 28. The output of latch 64 provides control signals for operating stepper motor 21 in a manner to be
  • the aforesaid enable signal is created by decoding address bus information from bus 54 by decoder 28 to generate the select signal SELP12, which signal, together with WRITE signal f om microprocessor 11 , enables command decoder 30 to develop the signal OUTLAT.
  • the microprocessor 11 proceeds into what is commonly referred to as the main loop of the program stored in PROM 25.
  • the program periodically branches off to one of its sub ⁇ routines, each of which perform specific operations.
  • Major subroutines are the print routine, video interrupt routine, carriage drive interrupt routine, paper drive interrupt routine, control character interrupt routine and Self-Test routine.
  • Input data RAM 48 receives input data over the buffered data bus 49.
  • Address lines 50b from the address counter incorporated in control circuit 50 control the location in memory at which time each code word is inserted, in accordance with the count of the counter in control circuit 50.
  • Microprocessor 11 writes data into memory (RAM) 32 by setting up an address on bus 54, enabling the select line SELP08 through address decoder 28, placing the data to be loaded into memory onto the data bus 40 and thereafter activating WRITE line 11a of micro ⁇ processor 11 which is coupled to WRITE line 32a of memory 32.
  • Data is read from the RAM 32 by setting up the address lines, enabling RAM 32 and enabling its READ line lib which is coupled to the READ line 32b of memory 32.
  • RAM 32 stores data representing vertical format (VFU) data and also serves as a scratch pad memory.
  • VFU vertical format
  • Microprocessor 11 accesses the program memory PROM 25 by setting up the appropriate address lines at 54 and enabling the select line 25a derived from address decoder 28.
  • I-I Microprocessor 11 accesses the character generator PROM 34 which contains the dot patterns of the character set by setting up an address on address lines 54 and enabling select line 34a through address decoder 28.
  • Head position circuit 38 contains the elec ⁇ tronics which provides microprocessor 11 with the absolute head position of print head 19 at all times .
  • the video outputs 36a and 36b from video amplifier 36 which are out of phase with one another, are examined to determine the direction of movement of print head 19.
  • One of the outputs 36a and 36 is also used to control the firing of the solenoids in print head 19.
  • the print head position counter means incorporated in head position circuit 38 counts up when print head 19 moves in the forward (left-to-right) direction and counts down when print head 19 moves in the reverse (right-to-left) direction.
  • the ready to print (RTP) switch is coupled to microprocessor 11 through control panel 13, transceivers 58 and 56 and data bus 40, and provides an indication to microprocessor 11 that print head 19 is at the left-hand margin and the head position counting means forming part of circuit 38 is cleared to a zero count.
  • the head position information and the output of the counter incorporated in circuit 50, which count repre ⁇ sents the address for the last character loaded into the input data RAM 48, is utilized by microprocessor 11 to determine the shorter path to the next character position at which printing is to occur.
  • the ready to print (RTP) signal is generated by a light emitting diode (LED) cooperating with a photo- transistor (see Fig. 1-6, page 1-7 of the aforesaid TECHNICAL MANUAL) which detects the presence of print head 19 at the left-hand margin of the printer when an arm mounted on the carriage assembly extends into the gap between the LED and phototransistor device thereby generating an RTP (ready to print) signal.
  • the end of print (EOP) signal is generated in substantially the identical manner when the print head 19 is at the right-hand margin.
  • the carriage assembly upon which print head 19 is mounted is coupled to the carriage stepper motor 21 by means of a rotating timing belt.
  • Micro- processor 11 addresses output latch 64 through command decoder 30 to apply the enable signal OUTLAT at input 64a and further develops a data word which is applied through data bus 40 to output latch 64 to develop the proper signals for driving the coil driver circuits 68 and 70 for driving windings LI and L2 of the carriage stepper motor 21.
  • Stepper motor 21 in one preferred embodiment, is capable of advancing in 0.9° steps per stepping pulse for a total of 400 steps per revolution of stepper motor 21.
  • Stepper motor 21 is capable of being stepped in either the forward or 'reverse direction by application of current of the proper direction to coil drive circuits 68 and 70.
  • Stepper motor 21 may also be operated at a slew rate which is controlled by a slew enabling signal (CRMTSL) which enables a multi-vibrator (not shown) to generate output pulses at a high rate to slew the carriage assembly supporting print head 219 to move print head 19 at a rate faster than the normal print rate in either the forward or the reverse direction.
  • CRMTSL slew enabling signal
  • the paper stepper motor 23 is substantially identical to the carriage stepper motor 21 and functions in substantially the same manner to move the paper through increments of the order of 0.00833 inches per 0.9° incremental rotation of paper stepper motor 23.
  • the paper may be advanced to perform a line feed, form feed, top of form or any other paper movement, in either the forward or reverse direction, depending upon the desired format.
  • the paper out condition is detected by a paper out switch (see Figure 1-6, page 1-7 of the TECHNICAL MANUAL) which is located in the path of movement of the paper as it proceeds toward the printer platen.
  • the paper out switch is held open when the printer 10 is loaded with paper. When the end of the web passes the paper out switch, the paper out switch closes.
  • This switch closure condition is detected by micro ⁇ processor 11 to deselect the printer 10, generate a speaker signal by activating speaker 78 and light an alert lamp (not shown) forming part of control panel 13.
  • An override signal from an external source which causes microprocessor 11 to override the paper-out condition, allows the last form of the paper web to be printed.
  • Figure 1 shows a simplified block diagram of a ' printer 10' embodying the basic components of the printer shown in Figures 3 and 4 and which is ' coupled to a print controller 104 designed to control the printing mechanism shown in simplified form as block 102.
  • the host system 101 is comprised of a format controller 106 including keyboard and display unit 108.
  • the printer mechanism 102 is controlled by the print controller 104 in a matter defined by the formatted data supplied to it by format controller 104.
  • the format controller 104 generates all of the format control data. Communication between format controller 106 and print controller 104 is accomplished through a shared communications random access memory (C-RAM) 110.
  • the data format is transferred from format controller 106 to predetermined locations in Communications RAM 110.
  • the format controller 106 transmits a signal to print con- troller 104, which is enabled to assume access of C-RAM 110 and operate on the data in C-RAM 110 as will be described hereinbelow, to operate the printing mechanism 102 whereupon access to the C-RAM 110 is then returned to format controller 106 after the print instructions are completed.
  • the keyboard and display device 108 provides manual control over format controller 106 for formatting purposes.
  • Signals from format controller 106 to the Communications RAM 110 are transferred through data and address bus 109, which also transfers data and address information between C-RAM 110 and print controller 104.
  • data and address bus 109 which also transfers data and address information between C-RAM 110 and print controller 104.
  • C-RAM 110 is selectively accessed by format controller 106 and print controller 104 in accordance with a handshake routine employing the handshake signals "HOLD IT" and "GOT IT" and their complements.
  • the "GOT IT" signal from printer 10' goes high whereupon format controller 106 in host system 101 must wait for print controller 104 to initialize printer 10' and C-RAM 110.
  • the signal "GOT IT" remains high for the duration of the initialization procedure and thereafter goes low relinquishing access of the C-RAM 110 to the format controller 106.
  • C-RAM 110 is coupled to format controller 106 and print controller 104 by data and address bus 109.
  • Bus 109 contains address lines to address the location in C-RAM in which data is to be written or the location from which data is to be read out of C-RAM 110.
  • the data lines of bus 109 carries data between C-RAM 110 and either print controller 104 or format controller 106.
  • a select line 114 (see Fig. 2) from the format controller 106 selects C-RAM 110 to enable data transfer to occur.
  • the Select signal is high when true and is only relevant when the format controller 106 has access to C-RAM 110, which condition occurs only when the "HOLD IT" signal from format controller 106 is high and the "GOT IT" signal derived from microprocessor 11' is low, said signals appearing at lines 115 and 116, respectively as shown in Figure 2.
  • the "HOLD IT" handshake signal originates in format controller 106 indicating that format con ⁇ troller 106 has exclusive read-write control of C-RAM 110.
  • Print controller 104 is prohibited from gaining access to C-RAM 110 at this time.
  • Format controller 106 relinquishes control of C-RAM 110 by developing a low "HOLD IT" signal which, in addition to relinquishing control of C-RAM 110, also serves as a request to print controller 104 to act on the data transferred to C-RAM 110 by format controller 106.
  • the "GOT IT" handshake signal originates in the microprocessor 11 ' of print controller 104 and when high indicates that print controller 104 has exclusive read/write control of C-RAM 110 and that appropriate action is presently in progress. Format controller 106 is prohibited from gaining access to C-RAM 110 at this time. Print controller 104 relinquishes control of the C-RAM by developing a low "GOT IT" signal which further indicates that action undertaken by print controller 104 is completed or if incomplete, that action can no longer proceed due to a halt condition, which status information is conveyed to the format controller 106 through C-RAM 110.
  • Action by the printer mechanism 102 is dictated by the parameters previously written into C-RAM 110 by format controller 106 and the signalling of the print
  • the address format of C-RAM 110 is divided into two basic sections, the first section comprising the Control Block and occupying memory locations
  • the second section constitutes the Data Block which occupies locations 10 _ through
  • C-RAM 110 storing the first 16 bytes, each byte being comprised of eight binary bits .
  • Figure 5 shows the address format of C-RAM 110.
  • the Control Block is comprised of sixteen bytes, said bytes occupying memory storage locations 00 through
  • the arguments are comprised of either a single byte or a pair of associated bytes which occupy locations
  • Arguments for five events are defined, four setting forth the amount of paper motion requested and a fifth argument being utilized for print action. These five events are read out of memory and performed, in a predetermined sequence.
  • the printer status is updated by print controller 104 after it completes " all requested events and before it relinquishes control of C-RAM 110 to format controller 106.
  • access to the Data Block is returned to the format controller 106 prior to having been reset, i.e. full of space codes.
  • the Data Block is neither interro ⁇ gated nor is its contents changed.
  • the four paper motion arguments are each comprised of the bytes stored in address location "05 through 08 _ and 0A through 0D , each argument consisting of two bytes.
  • the printer status byte at address location 00 R within the Control Block is updated by print controller 104 after each print action and prior to the print controller 104 returning control of the
  • C-RAM 110 to the format controller 106 and stores data representing printer status as defined in greater detail hereinbelow.
  • the transfer of control from format controller 106 to print controller 104 with all events being zero causes an update of the printer status byte.
  • the Self-Test byte at location represents the status of the printer 10' based upon the Self-Test requested by the format controller 106.
  • Figure 6 shows the format of the Print Status .byte stored in memory location 00 within the Control Block of C-RAM 110.
  • Bit 7 of the Print Status byte When Bit 7 of the Print Status byte is set, this indicates that one of the five events was aborted because of either a fault condition or a paper out condition.
  • bit 7 of the Print Status byte When bit 7 of the Print Status byte is set showing an abort of one of the events, one of the bits 2-6 are set to indicate which event was in progress when the abort occurred.
  • the aforesaid events are polled in a predetermined order by print controller 104 at the time that they are being performed, with the Event No. 1 performed first and Event No. 5 performed last. The aborting of an event prior to the last event will flag that event only by setting its appropriate bit, although subsequent events, if any, will not have been processed.
  • Bit 1 is set to indicate that a fault condition has been recognized by the print controller 104 or that a requested Self-Test has failed.
  • Bit 0 is set to indicate a paper-out condition. The recognition of a fault or paper-out condition by print controller 104 causes an abort of the event in progress unless the "override" bit in the "print command" word has been set, as will be more fully described.
  • the number of accumulated paper motion steps is comprised of a two byte 16 bit number stored in address locations 01, 16 c and 02.1,6_ within the Control Block of C-RAM 110. This two byte number represents the count of the number of steps that the paper has moved since the last time the count was reset to zero. The count is zeroed upon initialization of the printer 10'. Each forward paper motion step is added to the number and each reverse paper motion step is subtracted therefrom. The format controller 106 can zero the count of paper motion steps at each logical top of form if it is desired to accumulate the total steps performed. Each increment paper motion step is equal to 0.00833 inches, there being
  • a pair of bytes which are stored in address locations 031.6_ and 04.1,6_ in the Control Block of C-RAM 110 contain the number of paper motion steps remaining after an abort condition. In the event that the print con ⁇ troller 104 is forced to abort a paper motion event, the number of paper motion steps that have yet to be completed during that event are stored in these address locations by print controller 104. Address locations and 06,16_ store the bytes which contain the count for Event Number 1 which is the number of reverse paper motion steps to be performed by the printer before printing.
  • the two bytes in stored address locations 07 and 08.16_ contain the count for Event Number 2 which is comprised of a count representing the total number of forward paper motion steps before printing.
  • the bytes in address locations OA 1,6_ and 0B.16,_ store the count for Event Number 4 which represents the total amount of reverse paper motion to be performed by the printer 10' after printing.
  • Address locations OC. 16- and OD,16_ store the bytes containing the count representative of Event Number 5 which is the total number of forward paper motion steps to be performed after printing.
  • Event Number 3 which constitutes the print command byte.
  • the format of the print command byte is shown in Figure 7.
  • the print command indicates to the print controller 104 the action other than paper motion which may be requested by format controller 106.
  • Bit 7, the Prime bit causes the print head 19 to be moved to the left-hand margin when set.
  • Bit 6, -the print underline bit causes the data in the data block of C-RAM 110 to be printed with an underline when bit 6 is set.
  • bit 5 When bit 5 is set, the data in the data block of C-RAM 110 is printed in elongated (double-width) character format.
  • bit 4 When bit 4 is set this indicates that the data is to be printed and this bit must be set to initiate any printing action. Bits in the print command word are processed starting with bit 7. For example, if bit 7 is set, the print head 19 would first move to the left before printing.
  • Bit 3 is set when it is desired that the requested events be processed regardless of a paper out condition (i.e. "override").
  • Bit 1 is set when it is desired to print in the graphics mode.
  • the print head 19 will print a dot pattern contained in the eighth column of the character generator whereby no space will be provided between characters enabling the printer to print a " ot in every column.
  • the patterns stored in memory need not be a character but may be any pattern occupying an 8x8 matrix which, together with adjacent patterns , forms a composite graphic pattern.
  • the print head 19 When Bit 1 is reset, the print head 19 will ignore the dot pattern stored in the eighth column of the character generator, thereby printing 8x7 dot matrix patterns wherein a space the width of one dot column is provided between adjacent 8x7 dot matrix patterns as is the case when printing normal characters.
  • Bit 0 is set to cause the print controller to perform a Self-Test which includes a check of the C-RAM 110 and the moving of print head 19 from the left-hand margin to the right-hand margin and back to the left in order to verify the video count. Results of the Self-Test are placed in the status word described hereinabove with respect to Figure 6.
  • the Data Block of C-RAM 110 (see Fig. 5) comprises the print buffer.
  • the Control Block defines the method of printing the data within the print buffer.
  • Each of the bytes stored in the Data Block are comprised of 8 bits . providing up to 256 different codes all of which can be printable with the exception of two bytes which are defined as space codes.
  • the buffer (Data Block) portion of the C-RAM 110 is examined for printable codes.
  • the print controller 104 employs a logic seeking routine for selecting the shorter head movement between print lines. As each printable code is removed for printing by the print control a space code is loaded into that address location. When all Data Block memory locations in C-RAM 110 contain space codes, the buffer is then in a reset condition in readiness for a subsequent data transfer at the end of the print line.
  • the print controller 104 interrogates all 132 bytes in the Data Block for printable codes.
  • the expanded character bit is set, only the first 66 characters in the buffer are interrogated for printable codes and characters r. O PI outside of these 66 will be overlayed with space codes.
  • the print controller 104 further includes a character generator 126 (Fig. 2) which is preferably of the read only memory (ROM) or programmable read only memory (PROM) type and which contains dot patterns for printing 128 characters.
  • a character generator 126 Fig. 2 which is preferably of the read only memory (ROM) or programmable read only memory (PROM) type and which contains dot patterns for printing 128 characters.
  • the definition for an ASCII character set is shown, for example, in Figure 8.
  • the dot matrix pattern of a character is contained in eight consecutive locations in (ROM) or (PROM) starting with code 00 stored in address locations 00 _ through 08 , code stored in address locations 09 1 lb (r through 015.l c b , and so forth.
  • the eight consecutive ROM locations each contain a byte having the pin firing information for one dot column of a 'character. In the case of standard ASCII , the eighth byte of information is always 0 (i.e.
  • the character is blank () because the matrix is defined as a 7x8 matrix, although it is possible to add an eighth column of information to provide added flexibility to character formation.
  • the character is a nine part character with the first blank taken from ROM 126 storing the standard set and the ninth blank added by micro ⁇ processor 11.
  • microprocessor 11* (see Fig. 2). initializes the printer 10. As part of the initialization sub-routine of the main program, micro ⁇ processor 11* develops a high "GOT IT" signal at line 117 which is applied to one input of bus arbitration logic 130 which may be comprised of an INTEL Type 8155/8156 integrated circuit or a Type 8755 integrated circuit. Bus arbitration logic 130 develops a high "GOT IT" signal at its output 130c responsive to the high "GOT IT" " signal on line 117, prohibiting format controller 106 from gaining access to C-RAM 110.
  • the format controller 106 preferably includes computer means such as a micro ⁇ processor, which may, for example, be an INTEL Type 8085
  • microprocessor which is programmed to prevent the format controller from gaining access to the C-RAM 110 as long as a high level "GOT IT" signal is present.
  • the high "GOT IT" signal on line 116 is also applied to direction control input 122a of bidirectional bus drive circuit 122 to prevent data from being transferred from format controller 106 through bidirectional bus drive circuit 122 to C-RAM 110.
  • the high "GOT IT" signal is also applied to control input 120a of unidirectional bus driver 120 to prevennt format controller 106 from addressing C-RAM 110. .
  • the "GOT IT" signal goes low.
  • the low “GOT IT” signal is applied to format control 106 through bus arbitration logic circuit 130.
  • the format controller 106 generates a high "HOLD IT" signal at line 115 and a SELECT signal at line 114 which causes the bus arbitra ⁇ tion logic 130 to prevent microprocessor 11 ' from accessing C-RAM 110 and which further selects C-RAM no through line 130a.
  • the format controller 106 then transfers control data and character data to C-RAM 110 by generat ⁇ ing address information at address lines 125 and control codes and/or data codes at data bus lines 127.
  • the format controller 106 may initially transfer data to the proper locations in C-RAM 110 for the aforementioned five events. Assuming data is being transferred for Event Number 1 , the address developed on address lines 125 comprises the address of the first byte f or Event Number 1, i.e. 05, 1,6-.
  • Number 1 byte are applied to data bus 127.
  • the format controller 106 exerts exclusive control over C-RAM 110 and may introduce data into C-RAM 110 at any desired operating speed and may also introduce the data into C-RAM 110 in any order. However, the data must be transferred to the proper locations in C-RAM 110 in order to assure that the data will be interpreted correctly.
  • a WRITE signal is applied to line 123 by format controller 106, causing the output lines 122b of bidirectional bus drive circuit 122 to apply the next data word from format controller 106 to the data lines 110a of C-RAM 110 through bidirectional bus 40' .
  • the address in C-RAM 110 into which the code word is written is applied to C-RAM 110 through the output lines 120b of unidirectional bus driver circuit 120 to the address input lines 110b of C-RAM 110.
  • the second byte of Event Number 1, ' to be stored in address location 06.16_ is then loaded into the last mentioned address location by placing the appropriate address on lines 125 and by placing the data bits of the second byte on data bus lines 127 whereupon the unidirectional bus driver circuit 120 and the bidirectional bus drive circuit 122 are enabled to write the second byte of the first event into address location 06. fi .
  • the remaining events are written into C-RAM 110 in a similar manner.
  • the code words representative of the characters to be printed are loaded into C-RAM 110 in a similar fashion.
  • the format controller 106 generates a low "HOLD IT" level on line 115 to relinquish control over C-RAM 110.
  • the low "HOLD IT” signal deselects C-RAM 110 and provides a signal to microprocessor 11' through line 129 which acts as a request to microprocessor 11' to access C-RAM 110 and thereby carry out the events in accordance with the data just entered into C-RAM 110.
  • the data to be written into C-RAM 110 may be written in any desired order.
  • Microprocessor 11' under control of the firmware read only memory (ROM) 124, develops a high "GOT IT" signal at line 117, a high SELECT signal at line 121 and a READ signal at line 119 which causes bus arbitra ⁇ tion logic 130 to provide a SELECT signal at line 130a and a READ signal at line 130b through C-RAM 110 and further causes a high "GOT IT" signal to be developed at line 130c to prevent the format controller 106 from gaining access to C-RAM 110 * during the time that microprocessor 11' is interrogating C-RAM 110.
  • the high "GOT IT” signal also provides a disable signal to the inputs 120a and 122a of circuits 120 and 122 , respec ⁇ tively.
  • Microprocessor 11 places an address on address bus 54 (note also Fig. 4) causing the byte in the address location placed on address bus 54 to be transferred to data * bus 40. Presuming the byte which is read out to be the first byte for Event Number 1, this byte and the subsequent byte making up Event Number 1 are read out in similar fashion and are transferred through data bus 40 into the scratch pad RAM 128 which serves as the means for temporarily storing the bytes for the desired Event as the requested activity for such event is being carried out. For example, Event Number 1 calls for reverse paper motion of the paper prior to printing and sets forth the number of paper motion steps to be performed. Microprocessor 11' activates the paper motion stepper motor 23 (see Fig.
  • microprocessor 11' places the address code 09. R upon address lines 54 to address the input lines 110b of C-RAM 110 causing the Print Command byte stored in this location to be transferred to data bus 40 and into an appropriate register within microprocessor 11 ' .
  • microprocessor 11' sequentially examines the status of each bit within the print command byte in a predetermined sequence to ascertain its binary state and thereby ascertain what operation is called for. For example, when printing data in the normal fashion, bit numbers 7, 6 and 5, which are sequentially examined, should all be in a reset state. Thereafter, the next bit to be examined, i.e. bit 4 (see Fig.
  • microprocessor 11' enters into a print subroutine wherein each code word within the Data Block of C-RAM 110 is sequentially extracted from memory, to be utilized as an address by microprocessor 11' whereby the signals of address lines 54 coupled to the address inputs 126a of character generator 126 sequentially select the bytes representing the dot column patterns of the 7x8 character matrix to be successively read out of character generator 126 and transferred through data bus 40 to microprocessor 11' which, in turn, successively couples each dot pattern byte to the output latches 75 ( Figure 4) and thereafter to the solenoid driver circuits 76 for printing each vertical dot column pattern as the print head 19 moves across the paper document.
  • the registration pulses developed by the timing fence and associated light sources and light detectors are applied to microprocessor 11' to indicate: the direction of movement of print head 19; and the position of print head 19 in order to allow microprocessor 11' to select the proper dot pattern byte for printing. As the printing of each dot matrix character is completed,- the next character code in C-RAM 110 is read out and is
  • PI utilized to access character generator 126 for success ⁇ ively reading out the eight dot pattern bytes comprising the next 7x8 matrix character to be printed at outputs 126b of character generator 126 which are again employed in a manner similar to that described hereinabove for selectively firing the print wires of the print head 19.
  • either of these condi- tions cause the microprocessor 11 ' to enter into an associated subroutine which accesses the byte in C-RAM 110 which contains the printer status byte (i.e. byte 00. ) to set the event aborted bit number 7 the appropri ⁇ ate one of bits 2-6 indicating which event was being performed during the. abort condition.
  • bit 0 of the print status byte will also be set.
  • the bytes in C-RAM 110 representing the uncompleted paper motion steps i.e. the bytes in byte location 03 and 04 are updated by microprocessor 11' on a periodic basis.
  • the bytes representing the accumu ⁇ lated paper motion steps which are stored in locations 01. fi and 02 are also updated to reflect the cumulative count since the last time that these bytes were reset.
  • microprocessor 11 ' sets bit 1 of the print status byte to indicate a failure in the Self-Test operation.
  • the Self-Test results are contained in the Self-Test byte which is stored in address location 0E .
  • the Self-Test byte Error Map is shown in Figure 6a and is updated pending the results of the Self-Test routine.
  • microprocessor 11* relinquishes control over the C-RAM 110 by developing a low "GOT IT" signal at line 117 to relinquish control over C-RAM 110 to allow format controller 106 to gain access to C-RAM 110.
  • the format controller 106 which, as was previously mentioned, preferably incorporates a micro ⁇ processor, enters into a subroutine stored in its associated memory during which the format controller 106 initially examines the status bytes by addressing the appropriate memory locations within the Control Block of C-RAM 110 by applying the appropriate address to unidirectional bus drive circuit 120 and to inputs 110b of C-RAM 110 which transfers the byte stored in the accessed memory location to bus 40' and through bi ⁇ directional bus drive circuit 122 to the format con ⁇ troller for purposes of evaluation and to enable format controller 106 to take appropriate action. In the event that no aborted conditions have occurred, the format controller 106 continues in the normal fashion trans ⁇ ferring data representing one or more of the five possible events that are to be performed into C-RAM 110.
  • the apparatus of the present invention provides a wide variety of different formats due to the employment of a shared random access memory as has been described hereinabove.

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Abstract

Dispositif de mise en forme des donnees destinees a etre imprimees par une imprimante (102) a impact bidirectionnel caractere par caractere du type a impression par point, L'imprimante (102) utilise un microprocesseur (11) et un moteur pas a pas (21) pour l'impression bidirectionnelle et permet d'obtenir une vitesse maximum d'impression, grace a la possibilite de chercher logiquement le chemin le plus court pour l'impression de lignes successives de donnees. L'imprimante comprend un controleur d'impression (104) commande par un controleur de format (106) faisant partie d'un ordinateur, d'un reseau de communication ou d'un autre systeme de commande pour commander l'impression de la facon definie par les donnees de format fournies par le controleur de format (106). La communication d'interface et l'echange de donnee entre le controleur de format (106) et le controleur d'impression (104) est realisee au moyen d'une memoire partage e de communication (C-RAM) (110) du type a acces selectif. Les donnees sont mises en forme dans la C-RAM (110) par le controleur de format (106) pendant le temps ou il accede a la memoire de communication. Le controleur de format (106) cede ensuite l'acces a la C-RAM (110) au controleur d'impression (104) qui opere sur les donnees contenues dans la C-RAM (110) conformement au format desire, apres quoi l'acces a la C-RAM (110) est de nouveau rendu au controleur de format (106).
PCT/US1981/000065 1980-01-21 1981-01-16 Memoire a acces selectif servant d'interface aux controleurs d'impression et de format dans un systeme d'imprimante WO1981002211A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077892A2 (fr) * 1981-10-26 1983-05-04 International Business Machines Corporation Système de traitement des mots à imprimante bidirectionnelle déterminant le format
EP0182042A2 (fr) * 1984-10-24 1986-05-28 International Business Machines Corporation Sélection interactive par l'opérateur de réalisations alternatives de fonctions d'imprimante
EP0234933A2 (fr) * 1986-02-28 1987-09-02 Nec Corporation Système de commande pour sortie de données

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US3564509A (en) * 1968-04-22 1971-02-16 Burroughs Corp Data processing apparatus
US3594759A (en) * 1968-04-29 1971-07-20 Xerox Corp Graphical data processor
US3810109A (en) * 1972-07-21 1974-05-07 Ultronic Syst Storage and space availability apparatus for a data processing printout system
US3959776A (en) * 1974-02-19 1976-05-25 Modicon Corporation Programmable printer
US4179732A (en) * 1977-06-10 1979-12-18 Dataproducts Corporation Microprogrammable processor control printer system
US4203154A (en) * 1978-04-24 1980-05-13 Xerox Corporation Electronic image processing system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564509A (en) * 1968-04-22 1971-02-16 Burroughs Corp Data processing apparatus
US3594759A (en) * 1968-04-29 1971-07-20 Xerox Corp Graphical data processor
US3810109A (en) * 1972-07-21 1974-05-07 Ultronic Syst Storage and space availability apparatus for a data processing printout system
US3959776A (en) * 1974-02-19 1976-05-25 Modicon Corporation Programmable printer
US4179732A (en) * 1977-06-10 1979-12-18 Dataproducts Corporation Microprogrammable processor control printer system
US4203154A (en) * 1978-04-24 1980-05-13 Xerox Corporation Electronic image processing system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077892A2 (fr) * 1981-10-26 1983-05-04 International Business Machines Corporation Système de traitement des mots à imprimante bidirectionnelle déterminant le format
EP0077892A3 (en) * 1981-10-26 1984-05-02 International Business Machines Corporation Word processing system having a formatting bidirectional printer
EP0182042A2 (fr) * 1984-10-24 1986-05-28 International Business Machines Corporation Sélection interactive par l'opérateur de réalisations alternatives de fonctions d'imprimante
EP0182042A3 (en) * 1984-10-24 1989-10-18 International Business Machines Corporation Interactive operator selection of alternative implementations of printer functions
EP0234933A2 (fr) * 1986-02-28 1987-09-02 Nec Corporation Système de commande pour sortie de données
EP0234933A3 (en) * 1986-02-28 1988-01-20 Nec Corporation Data output control system

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