WO1980002900A1

WO1980002900A1 - Converter included in a phase modulator

Info

Publication number: WO1980002900A1
Application number: PCT/SE1979/000130
Authority: WO
Inventors: C Sundberg; T Aulin; N Rydbeck
Original assignee: Ericsson Telefon Ab L M
Priority date: 1979-06-08
Filing date: 1979-06-08
Publication date: 1980-12-24
Also published as: DE2953707A1; GB2071966B; GB2071966A; CH654155A5; JPS5635560A

Abstract

A converter is included in a modulator for phase modulation of data symbols ((Alpha)n) and converts the data symbols received each in one time interval to sequences of phase values ((Alpha)+(Alpha)n). Based on symbol correlation the present phase value sequence is calculated out of an arbitrary rational modulation index, of the present phase state ((Alpha)n) which is associated with a first number of symbols previously received and which defines a phase state number, and of a pulse response which extends over the present symbol and a second number of preceding symbols. There exists a finite number of phase value sequences which are stored in digital form in a memory arrangement (MA) and each accessible with an associated address. Any arbitrary sequence of data symbols results in continuous phase transition. A calculating unit (CU) calculates during each time interval a phase state number (vn). The memory arrangement comprises an access unit to generate the address, which is determined by the present data symbol, by the previously mentioned second number of preceding symbols and by the last phase state number received from the calculating unit.

Description

CONVERTER INCLUDED IN A PHASE MODULATOR

FIELD OF THE INVENTION

The present invention relates to a converter which is included in a modulator for phase modulation of data symbols each of which is received during a time interval and is converted by means of a memory arrangement to a sequence of phase values in order to determine how the phase of the carrier frequency generated in the modulator is continuously shifted during the time interval. At the so called symbolcorrelation comprising L symbols, the present sequence of phase values is determined by the present symbol and (L-1) previous symbols. To facilitate so called coherent demodulation, the phase should change continuously not only during each time interval but also during successive time intervals associated with an arbitrary symbol sequence.

Summing up, profound theoretical studies have shown that the signal transmission qualities of phase modulation improve if the symbolcorrelation increases and if the data symbols include M > 2 signal levels at unchanged bit rate. M = 2 and 4 and 8 defines a binary, quaternary and octal system, respectively. The theoretical basis of digital phase modulation has been published for example in Aulin, Rydbeck, Sundberg: "Further results on digital FM with coherent phase tree demodulation - Minimum distance and spectrum", Technical Report TP.-119, November 1978, Telecommunication Theory, University of Lund, Sweden which in itself contains on pages 70 - 74 a detailed relevant list of references.

DESCRIPTION OF PRIOR ART

In the reference (33) in the above mentioned Technical Report TR-119 and in the Swedish petent application No 7809358-0 a converter that achieves symbol-connelation and a procedure of so called "Tamed

Frequency Modulation" are described. The prior art converter comprises a memory arrangement to store and read in digital form sequences of values of cosinus and sinus of the phase. The memory arrangement is providew with a shift register which receives differentially encoded data symbols (M = 2) and contributes to produce symbol-correlation. Total continuity of the phase is obtained by means of a quadrant counter, further due to the fact that cosinus- and sinus-sequences stored in the memory arrangement are determined by a filtered version of a number of successive binary signals, and further by selecting a modulation index h = 0,5, resulting in exact phase shifts with the angles 0,± π/4 or ± π/2 respectively.

If M^L different phase value sequences are calculated in a known way, the phase values indicating phase changes in relation to the phase value at the end of the previous symbol time interval, total continuity of the phase would be achieved trivially and simply by means of a memory arrangement to store address and read the M^L phase change sequences, which memory arrangement comprises a register to store said end phase values and an adder to add the end phase value stored to the phase change values read successively from the memory arrangement.

The above mentioned Swedish patent application explains that such a trivial continuity solution would be accompanied by serious demodulation difficulties resulting in a too high fault probability. At the receiver side, it must be possible to reproduce the modulation carrier frequency as well as the time intervals of the symbols. Thus it is required that the phase value sequences are connected with absolute phase values 0 ≦ 0 < 2π. Then accumulating phase faults are avoided at the transmission, and unknown frequency shifts caused by disturbances between the transmitter and the receiver are easier to discriminate and eliminate at the demodulation.

At the prior art converter mentioned accumulating phase faults are easily avoided because the phase value remains in one phase quadrant during a symbol interval or changes to the neighbouring higher or lower phase quadrent. The prior art converter is arranged in this relation for storing sinus and cosinus sequences, the values at their ends referring to a border or to the center of a quadrant.

However, such a quadrant counter is completely inadequate for modulating data symbols with M > 2 in connection with a correlation extending over an arbitrary number of symbols, and also in connection with arbitrary rational modulation indexes and sequences of absolute phase values which are used for achieving high quality transmission and demodulation. With the aid of the present invention not only an arbitrarily complex digital phase modulation is achieved, but qualities of even simple system for phase modulation are improved in relation to those of prior art modulators.

At the converter according to the invention, the characteristics of which are apparent from the appended claims, the quadrant counter of prior art is substituted by a unit for calculating so called phase states, which define each one of a finite group of phase state numbers. The sequences of aboslute phase values which are stored in the memory arrangement are accessed with addresses which are determined by the symbols received and the phase state numbers. The number of addresses, i.e. the necessary capacity of the memory remains small in relation to the degree of complexity of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in detail with reference to the accompanying drawing where Figs 1 and 4 show prior art modulators for phase modulation of data symbols, Figs 5 to 8 show different forms of the invented converter and Figs 2, 3 and 9 to 12 show examples of phase trees, phase transition diagrams and phase value sequences as stored in the memory arrangement.

THEORETICAL BACKGROUND OF THE PREFERRED EMBODIMENTS

In this chapter a general description of the modulated signal is given. The optimum Maximum Likelihood Sequence Estimator (MLSE) is calculated assuming that the signal is transmitted on an additive white gaussian channel. Due to the fact that the log likelihood function can be written recursively and that the signal at the symbol transition instants can be described by a finite number of states, it is shown that the Viterbi algorithm can be used System mode l Let

be a sequence of uncorrelated M-ary data symbols (α_i = ±1, ±3,..., ±(M-1)) up to the n-th symbol time interval. Define the constant envelope CPFSK-signal as

where the information carrying phase function is

and where g(t) is a pulse of duration L symbol intervals i.e.

E is the symbol energy, f_o the carrier frequency and φ_o an arbitrary constant phase shift which without loss of generality can be set to zero in the case of coherent transmission.

A schematic modulator for such a signal (see equation (2)) is shown in figure 1, comprising a filter with impulse response g_(t) and a voltage controlled oscillator VCO.

The variable h is referred to as the modulation index, h is normalized by equation (9). For positive pulses or pulses satisfying equation (7) this means that the maximum absolute phase change is (M-1)hπ radians over one symbol interval. For all pulses considered this is exactly or approximately fulfilled. The phase change over one symbol interval is, using equation (3)

The variable substitution τ - iT → σ gives

If the pulse g(τ) is nonnegative for all t ∈ (0,LT), or if

then the maximum absolute phase change over one symbol interval is

Thus the normalizing constraint is

This constraint is satisfied if

For an arbitrary pulse g(t), a search - using (9) - for the maximum absolute phase change over one symbol interval has to be performed with respect to the variables

If pulses g(t) are used which do not have Limited duration, the maximum phase change over one symbol interval is

which is a generalization of equation (6). The pulse g(t) need not be causal. This quantity can be approximated with high accuracy by assuming that

where N_L is a sufficiently large number. This is equivalent to the truncation

We now define

Using (9) and the fact that g(t) by definition is causal and of duration LT we also have

Thus the phase function (3) can be written as

where and correspond to the first and the last sum respec

tively.

The Viterbi algorithm works recursively using a metric to choose those sequences that maximizes the log likelihood function up to the n-th symbol interval. A trellis is used to choose among possible extensions of those sequences. This trellis consists of a set of states, and a path through the trellis should uniquely correspond to a sequence of data symbols and vice versa. A trellis is always obtained for rational values of the modulation index since in this case

takes finitely many values i.e. p values. These values are referred to as the phase states.

Furthermore, for every fixed t, the function

has at most M different values. We now define the set of states in the trellis by the L-tuple

The total number of such states N_s is

It is seen that the state space consists both of the phase states and the L-1 previous data symbols. The latter are called the correlative states.

To illustrate the above discussion, we now present an example where M=2, i.e. the data symbols α_i are bipolar ±1. The pulse is chosen to be

whi ch i s a rai sed-cosi ne pu lse over th ree b it i nterva ls (L=3) , (3RC) . Finally we chose h = 1/2 (k=1). This gives directly p=4 and thus θ_n can only take the 4 values e.g. 0, π/2, π, 3 π/2. This also gives the possible states σ_n

(0,-1,-1) (π/2,-1,-1)- (π,-1,-D (3π/2,-1,-1) (0,-1,1) (π/2,-1,1) (π,-1,1) (3π/2,-1,1) (0,1,-1⁾ (π/2,1,-1) (π,1,-1) (3π/2,1,-1) (0,1,1) (π/2,1,1) (π,1,1) (3π/2,1,1)

In figure 2 the so called phase tree is plotted over five bit interval The phase tree is simply all the phase trajectories φ(t,α_n), assuming zero phase at t=0 and previous data symbols chosen as a sequence with values M-1. It is noted that the phase tree should preferably be seen modulo 2π, i.e. drawn on a cylinder.

Since at time t=0, the phase is zero and the previous data symbols are both +1, this state is denoted (0,1,1). Assuming the new data symbol up to time T still is +1, the correlative part of the state is the same, but the phase trajectory is now π/2. The phase state is thus changed to give the state (π/2,1,1). Assuming that the new data symbol is -1, the correlative part of the state is changed, whereas the phase state is changed from 0 to π/2 (π/2 - 1,1). How the states are attached to the phase tree is easily understood by looking at figure 2 when t=4T and 5T. The twelve phase values are seen to form groups around the phase states 0, π/2, π and 3π/2. The positions within the groups are given by the prehistory (correlation).

It is noted that the number of phase values at the bit transition instants are twelve whereas the number of states are sixteen. This is because four of the phase values each have two states attached to them It is also seen that there are four phase trajectories entering these phase values and also four leading from them. Thus we have a crossing. From figure 2 the trellis is easily obtained, see figure 3.

The number of states in the trellis has been shown to be N_s = p.M^L-1.

With b equal to the number of bits per channel syr.bol this means that N_s can be written as

i f

Table 1 shows numerical data calculated by using the equation above. If b·L is denoted the correlation time in bits we note that the number of states decreases with increasing b (M) for fixed correlation time b·L and fixed p. Hence the number of states for M-ary schemes is smaller than that of binary schemes for equal correlation time.

For example an octal 2RC scheme (M=8, L=2) has 32 states for p=4. The correlation time for this system is six bits. Compare a binary L=6 scheme with 128 states for the same p. However, for an octal scheme p=4 corresponds to a higher average modulation index than for a binary scheme. I e if a binary scheme with p=4 is compared to an

octal scheme with p=16 which is more appropriate, the number

of states is 128 for both schemes for a 6 bit correlation time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The normalized transmitted signal s_o(t,α_n) is

s_o(t,α_n) ^Δ cos (ω_ot+φ(t,α_n)) (23)

Dividing s_o(t,α_n) into quadrature components yields

s_o(t,α_n) = I(t).cos(ω_ot) -Q(t)·sin(ω_ot) (24)

where

From equation (3) and (15) we have

<PCt,σ ⁾ = θCt,α ) + θ -n -n n

where

θ_n represents the phase state and θ(t,α_n)/nT ≤ t < (n+1)T is the phase branch.

Figure 1 shows a simple transmitter structure. The problem with implementations based on this structure is to achieve an exact rational relationship between the modulation index h and the bit rate. An accumulated phase error occurs if the "sensitivity of the VCO" is not exactly matched to the bit rate. The transmitter in figure 4 avoids this prcblen since in this case the I(t) and Q(t) generators are clocked with a multiple of the bit rate.

The I(t) and Q(t) generators for a general M-ary system can be implemented in many ways. One straight forward solution is shown in figure 5. In this solution all possible I(t) and Q(t) shapes over 1 symbol interval T are stored in memories of a memory arrangement MA addressed by the states (α_n-1,θ_n) and the present input symbol α_n. The phase states θ are generated by a calculating unit CU consisting of a phase state ROM and a delay of length one symbol interval T. At each symbol time the data sequence g and the previous phase state θ_n-1 determines the next phase state θ_n. The phase state machine CU is preferably constructed with phase state numbers v_n instead of actual phase state values θ_n. These numbers v_n are related to the phase values θ_n by the equation θ_n = (hπv_n + ψ_o) mod(2π) (27)

where ψ_o is an arbitrary phase constant.

In the following ψ_o is chosen to zero.

The I(t) and Q(t) shapes are swept by a counter C at the rate m·1/T where m is the number of stored samples per symbol interval T.

As an example the size of the I(t) ROM is 3200 bits for M=2, 3RC (L=3), h=.5, m=10 and 10 bit quantization. In general the I(t) ROM size is given by

R_s = M·N_s·m·m_q (28)

where m_q is the number of bits per sample. The θ(t) ROM is of course of the same size.

The size of the phase state ROM is normally small compared to R_s. The size in bits

where [y] denotes the integer part of y.

The J(t) and Q(t) ROM size can be reduced by a factor p by rewriting I(t) and Q(t) as

I(t) = cos (θ(t,α_n)+θ_n) =

= cos (θ(t,α_n))·cos(θ_n) - sin(θ(t,α_n))·sin(θ_n) (30)

Q(t) = sin (θ( ,α_n)+θ_n) =

= cos (θ(t,α_n))-sin(θ_n) + sin(θ(t,α_n))·cos(θ_n) (31)

One memory arrangement implementation based on (30), (31) is given in figure 6. The penalty for the p-fold ROM-reduction is 4 multipliers and 2 small ROM's (cos(θ_n) and sin(θ_n)) of size p·m_q bits.

Another possibly better memory arrangement structure is based onstored phase values instead of stored cosines and sines. This structure is shown in figure 7. The scheme avoids multipliers and double cos-sine-ROM's but adds one cos/sine-converting ROM1 at the end. This final ROM1 must be able to "fold" input values ±(M-1)·hπ outside the normal ±π range. The phase path ROM contains all possibLe phase paths θ(t,α_n). The phase state sequential-machine CU generates the successive phase state numbers, v_n. These numbers are converted to actual phase values θ in a small converting ROM2. The phase paths θ(t,α_n) and θ_n are then added in a digital adder and converted to I(t) and Q(t) in a fairly small cos-sin-ROM1.

The total ROM size of this transmitter is sometimes smaller than that of the previous transmitters. The main reason for this is that only one phase path ROM and one phase state converting ROM is needed instead of two in the transmitter in figure 6. The saving in ROM size by this should be compared to the size of the converting output ROM1.

Several authors have considered systems where the modulation index h is changed in a cyclic way from symbol to symbol. It is easy to see that the general transmitter structures described above can be generalized by adding an "h-state-machine" as an additional address input to the phase-path and phase state memories.

The current phase branch is then determined by the data symbols α_n, the phase state θ_n and the present h-value h_n. The transitions in the phase-state-machine are, of course, also dependent on the h-value used.

Previously the h-value was chosen as a rational number where

k and p are integers. With cyclically shifted h_i the values are chosen

2 among the rational numbers . The number of states are mul

P tiplied by the number (K) of k_i-values used. For example if the two h-values and are used alternately for every other data

symbol (K=2) the number of different branches in the receiver tree is twice as high as that of the corresponding fixed h system.

In general the number of states can be written as

As soon as the receiver has syncronized the cyclic h-sequence the number of possible trellis nodes at each sampling interval will be reduced to the normal p.M^L-1, however. This is due to the fact that, with known h-value, only the normal receiver uncertainty, determined by the data sequence, has to be resolved. Thus the number of real states in the receiver trellis is the same for multi-h codes and the fixed h systems considered previously.

In a more general system where the h-values are dependent on the data sequence α_n, i e not cycliely shifted, the h-states are real states.

A schematic transmitter structure is shown in figure 8. Note that the cos, sin, ROM address inputs come from the phase-state-machine CU, the "n-state-machine" and the data symbols α_n. Note that for multi-h systems the h-values are generated by a degenerated state-machine with no data-dependence. The transmitter in figure 8 is based on the one in figure 5. The transmitters in figure 6 and 7 are, of course, just as easy to change into multi-h transmitters. It is just to add the "h-state-machine" with additional address inputs to the ROM's.

Table 2 gives an example of the phase state ROM-contents for a binary system with a pulse length L=2. The pulse is a raised cosine. The phase tree is given in figure 9. The phase numbers v_n in Table 2 are converted to phase values (θ_n) or cos(θ_n) and sin(θ_n) in the same table.

The phase branches are given in figure 10. Table 3 shows the phase state ROM-contents for a 2RC pulse with h = 2/3.

Figure 11 and Table 4 gives the same data for a 3RC system, see figure 2.

In table 4 we note that the alternative v_n can be generated by a simple state-machine consisting of an up-down counter controlled by α_{n - 1}. The phase branches in figure 11 are not the same for the alternative definition of v_n. These phase branches are given in figure 12. Note the symmetry between the branches. This symmetry can be used for ROM-savings if desired.

Claims

What we claim is:

1 Converter included in a modulator for phase modulation of data symbols each of which is received during a time interval and is converted by means of a memory arrangement (MA) to a sequence of phase values characterized by calculating means (CU) for calculating during each time interval one of a finite number of phase states, which is associated with a first number of previously received symbols and which defines a phase state number, and further by accessing means included in the memory arrangement for reading successively said phase values in digital form by means of an address which is determined by the recent symbol, by a second number of symbols previously received and by the recent phase state number obtained from the calculating means.

2 Converter according to claim 1, characterized in that the calculating means has its input connected to the memory arrangement, and calculates by means of the phase value obtained at the end of each time interval the phase state number being used by the accessing means during the subsequent time interval.

3 Converter according to claim 1, characterized in that the calculating means is constituted by a sequential machine which calculates the recent phase state number from the recent symbol, from said second number of symbols received previously and from the previous phase state number.