USRE47639E1 - Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write - Google Patents
Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write Download PDFInfo
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- USRE47639E1 USRE47639E1 US15/004,713 US201615004713A USRE47639E US RE47639 E1 USRE47639 E1 US RE47639E1 US 201615004713 A US201615004713 A US 201615004713A US RE47639 E USRE47639 E US RE47639E
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
Definitions
- Embodiments described herein relate to a semiconductor storage device.
- MRAM magnetic RAM
- DRAM dynamic random access memory
- FIG. 1 is a block diagram illustrating a memory cell array of an MRAM and its peripheral circuit according to a first embodiment.
- FIG. 2 is a diagram illustrating the components and operation of a single memory cell MC.
- FIG. 3 is a diagram illustrating the connection relationship between a read global data bus RGDB as well as a write global data bus WGDB and memory cell macros MCM 1 through MCM 4 .
- FIG. 4 is a block diagram illustrating the internal components of a comparison buffer CMPB.
- FIG. 5 is a time diagram illustrating a data write operation of the memory of the first embodiment.
- FIG. 6 is a block diagram illustrating the components of an MRAM according to a second embodiment.
- FIG. 7 is a time diagram illustrating a data write operation of the memory of the second embodiment.
- FIG. 8 is a block diagram illustrating the components of an MRAM according to a third embodiment.
- FIG. 9 is a block diagram illustrating the components of a comparison buffer CMPB according to the third embodiment.
- FIG. 10 is a block diagram illustrating the components of an MRAM according to a fourth embodiment.
- FIG. 11 is a block diagram illustrating the components of an MRAM according to a fifth embodiment.
- FIG. 12 is a block diagram illustrating the components of a comparison buffer CMPB according to the fifth embodiment.
- a semiconductor storage device that can carry out data writes continuously while reducing the wasteful power consumption during the data write operation.
- the semiconductor storage device has plural bit lines and plural word lines.
- the memory cell array has plural memory cells that can store data and are connected to the bit lines and word lines.
- Plural sense amplifiers detect the data stored in the memory cells.
- Plural write drivers write data to the memory cells.
- a comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. During a series of write sequences, the comparison buffer stores the read data from memory cells selected as the write object (the storage destination) and the write data to be written in the selected memory cells. After the series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes a write to the selected memory cells of the write data stored in the comparison buffer.
- FIG. 1 is a block diagram illustrating a magnetic random access memory (hereinafter to be referred to as MRAM) memory cell array and its peripheral circuit according to Embodiment 1.
- MRAM magnetic random access memory
- the present embodiment may also be used in the memories (such as PCRAM, ReRAM, etc.) using resistance change type elements.
- the MRAM in this embodiment has the following parts: a cell array unit CAU containing plural memory cell arrays MCA, plural main word lines MWL, plural local word lines LWL, plural read global data buses RGDB, plural write global data buses WGDB, sense amplifier S/A, read buffer RB, write driver W/D, write buffer WB, row controller RC, main row decoder MRD, column decoder CD, input/output gate circuit IOG, and read/write data line RWD.
- a cell array unit CAU containing plural memory cell arrays MCA, plural main word lines MWL, plural local word lines LWL, plural read global data buses RGDB, plural write global data buses WGDB, sense amplifier S/A, read buffer RB, write driver W/D, write buffer WB, row controller RC, main row decoder MRD, column decoder CD, input/output gate circuit IOG, and read/write data line RWD.
- Each memory cell array MCA contains plural memory cells MC arranged in a matrix-shaped two-dimensional configuration.
- the memory cells MC are arranged at cross points between the bit lines BL and local word lines LWL shown in FIG. 3 .
- the bit lines BL extend in the column direction, and the local word lines LWL extend in the row direction orthogonal to the column direction.
- the main word lines MWL are connected with the local row decoder LRD, and the local row decoder LRD is connected with the memory cells MC via local word lines LWL.
- the respective cell array units CAU in the memory cell macros MCM there is a one-to-one corresponding relationship between the main word lines MWL and the local word lines LWL. Consequently, according to the present embodiment, there is no need to distinguish the main word lines MWL and the local word lines LWL from each other.
- word lines refers to both types.
- Plural memory cell arrays MCA form a cell array unit CAU. As shown in FIG. 1 , four memory cell arrays MCA form a cell array unit CAU. However, there is no specific restriction on the number of memory cell arrays MCA contained in each cell array unit CAU.
- the plural cell array units CAU that share the main word lines MWL form a memory cell macro MCM.
- the memory cell macro MCM is a unit that can be activated under one read command to simultaneously read the data or simultaneously write the data under one write command.
- Plural memory cell macros MCM that share the read global data bus RGDB and write global data bus WGDB form a macro block MB. There is no specific restriction on the number of the cell array units CAU contained in each memory cell macro MCM.
- the sense amplifier S/A is arranged corresponding to plural bit lines BL.
- Sense amplifier S/A detects the data transmitted via specific bit lines among the plural bit lines BL.
- the write driver W/D is arranged corresponding to plural bit lines BL.
- the write driver W/D carries out write of data to the memory cells MC via specific bit lines among the plural bit lines BL.
- Each cell array unit CAU has one or more sense amplifiers S/A and one or more write drivers W/D.
- Plural sense amplifiers S/A in a memory cell macro MCM are connected with different read global data buses RGDB.
- Plural write drivers W/D in a memory cell macro MCM are connected with different write global data buses WGDB. That is, the read global data buses RGDB and the write global data buses WGDB are arranged with a one-to-one corresponding relationship with the sense amplifiers S/A and write drivers W/D, respectively. Consequently, the read global data buses RGDB are arranged corresponding to bit lines and sense amplifiers S/A and write global data buses WGDB are arranged corresponding to the bit lines BL and write drivers W/D, respectively.
- the read global data buses RGDB and the write global data buses WGDB extend in the column direction.
- the main word lines MWL extend in the row direction orthogonal to the column direction.
- the read global data buses RGDB each are connected to the read buffer RB via column decoder CD.
- the write global data buses WGDB each are connected to the write buffer WB via column decoder CD.
- the column decoder CD has the function of selecting the bit line BL according to the column address. In this case, the column decoder CD selects and drives one bit line BL with respect to one sense amplifier S/A.
- the read buffer RB and write buffer WB are connected to the read/write data lines RWD via the input/output gate circuit IOG.
- the read buffer RB amplifies the read data obtained from the corresponding read global data bus RGDB and sends the obtained read data to the input/output gate circuit IOG.
- the read buffer RB then sends the read data to outside elements via the input/output gate circuit IOG.
- the write buffer WB amplifies the write data obtained from the read/write data line RWD, and sends the data to the memory cell macros MCM 1 through MCM 4 .
- the number of read/write data lines RWD is the same as the number of pairs of read buffer RB and write buffer WB. That is, in this embodiment there is one read/write data line RWD for each read buffer RB and write buffer WB pair.
- Read/write data lines RWD can read the data out simultaneously in parallel from one memory cell macro MCM.
- the read/write data lines RWD also can fetch the write data from outside the memory chip for a memory cell macro in parallel with each other the same time. For example, when the number of read buffer RB/write buffer WB pairs in one macro block MBA is 64, then 64 read/write data lines RWD are arranged corresponding to the pairs, respectively. As a result, the memory design would allow simultaneous reading or writing of 64-bit data.
- the main word lines MWL are connected to the row controller RC.
- the row controller RC is connected to the main row decoder MRD.
- the main row decoder MRD decodes the row address. According to the row address, the row controller RC selects one main word line MWL from each of the plural memory cell macros MCM in the macro block MB. As the main word line MWL is selected, the one local word line LWL corresponding to the main word line MWL is selected in each of the cell array units CAU.
- each sense amplifier S/A can detect the data of the memory cell MC (hereinafter to be referred to as selected memory cell MC) corresponding to the cross point between the bit line BL selected by the column address and the main word line MWL (or the local word line LWL) selected by the row address. Also, in the memory cell macro MCM, the respective write driver W/D can write the data into the selected memory cell MC.
- the write data are temporarily stored in the comparison buffer CMPB (see FIG. 3 ) after being transmitted from input/output gate circuit IOG via the read/write data line RWD.
- the data of the write object memory cell MC from the selected page is also temporarily read in to the comparison buffer CMPB.
- the write to the memory cell MC is not yet carried out.
- the comparison buffer CMPB compares the write data with the corresponding read data from the memory cell, then, on the basis of the comparison result, the comparison buffer CMPB controls the write buffer WB such that only the write data different in logic from the read data are written to the memory cell macro MCM.
- the write driver W/D Based on the comparison of read and write data the write driver W/D writes only the write data which does not match the read data from the memory cell MC.
- the comparison buffer CMPB controls the write buffer WB so that the write data are not written in the memory cell macro MCM.
- FIG. 2 is a diagram illustrating the components and operation of a single memory cell MC.
- the respective memory cell MC contain the magnetic tunnel junction element (MTJ) 10 and the cell transistor 20 .
- the MTJ element 10 and the cell transistor 20 are connected in tandem between the bit line BL and the source line SL.
- the cell transistor 20 is arranged on the side neighboring the bit line BL, and the MTJ element 10 is arranged on the side neighboring the source line.
- the gate of the cell transistor 20 is connected to the word line WL (main word line MWL or local word line LWL).
- the MTJ element that exploits the TMR (tunneling magnetoresistive) effect has a laminated structure including two ferromagnetic layers and a nonmagnetic layer (insulating film) sandwiched between them, and it stores the digital data corresponding to change in the magnetic resistance due to the spin polarization tunnel effect.
- the MTJ element acquires a low resistance state or a high resistance state corresponding to the configuration of magnetization of two ferromagnetic layers.
- the low resistance state is defined as 0, while the high resistance state is defined as 1, so that the MTJ element can record 1-bit data.
- the low resistance state is defined as 1
- the high resistance state is defined as 0.
- the MTJ element may be formed, for example, by sequentially laminating an anchoring layer, a tunnel barrier layer, and a recording layer.
- the anchoring layer F and the recording layer P are made of ferromagnetic material, while the tunnel barrier layer is made of an insulating film.
- the anchoring layer F is a layer that anchors the orientation of magnetization.
- the recording layer P can change its orientation of magnetization, so that data can be stored corresponding to the orientation of the magnetization.
- the orientation of the recording layer P becomes the anti-parallel state with respect to the magnetization orientation of the anchoring layer F, and the state becomes the high resistance state (data 1).
- the orientation of magnetization of the anchoring layer F and that of the recording layer P are parallel with each other, and the state becomes the low resistance state (data 0). In this way, the TMJ element can be written with different data depending on the current direction.
- FIG. 3 is a diagram illustrating the connection relationship between the read global data bus RGDB as well as the write global data bus WGDB and the memory cell macros MCM 1 through MCM 4 .
- FIG. 3 shows only one sense amplifier S/A/write driver W/D pair and one read global data bus RGDB/write global data bus WGDB pair. However, in the practical structure, a plurality of these pairs is used.
- the read global data bus RGDB is connected to the read buffer RB, and the write global data bus WGDB is connected to the write buffer WB.
- the read buffer RB and the write buffer WB are connected to the read/write data line RWD via comparison buffer CMPB.
- the comparison buffer CMPB is assembled in the input/output gate circuit IOG.
- the local row decoder LRD is arranged between memory cell arrays MCA in each of the memory cell macros MCM 1 through MCM 4 .
- the local row decoder LRD works as a buffer for driving the local word line LWL. Consequently, row controller RC drives word line WL via main word line MWL and local row decoder LRD. In FIG. 3 , the main word line MWL is not shown.
- the memory cell macros MCM in the same macro block MB share a read global data bus RGDB and a write global data bus WGDB. But, the sense amplifiers S/A in the same memory cell macro MCM are connected to different read global data buses RGDB via plural read latch parts RLCH.
- the read latch parts RLCH are arranged corresponding to the sense amplifiers S/A, and each read latch part RLCH is connected between the sense amplifier S/A and a read global data bus RGDB.
- the read latch part RLCH latches the data detected by the sense amplifier S/A.
- the read latch part RLCH contains a gated inverter In 1 that outputs the latched data at the time determined by the output enable signal SOE_Ci (where i represents an integer).
- the write drivers W/D in the memory cell macro MCM are connected to different write global data buses WGDB via write latch parts WLCH.
- the write latch parts WLCH are arranged corresponding to the write drivers W/D, and each write latch part WLCH is connected between a corresponding write driver W/D and a write global data bus WGDB.
- the write latch part WLCH contains the gated inverter In 2 that receives the write data from the write global data bus WGDB at the time determined by the input enable signal WIE_Ci. As a result, the write latch part WLCH latches the data to be sent to the write driver W/D.
- the sense amplifier S/A and the write driver W/D are connected to the bit line BL selected by the column selection line CSL. As shown in FIG. 3 , while one memory cell array MCA is connected to the sense amplifier S/A, the other memory cell array MCA is connected to the write driver W/D. However, the memory cell array MCA can be connected to both the sense amplifier S/A and the write driver W/D via the column selection line CSL. The voltage of the column selection line CSL is controlled by the column decoder CD.
- the comparison buffer CMPB is a circuit that temporarily stores the write data and the data stored in the selected memory cell MC where the data are to be written in the data write operation, and it compares the logic states of these data.
- one main word line MWL is selected in each memory cell macro MCM, and the data are simultaneously detected by the sense amplifiers S/A via read global data buses RGDB from the memory cells MC connected to the selected main word line MWL.
- the data detected by the sense amplifiers S/A are temporarily stored in the corresponding read latch parts RLCH.
- the output enable signals SOE_C 1 through SOE_C 4 are then sequentially activated consecutively at different times such that the data are continuously output from the read latch parts RLCH of each memory cell macro MCM to the read global data buses RGDB.
- the read data are then temporarily stored in the comparison buffer CMPB via the read global data bus RGDB.
- read latch parts RLCH in one memory cell macro MCM may simultaneously send the data to the corresponding read global data bus RGDB connected to them.
- the read latch parts RLCH in the different memory cell macros MCM of a macro block MB transmit the data to the read global data buses RGDB at different times.
- the comparison buffer CMPB temporarily stores the write data received via the read/write data lines RWD.
- the input enable signals WIE_C 1 through WIE_C 4 are then sequentially activated consecutively, and the data are continuously fetched into the write latch parts WLCH of the respective memory cell macros MCM via the write global data buses WGDB and the write buffers WB.
- the write latch parts WLCH in one memory cell macro MCM may fetch the data simultaneously from comparison buffers CMPB connected to them, respectively.
- data can be transmitted in parallel by using all of the write global data buses WGDB in the macro block MB without waste.
- the write latch parts WLCH of the different memory cell macros MCM in one macro block MB receive the data at different times from one comparison buffer CMPB.
- FIG. 4 is a block diagram illustrating the internal components of a comparison buffer CMPB.
- the comparison buffer CMPB has a multiplexer MUX, D flip-flop circuits DFF 1 , DFF 2 , logic circuit LC, and gate circuit G 1 .
- the multiplexer MUX is connected to the read buffer RB and write buffer WB, and it receives the read data RD 1 through RD 4 and the write data RWD 1 through RWD 4 .
- the read data RD 1 through RD 4 and write data RWD 1 through RWD 4 correspond to the memory cell macros MCM 1 through MCM 4 , respectively.
- the multiplexer MUX transmits any of the read data RD 1 through RD 4 and write data RWD 1 through RWD 4 selectively to the D flip-flop circuit DFF 1 . For example, when the read commands CBR_LTC 1 through CBR_LTC 4 are activated, the multiplexer MUX selects the read data RD 1 through RD 4 ; when the write commands CBW_LTC 1 through CBW_LTC 4 are activated, it selects write data RWD 1 through RWD 4 .
- the gate circuit G 1 is a NOR gate.
- the read commands CBR_LTC 1 through CBR_LTC 4 and write commands CBW_LTC 1 through CBW_LTC 4 are input to it and, the latch command LTC 1 to the D flip-flop circuit DFF 1 is activated when any of these commands are active.
- the D flip-flop circuit DFF 1 as the first latch part latches the read data RD 1 through RD 4 or write data RWD 1 through RWD 4 from the multiplexer MUX.
- the D flip-flop circuit DFF 2 as the second latch part latches the read data RD 1 through RD 4 .
- the D flip-flop circuits DFF 1 , DFF 2 are set so that the read data obtained via the read global data buses RGDB and read buffer RB can be held as one page portion (for example, 128 bits).
- the D flip-flop circuit DFF 1 is set so that it can hold one page portion (for example, 128 bits) of the write data obtained via the read/write data line RWD.
- the logic circuit LC as the logic part receives the pre-charge command PRECH and read data RD 1 through RD 4 or write data RWD 1 through RWD 4 latched in the D flip-flop circuits DFF 1 , DFF 2 .
- the write execution command CBW is activated by the logic circuit LC.
- the logic circuit LC outputs the write execution command CBW to the write buffer WB.
- the logic circuit LC compares the logic of the read data RD 1 through RD 4 from the D flip-flop circuit DFF 2 with the logic of the read data RD 1 through RD 4 or the write data RWD 1 through RWD 4 from the D flip-flop circuit DFF 1 .
- the logic circuit LC activates the write execution command CBW.
- the logic circuit LC maintains the inactive state for the write execution command CBW (i.e., the write execution command CBW is not activated).
- the write buffer WE When the write execution command CBW is activated, the write buffer WE sends the write data of the corresponding address among the write data stored in the D flip-flop circuit DFF 1 to the write driver W/D. When the write execution command CBW is in the inactive state, the write buffer WE does not send the write data of the corresponding address among the write data stored in the D flip-flop circuit DFF 1 to the write driver W/D.
- the pre-charge commands PRECH 1 through PRECH 4 have the bank address (the address of the memory cell macro MCM). Consequently, when the write buffer WB receives the pre-charge commands PRECH 1 through PRECH 4 , it may transfer the write data to any of the memory cell macros MCM 1 through MCM 4 according to the bank address.
- the logic circuit LC is shared by the plural write data RWD 1 through RWD 4 and plural read data RD 1 through RD 4 .
- the logic circuit LC may execute a comparison between the write data RWD 1 through RWD 4 and the read data RD 1 through RD 4 at different times.
- FIG. 5 is a time diagram illustrating the data write operation of the memory according to Embodiment 1.
- each macro block MB contains the four memory cell macros MCM 1 through MCM 4 . Consequently, the write operation (write sequence) to the respective memory cell macros MCM 1 through MCM 4 is started by the four write commands W 1 through W 4 .
- the sense amplifier S/A reads the data from the memory cell MC selected as the write object (the selected memory cell MC), and the read data from the selected memory cell MC are stored in the comparison buffer CMPB. Also, the comparison buffer CMPB receives the write data to be written in the selected memory cell MC from the read/write data line RWD and stores the write data. That is, before the data are actually written, the data are read from the selected memory cell MC. Consequently, on the basis of the write commands W 1 through W 4 , the read commands CBR_LTC 1 through CBR_LTC 4 are also activated.
- the addresses CA (column address, row address, etc.) and the various types of commands Cmd (active command A, write commands W 1 through W 4 , etc.) are sent to the memory.
- the row address one main word line MWL is selected in each memory cell macro MCM, and the local word line LWL in each cell array unit CAU connected to the selected main word line MWL is also selected.
- the bit line BL connected to the respective sense amplifier S/A in the memory cell macro MCM is selected.
- the multiple sense amplifiers S/A in the memory cell macro MCM can simultaneously read the data from the selected memory cells MC connected to the selected bit lines BL and the selected local word lines LWL.
- the memory receives the active command A, and the row address is selected. Next, as the memory receives the write commands W 1 through W 4 , the column address is selected.
- the word enable signal bMWL As the word enable signal bMWL is activated on the low level, according to the row address, it is possible to drive the word lines LWL_C 1 through LWL_C 4 .
- the column selection line CSL When the column selection line CSL is activated on the high level, as explained with reference to FIG. 3 , the bit line BL selected according to the column address is connected to the sense amplifier S/A.
- the sense amplifiers S/A of the respective memory cell macros MCM 1 through MCM 4 can detect the data of the selected memory cells MC.
- the data detected by the sense amplifiers S/A are latched in the read latch part RLCH.
- the output enable signals SOE_C 1 through SOE_C 4 are continuously activated.
- the read data latched in the read latch parts RLCH of the memory cell macros MCM 1 through MCM 4 are sent continuously via the read global data buses RGDB to the comparison buffer CMPB.
- the read commands CBR_LTC 1 through CBR_LTC 4 are continuously activated.
- the read command CBR_LTC 4 When the read command CBR_LTC 4 is activated at t 5 , the data read from the memory cell macro MCM 4 are held in both the D flip-flop circuits DFF 1 , DFF 2 of the comparison buffer CMPB. As a result, the respective read data of the memory cell macros MCM 1 through MCM 4 are stored in the D flip-flop circuits DFF 1 , DFF 2 of the comparison buffer CMPB.
- the D flip-flop circuits DFF 1 , DFF 2 hold the data read from the memory cell macro MCM 2 aside (separate) from the read data from the memory cell macro MCM 1 and the write data to the memory cell macro MCM 1 .
- the D flip-flop circuits DFF 1 , DFF 2 hold the read data from the memory cell macro MCM 3 aside from the read data from memory cell macros MCM 1 , MCM 2 and the write data to the memory cell macros MCM 1 , MCM 2 .
- the D flip-flop circuits DFF 1 , DFF 2 hold the read data from the memory cell macro MCM 4 aside from the read data from the memory cell macros MCM 1 through MCM 3 and the write data to the memory cell macros MCM 1 through MCM 3 .
- the write data are sent to the comparison buffer CMPB via the data line DQ.
- the comparison buffer CMPB stores the write data RWD 1 through RWD 4 .
- the write command CBW_LTC 1 is activated.
- the write command CBW_LTC 1 corresponds to the read command CBR_LTC 1 , and it has the address of the selected memory cell MC of the memory cell macro MCM 1 . That is, the write data sent to the comparison buffer CMPB due to activation of the write command CBW_LTC 1 are data having the same address as the read data sent to the comparison buffer CMPB due to activation of the read command CBR_LTC 1 .
- the D flip-flop circuit DFF 1 of the comparison buffer CMPB shown in FIG. 4 holds the write data.
- the read data stored in the D flip-flop circuit DFF 1 are refreshed (overwritten) by the write data. This is because the write command CBW_LTC 1 and the read command CBR_LTC 1 show the selected memory cells MC with the same address.
- the read data from the selected memory cell MC of the memory cell macro MCM 1 are held in the D flip-flop circuit DFF 2 .
- the data to be written in the selected memory cell MC of the memory cell macro MCM 1 are held in the D flip-flop circuit DFF 1 .
- the write command CBW_LTC 1 is activated. This means that the memory continuously receives the write data of the same address. In the series of write sequences, when plural write data of the same address are received, the finally received write data are the effective data. Consequently, the data to be written in the selected memory cell MC of the memory cell macro MCM 1 are refreshed each time that activation of the write command CBW_LTC 1 is carried out at the time of t 1 through t 4 . The D flip-flop circuit DFF 1 then effectively holds the write data RWD 1 finally received at time t 6 .
- the write command CBW_LTC 1 is activated four times with the incoming write data being 1, 1, 1, 0, respectively.
- the finally received piece of data “0” is taken as the write data RWD 1 that will be written to the selected memory cell MC.
- the write command CBW_LTC 2 is activated.
- the write command CBW_LTC 2 corresponds to the read command CBR_LTC 2 , and it has the address of the selected memory cell MC of the memory cell macro MCM 2 .
- the D flip-flop circuit DFF 1 of the comparison buffer CMPB holds the write data.
- the read data stored in the D flip-flop circuit DFF 1 are refreshed by the write data. This is because the write command CBW_LTC 2 and the read command CBR_LTC 2 show the selected memory cells MC of the same address.
- the read data from the selected memory cell MC of the memory cell macro MCM 2 are held in the D flip-flop circuit DFF 2
- the data to be written in the selected memory cell MC of the memory cell macro MCM 2 are held in the D flip-flop circuit DFF 1 .
- the write command CBW_LTC 2 is activated only once. Consequently, the D flip-flop circuit DFF 1 effectively holds the write data RWD 2 received at time t 4 .
- the D flip-flop circuit DFF 1 holds the write data RWD 2 aside from the write data RWD 1 .
- the D flip-flop circuit DFF 2 holds the read data RD 2 aside from the read data RD 1 .
- the write command CBW_LTC 3 is activated.
- the write command CBW_LTC 3 corresponds to the read command CBR_LTC 3 , and it has the address of the selected memory cell MC of the memory cell macro MCM 3 .
- the D flip-flop circuit DFF 1 of the comparison buffer CMPB holds the write data.
- the read data stored in the D flip-flop circuit DFF 1 due to activation of the read command CBR_LTC 3 are refreshed by the write data. This is because the write command CBW_LTC 3 and the read command CBR_LTC 3 show the selected memory cells MC of the same address.
- the read data from the selected memory cell MC of the memory cell macro MCM 3 are held in the D flip-flop circuit DFF 2
- the data to be written in the selected memory cell MC of the memory cell macro MCM 3 are held in the D flip-flop circuit DFF 1 .
- the write command CBW_LTC 3 is activated twice.
- the D flip-flop circuit DFF 1 effectively holds the last write data RWD 3 fetched at t 6 .
- the D flip-flop circuit DFF 1 holds the write data RWD 3 aside from the write data RWD 1 and RWD 2 .
- the D flip-flop circuit DFF 2 holds the read data RD 3 aside from the read data RD 1 and RD 2 .
- the write command CBW_LTC 4 is activated.
- the write command CBW_LTC 4 corresponds to the read command CBR_LTC 4 , and it has the address of the selected memory cell MC of the memory cell macro MCM 4 .
- the D flip-flop circuit DFF 1 of the comparison buffer CMPB holds the write data.
- the read data stored in the D flip-flop circuit DFF 1 due to activation of the read command CBR_LTC 4 are refreshed by the write data. This is because the write command CBW_LTC 4 and read command CBR_LTC 4 indicate the selected memory cells MC of the same address.
- the read data from the selected memory cell MC of the memory cell macro MCM 4 are held in the D flip-flop circuit DFF 2
- the data to be written in the selected memory cell MC of the memory cell macro MCM 4 are held in the D flip-flop circuit DFF 1 .
- the write command CBW_LTC 4 is activated thrice.
- the D flip-flop circuit DFF 1 effectively holds the last write data RWD 4 received at t 8 .
- the D flip-flop circuit DFF 1 holds the write data RWD 4 aside from the write data RWD 1 through RWD 3 .
- the D flip-flop circuit DFF 2 holds the read data RD 4 aside from the read data RD 1 through RD 3 .
- the comparison buffer CMPB latches the write data RWD 1 through RWD 4 and read data RD 1 through RD 4 corresponding to the addresses of the plural selected memory cells MC in a series of respective write sequences.
- the write sequence comes to an end, and the pre-charge commands PRECH 1 through PRECH 4 are activated.
- the number of pre-charge commands PRECH 1 through PRECH 4 generated is equal to the number (bank number) of the memory cell macros MCM that execute the interleaved operation.
- the logic circuit LC of the comparison buffer CMPB compares the logic of the read data RD 1 through RD 4 with that of the write data RWD 1 through RWD 4 for each of their addresses. In this case, the logic circuit LC detects the difference/identity in the logic of the output data of the D flip-flop circuits FFD 1 and FFD 2 for each address.
- the logic circuit LC activates the write execution commands CBW_A 1 through CBW_A 4 .
- the logic circuit LC activates the write execution command CBW_A 1 .
- the logic circuit LC When the read data RD 1 through RD 4 and the write data RWD 1 through RWD 4 have the same logic, the logic circuit LC does not activate the write execution commands CBW_A 1 through CBW_A 4 ; instead, it keeps them in the inactive state. For example, when the read data RD 2 and write data RWD 2 have the same logic state, the logic circuit LC does not activate the write execution command CBW_A 2 ; instead, it keeps the command in the inactive state.
- the read data RD 1 and the write data RWD 1 have different logic states, as do the read data RD 4 and write data RWD 4 .
- the write data RWD 2 and RWD 3 has the same logic read data RD 2 and RD 3 , respectively. Consequently, the logic circuit LC activates the write execution commands CBW_A 1 and CBW_A 4 (t 10 , t 13 ), while it keeps the write execution commands CBW_A 2 and CBW_A 3 in the inactive state.
- the write buffer WB sends the write data RWD 1 , RWD 4 via the write global data bus WGDB to the write drivers W/D of the memory cell macros MCM 1 , MCM 4 .
- the write data RWD 1 , RWD 4 are stored in the D flip-flop circuit DFF 1 , respectively, they are sent from the D flip-flop circuit DFF 1 .
- the input enable signal WIE_C 1 is activated, and the write latch part WLCH of the memory cell macro MCM 1 receives the write data RWD 1 .
- the input enable signal WIE_C 4 is activated, and the write latch part WLCH of the memory cell macro MCM 4 receives the write data RWD 4 .
- the input enable signals WIE_C 2 , WIE_C 3 for the memory cell macros MCM 2 , MCM 3 which will not have different data written to them, are not activated.
- the write data RWD 1 , RWD 4 are written in the selected memory cells MC of the memory cell macros MCM 1 , MCM 4 .
- the comparison buffer CMPB compares the logic of the read data RD 1 through RD 4 with the logic of the write data RWD 1 through RWD 4 . If the logic of the read data is different from the logic of the write data, the write driver W/D writes the write data to the corresponding selected memory cell. On the other hand, if the logic of the read data is identical to the logic of the write data, the write driver W/D does not write the write data to the corresponding selected memory cell.
- the write driver W/D may execute the write operation to the selected memory cell MC (that is, cell current may be made to flow to the selected memory cell MC) only in the memory cell macros MCM 1 , MCM 4 that have the logic of the write data different from the logic of the data already stored in the selected memory cell MC.
- the memory cell macros MCM 2 , MCM 3 with the logic of the write data identical to the logic of the data stored in the selected memory cell MC there is no need for the write driver W/D to carry out write operation to the selected memory cell MC (that is, there is no need to have a cell current flow to the selected memory cell MC). As a result, it is possible to suppress the wasteful power consumption in the data write operation.
- the write data RWD 1 through RWD 4 fetched by a series of write commands W 1 through W 4 are temporarily stored in the comparison buffer CMPB.
- the pre-charge commands PRECH 1 through PRECH 4 are activated, so that the comparison buffer CMPB activates the write execution commands CBW_A 1 through CBW_A 4 .
- the write driver W/D executes the actual write operation to the selected memory cell MC during the pre-charge period. Consequently, the write time from the viewpoint of the user is only the time of data write to the write buffer WB, and the actual write time to the selected memory cell MC is not sensed by the user.
- the MRAM has an extremely high write operation speed, and an interleaved write operation can be easily carried out.
- the four pre-charge commands PRECH 1 through PRECH 4 have the addresses (bank addresses) of the memory cell macros MCM 1 through MCM 4 respectively, it is possible to have the write operation to the respective memory cell macros MCM 1 through MCM 4 dispersed in time during the pre-charge period. As a result, it is possible to prevent simultaneous write operation to plural memory cell macros MCM, and it is possible to suppress instant surge of the current consumption. That is, according to the present embodiment, the MRAM can have an even write current.
- the comparison buffer CMPB holds only the last received write data RWD 1 through RWD 4 .
- the write driver W/D writes the last received write data RWD 1 through RWD 4 to the selected memory cells MC. Consequently, even when a memory cell MC of the same memory cell macro MCM is repeatedly accessed over a short time (that is, a time shorter than the time needed for write of the data to the MTJ element), there will still be no defective write and the necessary time for writing the data to the MTJ element can be sufficiently obtained.
- the comparison buffer CMPB may store two or more pages of data in each of the read buffer RB and the write buffer WB. Each page is a data read unit or a data write unit.
- the data are temporarily stored in the comparison buffer CMPB, and they are then output to the outside via the read/write data line RWD.
- the data read operation through the step involving storage of the read data in the comparison buffer CMPB can be easily understood with reference to FIG. 5 and the accompanying explanation above. Consequently, the operation from detection of the read data to storage of the data in the comparison buffer CMPB will not be explained repeatedly.
- the memory instead of the write commands W 1 through W 4 supplied previously, the memory receives the read commands R 1 through R 4 , and the read operation is executed on the basis of the read commands R 1 through R 4 .
- the comparison buffer CMPB may output the read data stored in the D flip-flop circuit DFF 1 via the read/write data line RWD without alteration.
- the read latch parts RLCH of the respective memory cell macros MCM 1 through MCM 4 send the data sequentially to the read global data bus RGDB on the basis of the output enable signals SOE_C 1 through SOE_C 4 . Consequently, it is possible to carry out a burst read operation.
- FIG. 6 is a block diagram illustrating the components of an MRAM device according to Embodiment 2.
- the read global data bus RGDB and the write global data bus WGDB are shared, and they are set as the global data bus RWGDB.
- the read latch part RLCH and write latch part WLCH of the respective memory cell macros MCM 1 through MCM 4 are both connected to the global data bus RWGDB, and they are then connected to the comparison buffer CMPB via the global data bus RWGDB. Consequently, while the comparison buffer CMPB in Embodiment 1 is of the dual port type, the comparison buffer CMPB in Embodiment 2 is of the single port type.
- the time for transferring the write data in the write global data bus WGDB (t 11 to t 14 ) is during the pre-charge period. Consequently, the time of transfer of the write data in the write global data bus WGDB does not overlap the time (t 1 to t 5 ) in which the transfer of the read data in the read global data bus RGDB occurs. Consequently, there is no problem even when the global data bus RWGDB is shared as in Embodiment 2.
- the read buffer RB and the write buffer WB can, therefore, be connected to the shared global data bus RWGDB.
- the functions of the read buffer RB and the write buffer WB are the same as in Embodiment 1.
- the remaining features of Embodiment 2 may be the same as the corresponding features in Embodiment 1.
- FIG. 7 is a time diagram illustrating the data write operation of the memory according to Embodiment 2.
- the global data bus RWGDB is shared for read and write, and the read data and the write data are transferred at different times.
- the remaining features of the operation according to Embodiment 2 may be the same as those of the corresponding features of the operation according to Embodiment 1.
- Embodiment 2 the same effects as those of Embodiment 1 can be realized.
- the global data bus RWGDB is shared for the read and write, so that the separate read buffer RB and write buffer WB are omitted. Consequently, the MRAM according to Embodiment 2 is favorable for forming smaller memory chips.
- FIG. 8 is a block diagram illustrating the components of the MRAM according to Embodiment 3.
- ECC (error correcting code) decoder ECCDEC is arranged between the read buffer RB and the comparison buffer CMPB
- ECC encoder ECCENC is arranged between the write buffer WB and the comparison buffer CMPB.
- the other features of Embodiment 3 may be the same as the corresponding features of Embodiment 1.
- FIG. 9 is a block diagram illustrating the components of the comparison buffer CMPB according to Embodiment 3.
- the components of the comparison buffer CMPB itself is the same as the components of the comparison buffer CMPB in Embodiment 1.
- multiplexer MUX receives the read data PRD 1 through PRD 4 corrected by the ECC decoder ECCDEC. Consequently, by means of activation of the read commands CBR_LTC 1 through CBR_LTC 4 , the D flip-flop circuit DFF 1 latches the corrected read data PRD 1 through PRD 4 .
- the data write operation according to Embodiment 3 is otherwise the same as the data write operation according to Embodiment 1.
- the D flip-flop circuit DFF 1 latches the corrected read data PRD 1 through PRD 4 .
- the D flip-flop circuit DFF 1 is updated by the write data RWD 1 through RWD 4 .
- the comparison buffer CMPB compares the read data RD 1 through RD 4 actually stored in the selected memory cell MC with the write data RWD 1 through RWD 4 .
- the D flip-flop circuit DFF 1 stores the corrected read data PRD 1 through PRD 4
- the D flip-flop circuit DFF 2 stores the read data RD 1 through RD 4 . Consequently, when the corrected read data PRD 1 through PRD 4 and the read data RD 1 through RD 4 are different from each other, the logic circuit LC activates the write execution commands CBW_A 1 through CBW_A 4 .
- the write buffer WB has the corrected read data PRD 1 through PRD 4 held in the D flip-flop circuit DFF 1 written in the memory cell MC. That is, when the logic of the data stored in the memory cells MC is incorrect, the comparison buffer CMPB can write the corrected read data PRD 1 through PRD 4 to correct the memory cells MC.
- Embodiment 3 may also be used on the MRAM having an ECC circuit.
- the remaining features of operation of Embodiment 3 may be the same as those of Embodiment 1.
- Embodiment 3 also can realize the same effects as those of Embodiment 1.
- FIG. 10 is a block diagram illustrating the components of the MRAM according to Embodiment 4.
- Embodiment 4 is a combination of Embodiment 2 and Embodiment 3. That is, according to Embodiment 4, the read global data bus RGDB and the write global data bus WGDB are shared, and they are set as the global data bus RWGDB. Also, an ECC decoder ECCDEC and ECC encoder ECCEN are arranged between the comparison buffer CMPB and the read buffer RB as well as the write buffer WB.
- the global data bus RWGDB is shared for read and write.
- the read data and the write data are transferred at different times. Consequently, even when the global data bus RWGDB shown in FIG. 10 is shared, there is still no problem.
- the MRAM has the ECC circuit ECCDEC and ECCENC, the comparison buffer CMPB works in the same way as the comparison buffer CMPB in Embodiment 3.
- Embodiment 4 has both the effects of Embodiment 2 and Embodiment 3.
- FIG. 11 is a block diagram illustrating the components of the MRAM according to Embodiment 5.
- FIG. 12 is a block diagram illustrating the components of the comparison buffer CMPB according to Embodiment 5.
- the logic circuits LC 1 through LC 4 are arranged in the memory cell macros MCM 1 through MCM 4 , respectively.
- the logic circuits LC 1 through LC 4 have a similar components and function as that of the logic circuit LC in Embodiment 1.
- the logic circuits LC 1 through LC 4 are connected to the read latch part RLCH and receive the read data RD 1 through RD 4 from the read latch part RLCH directly, not through the read global data bus RGDB.
- the logic circuits LC 1 through LC 4 are connected to the write latch part WLCH and transfer the write data RWD 1 through RWD 4 directly to the write latch part WLCH, not through the write global data bus WGDB.
- the multiplexer MUX, D flip-flop circuit DFF 1 , and gate circuit G 1 are set between the read buffer RB as well as write buffer WE and the read/write data line RWD just as in the other embodiments.
- the D flip-flop circuit DFF 2 of the comparison buffer CMPB can be omitted.
- the components of the D flip-flop circuit DFF 1 , multiplexer MUX and gate circuit G 1 may be the same as that shown in FIG. 4 . Consequently, the multiplexer MUX receives the read data RD 1 through RD 4 (or the corrected read data PRD 1 through PRD 4 ) via the read global data bus RGDB.
- the comparison buffer CMPB directly receives the read data RD 1 through RD 4 from the read latch part RLCH, so that there is no need to have a D flip-flop circuit DFF 2 .
- the read data RD 1 through RD 4 are latched in the read latch part RLCH, shown in FIG. 11 .
- the read data RD 1 through RD 4 are directly sent to the logic circuits LC 1 through LC 4 .
- the read data RD 1 through RD 4 are stored in the D flip-flop circuit DFF 1 via the read global data bus RGDB.
- the operation for storage of the read data RD 1 through RD 4 in the D flip-flop circuit DFF 1 in the comparison buffer CMPB is the same as the corresponding operation in Embodiment 1.
- the operation of holding of the write data RWD 1 through RWD 4 in the D flip-flop circuit DFF 1 is the same as the corresponding operation in Embodiment 1.
- the D flip-flop circuit DFF 1 stores the write data RWD 1 through RWD 4 .
- the pre-charge commands PRECH 1 through PRECH 4 are sequentially activated.
- the logic circuits LC 1 through LC 4 compare the write data RWD 1 through RWD 4 with the read data RD 1 through RD 4 .
- the logic circuits LC 1 through LC 4 activate the write execution commands CBW_A 1 through CBW_A 4 .
- the write data RWD 1 through RWD 4 are sent to the logic circuits LC 1 through LC 4 and the write latch parts WLCH of the memory cell macros MCM 1 through MCM 4 respectively.
- the write latch parts WLCH of the memory cell macros MCM 1 through MCM 4 latch the write data RWD 1 through RWD 4 respectively.
- the write execution commands CBW_A 1 through CBW_A 4 are directly fed from the logic circuits LC 1 through LC 4 to the write driver W/D. Consequently, as the write execution commands CBW_A 1 through CBW_A 4 are activated, the write driver W/D starts the write operation for the write data RWD 1 through RWD 4 .
- the memory After the end of a series of write sequences, the memory enters the pre-charge state.
- the write data RWD 1 through RWD 4 are sent to the write latch part WLCH either directly or via the logic circuits LC 1 through LC 4 . Consequently, the pre-charge commands PRECH 1 through PRECH 4 that activate the write execution commands CBW_A 1 through CBW_A 4 may be simultaneously activated. That is, the memory cell macros MCM 1 through MCM 4 may be simultaneously set in the pre-charge state.
- the logic circuit should be arranged for each of the memory cell macros MCM 1 through MCM 4 .
- the D flip-flop circuit DFF 2 can be omitted.
- Embodiment 5 also can realize the effects of Embodiment 1.
- Embodiment 5 may be used in Embodiment 2. That is, according to Embodiment 5, the read global data bus RGDB and the write global data bus WGDB may be shared and set as the global data bus RWGDB. In this case, Embodiment 5 can also realize the effects of Embodiment 2.
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JP5443420B2 (en) * | 2011-03-23 | 2014-03-19 | 株式会社東芝 | Semiconductor memory device |
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KR102646755B1 (en) * | 2017-01-06 | 2024-03-11 | 삼성전자주식회사 | Memory device comprising resistance change material method for operating the memory device |
JP2018112883A (en) * | 2017-01-11 | 2018-07-19 | 東芝メモリ株式会社 | Semiconductor memory |
JP2019053794A (en) * | 2017-09-13 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor storage device |
JP2020047352A (en) * | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | Semiconductor storage device |
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