USRE45817E1 - Nonvolatile semiconductor memory device comprising memory cell array having multilayer structure - Google Patents
Nonvolatile semiconductor memory device comprising memory cell array having multilayer structure Download PDFInfo
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- USRE45817E1 USRE45817E1 US14/175,738 US201414175738A USRE45817E US RE45817 E1 USRE45817 E1 US RE45817E1 US 201414175738 A US201414175738 A US 201414175738A US RE45817 E USRE45817 E US RE45817E
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H01L27/2481—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01L27/2409—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H01L45/147—
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- H01L45/1675—
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
Definitions
- the present invention relates to a nonvolatile semiconductor device, and in particular, to a nonvolatile semiconductor memory device having a memory cell array with a multilayer structure.
- Flash memories in which memory cells having a floating gate structure are NAND- or NOR-connected to form a memory cell array have been well known as conventional nonvolatile memories that is electrically rewritable.
- ferroelectric memories are also known as nonvolatile memories that make high speed random access possible.
- variable resistance elements phase change memory elements whose resistance value changes as a chalcogenide compound switches between a crystal and an amorphous state, MRAM elements in which the resistance changes due to the tunneling magnetoresistive effects, memory elements of a polymer ferroelectric RAM (PFRAM) in which resistive elements are formed of a conductive polymer, ReRAM elements in which resistance changes through the application of an electrical pulse, and the like are known (Patent Document 1: Japanese Patent Application Laid-Open No. 2006-344349, paragraph 0021).
- PFRAM polymer ferroelectric RAM
- memory cells can be formed of a series circuit of a Schottky diode and a variable resistance element instead of a transistor, and therefore, a cross point structure in which memory cells are placed at intersections of upper and lower wires can be used.
- Patent Document 2 Japanese Patent Application Laid-Open No. 2005-522045.
- a memory cell array can have a multilayer structure in these resistance change memories so that the capacity of the non-volatile memory can be increased.
- a nonvolatile semiconductor memory device including a memory cell array in which a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, the memory cells having a variable resistance element and a non-ohmic element laminated in a direction in which the memory cell layers are laminated, and being tapered in such a manner that an area in a cross section gradually becomes smaller from a bottom memory cell layer towards a top memory cell layer, and the variable resistance element and the non-ohmic element of the memory cells being laminated in the same order between a certain memory cell layer and another memory cell layer.
- a nonvolatile semiconductor memory device including a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, the memory cells having a variable resistance element and a non-ohmic element laminated in a direction in which the memory cell layers are laminated, and being tapered in such a manner that an area in a cross section gradually becomes smaller from a bottom memory cell layer towards a top memory cell layer, and the variable resistance element and the non-ohmic element of the memory cells in a certain memory cell layer being laminated in the same order and have substantially the same size as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.
- a method for manufacturing a nonvolatile semiconductor memory device including: forming a semiconductor substrate; depositing a first interlayer insulating film above the semiconductor substrate; forming, in the first interlayer insulating film, a plurality of first trenches extending in a first direction and having such a depth as not to hit a top surface of the semiconductor substrate; filling the first trenches with a wire material to form a plurality of first wires extending in the first direction; sequentially layering a material for a first element and a material for a second element for forming memory cells in a lower layer; carrying out anisotropic etching on the materials for the first and second elements for forming the memory cells in the lower layer to form the memory cells in the lower layer at intersections of the first wires and a plurality of second wires to be formed afterwards so as to extend in a second direction that crosses the first direction in tapered pillar form where an area in a cross section gradually becomes smaller from the bottom layer
- FIG. 1 is a block diagram showing a nonvolatile memory according to a first embodiment of the present invention
- FIG. 2 is a perspective view showing part of the memory cell array of the nonvolatile memory according to the first embodiment
- FIG. 3 is a cross-sectional view along line I-Iโฒ in FIG. 2 showing one memory cell as viewed in the direction of the arrows;
- FIG. 4 is a schematic cross-sectional view showing an example of a variable resistance element according to the first embodiment
- FIG. 5 is a circuit diagram showing the memory cell array and its peripheral circuit in the nonvolatile memory according to the first embodiment
- FIG. 6 is a cross-sectional view showing the nonvolatile memory according to the first embodiment
- FIG. 7 is a perspective view showing one of the steps of forming an upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 8 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 9 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the first embodiment.
- FIG. 10 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 11 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 12 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 13 is a perspective view showing another step of forming the upper layer portion of the nonvolatile memory according to the first embodiment
- FIG. 14 is a perspective view showing one of the steps of forming an upper layer portion of a nonvolatile memory according to a second embodiment of the present invention.
- FIG. 15 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the second embodiment
- FIG. 16 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the second embodiment
- FIG. 17 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the second embodiment
- FIG. 18 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the second embodiment
- FIG. 19 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the second embodiment.
- FIG. 20 is a cross-sectional view showing memory cells of the nonvolatile memory according to the second embodiment
- FIG. 21 is a cross-sectional view showing other memory cells of the nonvolatile memory according to the second embodiment.
- FIG. 22 is a perspective view showing one of the steps of forming an upper layer portion of a nonvolatile memory according to a third embodiment of the present invention.
- FIG. 23 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the third embodiment.
- FIG. 24 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the third embodiment.
- FIG. 25 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the third embodiment.
- FIG. 26 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the third embodiment.
- FIG. 27 is a perspective view showing the next step of forming the upper layer portion of the nonvolatile memory according to the third embodiment.
- FIG. 28 is a cross-sectional view showing memory cells of the nonvolatile memory according to the third embodiment.
- FIG. 29 is a cross-sectional view showing memory cells of a nonvolatile memory according to a comparative example.
- FIG. 1 is a block diagram showing a nonvolatile memory according to a first embodiment of the present invention.
- This nonvolatile memory is provided with a memory cell array 1 where memory cells using a later-described ReRAM (variable resistance element) are arranged in a matrix.
- a column control circuit 2 which controls bit lines BL in the memory cell array 1 , erases data in memory cells, writes data into memory cells, and reads data from memory cells, is provided in a position adjacent to the memory cell array 1 in the direction of the bit lines BL (hereinafter referred to as direction of columns).
- a row control circuit 3 which selects a word line WL in the memory cell array 1 , erases data in memory cells, writes data into memory cells, reads data from memory cells, and applies a voltage required to read data from memory cells, is provided in a position adjacent to the memory cell array 1 in the direction of the word lines WL, which are first wires in the memory cell array 1 (hereinafter referred to as direction of rows).
- a data input/output buffer 4 is connected to an external host, not shown, via an I/O line, receives write data, receives erasure instructions, outputs read data, and receives address data and command data.
- the data input/output buffer 4 sends the received write data to the column control circuit 2 , receives the data read from the column control circuit 2 , and outputs the data to the outside.
- the address supplied from the outside to the data input/output buffer 4 is sent via an address register 5 to the column control circuit 2 and the row control circuit 3 .
- the command supplied from the host to the data input/output buffer 4 is sent to a command interface 6 .
- the command interface 6 receives an external control signal from the host, determines whether the data input into the data input/output buffer 4 is write data, a command or an address, and transfers the data to a state machine 7 as a reception command signal in the case where the data is a command.
- the state machine 7 manages the entire nonvolatile memory, and thus, receives a command from the host and reads, writes, erases, and inputs/outputs data.
- the external host receives status information managed by the state machine 7 , and thus can determine the operation results. Furthermore, this status information is used for the control of write and erasure.
- the state machine 7 controls a pulse generator 9 .
- This control makes it possible for the pulse generator 9 to output a pulse having an arbitrary voltage at an arbitrary timing.
- FIG. 2 is a perspective view showing part of the memory cell array 1
- FIG. 3 is a cross-sectional view along line I-Iโฒ in FIG. 2 showing one memory cell as viewed in the direction of the arrows.
- a plurality of word lines WL 0 to WL 2 are provided in parallel as first wires, a plurality of bit lines BL 0 to BL 2 are provided in parallel as second wires crossing the first wires, and memory cells MC are provided at intersections of these wires so as to be sandwiched by the two wires.
- the first and second wires prefferably be made of a material that is heat-resistant and has a low resistance value, and W, WSi, NiSi and CoSi can be used, for example.
- the memory cells MC are formed of a circuit where a variable resistance element VR and a non-ohmic element NO are connected in series.
- the resistance value of the variable resistance element VR changes through the application of a voltage as a result of a change in the current, heat, chemical energy and the like, and electrodes EL 2 and EL 3 , which function as a barrier metal and an adhesive layer, are provided above and beneath the variable resistance element VR.
- the material for the electrodes Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrO x , PtRhO x , Rh/TaAIN and the like can be used.
- a metal film in order to make the orientation uniform. It is also possible to insert a buffer layer, a barrier metal layer and an adhesive layer separately.
- a complex compound which includes a cation becoming a transition element and whose resistance value changes as the cation moves can be used for the variable resistance element VR.
- FIG. 4 is a diagram showing an example of such a variable resistance element.
- This variable resistance element VR has a recording layer 12 placed between electrode layers 11 and 13 .
- the recording layer 12 is formed of a complex compound having at least two types of cation elements. At least one type of the cation elements is a transition element having a d-or-bital not completely filled with electrons, and the shortest distance between the adjacent cation elements is 0.32 nm or less.
- a x M y X z (A and M are elements different from each other) and is formed of a material having a crystal structure, such as a spinel structure (AM 2 O 4 ), an ilmenite structure (AMO 3 ), a delafossite structure (AMO 2 ), an LiMoN 2 structure (AMN 2 ), a wolframite structure (AMO 4 ), an olivine structure (A 2 MO 4 ), a hollandite structure (A x MO 2 ), a rams-dellite structure (A x MO 2 ) and a perovskite structure (AMO 3 ).
- a spinel structure AM 2 O 4
- AMO 3 ilmenite structure
- AMO 2 delafossite structure
- AMO 2 LiMoN 2 structure
- AMO 4 a wolframite structure
- AMO 4 an olivine structure
- a x MO 2 hollandite structure
- a x MO 2 a rams-
- A is Zn
- M is Mn
- X is O.
- the small white circles, the large white circles and the small black circles in the recording layer 12 represent diffusion ions (Zn), anions (O) and transition element ions (Mn), respectively.
- the recording layer 12 is initially in a high resistance state, and when the electrode layer 11 is set at a fixed potential and a negative voltage is applied to the electrode layer 13 , diffusion ions in the recording layer 12 partially move to the electrode layer 13 side so that the diffusion ions in the recording layer 12 are reduced relative to the anions.
- the diffusion ions that have moved towards the electrode layer 13 side receive electrons from the electrode layer 13 and are deposited as a metal so that a metal layer 14 is formed.
- the non-ohmic element NO is formed of any type of diode, such as (a) a Schottky diode, (b) a PN junction diode and (c) a PIN diode, (d) an MIM (metal-insulator-metal) structure or (e) an SIS (silicon-insulator-silicon) structure. Electrodes EL 1 and EL 2 for forming barrier metal layers and adhesive layers may be inserted herein. In addition, in the case where a diode is used, a unipolar operation can be carried out corresponding to the properties thereof, while in the case of an MIM structure or an SIS structure, it is possible to carry out a bipolar operation.
- a plurality of the above-described memory structures can be layered on top of each other so that a three-dimensional structure can be provided.
- FIG. 5 is a circuit diagram showing the memory cell array 1 using diodes SD as non-ohmic elements NO, as well as its peripheral circuit.
- the circuit has a one layer structure.
- the anode of the diodes SD that form the memory cells MC is connected to a word line WL, and the cathode is connected to a bit line BL via a variable resistance element VR.
- One end of each bit line BL is connected to a selection circuit 2 a, which is part of the column control circuit 2 .
- one end of each word line WL is connected to a selection circuit 3 a, which is part of the row control circuit 3 .
- the selection circuit 2 a is formed of selection PMOS transistors QP 0 and selection NMOS transistors QN 0 , which are provided for every bit line BL and whose gates and drains are connected to each other.
- the source of the selection PMOS transistors QP 0 is connected to a high potential power supply Vcc.
- the source of the selection NMOS transistors QN 0 is connected to a bit line side drive sensing line BDS which applies a write pulse and through which a current to be detected at the time of data read flows.
- the common drain of the transistors QP 0 and QN 0 is connected to a bit line BL, and a bit line selection signal BSi for selecting a bit line BL is supplied to the common gate.
- the selection circuit 3 a is formed of selection PMOS transistors QP 1 and selection NMOS transistors QN 1 , which are provided for every word line WL and whose gates and drains are connected to each other.
- the source of the selection PMOS transistors QP 1 is connected to a word line side drive sensing line WDS which applies a write pulse and through which a current to be detected at the time of data read flows.
- the source of the selection NMOS transistors QN 1 is connected to a low potential power supply Vss.
- the common drain of the transistors QP 1 and QN 1 is connected to a word line WL, and a word line selection signal /WSi for selecting a word line WL is supplied to the common gate.
- the memory cell array 1 may have diodes SD with the opposite polarity to the circuit shown in FIG. 5 , so that a current flows from the bit line BL side to the word line WL side.
- FIG. 6 is a cross-sectional view showing a nonvolatile memory including one layer of the above-described memory structure.
- An impurity diffusion layer 23 and a gate electrode 24 of the transistors that form a peripheral circuit are formed on a silicon substrate 21 in which a well 22 is formed.
- a first interlayer insulating film 25 is deposited on top. Vias 26 that extend to the surface of the silicon substrate 21 are formed in this first interlayer insulating film 25 .
- a first metal 27 for forming word lines WL which are first wires for the memory cell array is formed of a low resistance metal, such as W, on top of the first interlayer insulating film 25 .
- a barrier metal 28 is formed in a layer above the first metal 27 .
- a barrier metal may also be formed in a layer beneath the first metal 27 .
- the barrier metal can be formed of Ti and/or TiN.
- Non-ohmic elements 29 such as diodes, are formed above the barrier metal 28 .
- a first electrode 30 , a variable resistance element 31 and a second electrode 32 are formed on top of the non-ohmic elements 29 in this order.
- the layers from the barrier metal 28 to the second electrodes 32 are formed as memory cells MC.
- barrier metals may be inserted beneath the first electrodes 30 and above the second electrodes 32 , or barrier metals, adhesive layers and the like may be inserted beneath the second electrodes 32 and above the lower electrodes.
- a stopper for CMP or the like may be inserted above the second electrodes 32 .
- the space between adjacent memory cells MC is filled with a second interlayer insulating film 34 and a third interlayer insulating film 35 ( FIG. 6 does not show the second interlayer insulating film 34 ).
- a second metal 36 for forming bit lines BL which are second wires extending in a direction perpendicular to the word lines WL is formed above the memory cells MC in the memory cell array.
- a fourth interlayer insulating film 37 and a metal wiring layer 38 are formed on the second metal 36 , so that a nonvolatile memory, which is a resistance change memory, is formed.
- the layers from the barrier metal 28 to the second electrode 32 and the formation of the second and third interlayer insulating films 34 and 35 between the memory cells MC are repeated the same number of times as the necessary number of layers.
- an FEOL (front end of line) process is carried out on a silicon substrate 21 in order to form transistors for forming a necessary peripheral circuit, and a first interlayer insulating film 25 is deposited on top.
- vias 26 are created.
- FIGS. 7 to 12 are perspective views illustrating the steps for forming the upper layers in sequence. The process for forming the upper layers is described below in reference to these FIGS. 7 to 12 .
- a memory cell layer 27 a (first wire material) is deposited on top as a first metal 27 , and after that, in order to form memory cells, a layer 28 a is formed as a barrier metal 28 , a layer 29 a is deposited as a non-ohmic element 29 , a layer 30 a is deposited as a first electrode 30 , a layer 31 a is deposited as a variable resistance element 31 , and a layer 32 a is deposited as a second electrode 32 in sequence.
- the upper multilayer body in FIG. 7 is formed.
- a hard mask such as of TEOS, not shown, is formed on top of the multilayer body and used as a mask for first anisotropic etching, so that first trenches 41 are created along the word lines WL as shown in FIG. 8 , and thus, the multilayer body is divided.
- the trenches 41 are filled with a second interlayer insulating film 34 .
- the material for the second interlayer insulating film 34 it is appropriate for the material for the second interlayer insulating film 34 to have good insulating properties and a low capacitance so that it is easy to fill the trenches.
- a leveling process is carried out using CMP or the like, so that extra parts of the second interlayer insulating film 34 are removed and the second electrode 32 are exposed, and thus a block body is formed.
- FIG. 9 shows the block body after the leveling process.
- FIG. 10 shows the state after this step.
- a second etching process is carried out in the direction of the columns L/S.
- second trenches 42 are created along the bit lines BL, which are perpendicular to the word lines WL, as shown in FIG. 11 , and at the same time, memory cells MC in pillar form are separately formed at cross points between the word lines WL and the bit lines BL in a self-aligned manner.
- the spaces are filled with the third interlayer insulating film 35 , and the third interlayer insulating film 35 is leveled, so that a cross point type memory cell layer can be formed as shown in FIG. 12 .
- solid films are layered on top of each other and patterned twice for L/S, which are perpendicular to each other, and thus, cells are formed at cross points and aligned with wires in a self-aligned manner.
- a protective film 51 of an oxide film may be formed in the first trenches 41 after the first etching process and before the trenches are filled with the second interlayer insulating film 34 .
- a protective film of an oxide film may be formed in the second trenches 42 after the second etching process and before the trenches are filled with the third interlayer insulating film 35 .
- an oxide of a so-called rare earth element such as Cr, W or V, can be used for the oxide films.
- the protective film 51 can be formed so that the resistance value can be optimized at the time of setting, and the current leaking through the side walls of the metal oxide films can be reduced.
- the data retaining properties can be improved.
- the memory cells have a structure where wires, barrier metals, non-ohmic elements such as diodes, first electrodes, variable resistance elements, second electrodes and wires are layered in sequence from the bottom layer up in all of the memory cell layers, as shown in FIG. 3 .
- variable resistance elements VR are layered above the non-ohmic elements NO, and therefore, the variable resistance elements VR have a smaller area in a cross section.
- the cell current can be made smaller, so that the power consumption can be reduced.
- the non-ohmic elements NO are layered beneath the variable resistance elements VR, the non-ohmic elements NO have a greater area in a cross section, so that a current in the forward direction is higher and the maximum value of the capacitance for the current is higher.
- the variable resistance elements VR are layered beneath the non-ohmic elements NO, the cell current is greater, and the switching probability and the durability can be expected to increase.
- the diodes are smaller in size, and therefore, the current flowing in the opposite direction through the diodes can be reduced.
- the order of the layers in the memory cells is the same in different layers of the semiconductor memory having a multilayer structure, and thus, it is possible to reduce inconsistency in the properties of the variable resistance elements VR and the non-ohmic elements NO between different layers.
- at least one of an on-cell current, an off-cell current, an on-cell resistance, and an off-cell resistance of the memory cells being included in the different layers can be made substantially the same.
- a nonvolatile memory having a memory cell array with a multilayer structure in the case where word lines WL, which are first wires, and bit lines BL, which are second wires, are shared by the memory cell layers according to a second embodiment of the present invention is described below.
- a resist pattern for word lines WL is formed through photolithography, in order to form word lines WL as damascene wires after the first interlayer insulating film 25 is formed. After that, the oxide film in the parts where there is no resist is etched, so that first trenches 141 extending in the direction of rows, which is the first direction, are created.
- the created first trenches 141 are filled with a wire material that becomes a first metal 27 , such as TiN or W.
- a wire material that becomes a first metal 27 such as TiN or W.
- the top surface of the first interlayer insulating film 25 and the first metal 27 is leveled through CMP.
- word lines WL are formed so as to extend in the direction of rows.
- layers 28 b, 29 b, 30 b, 31 b and 32 b are sequentially deposited on the top surface of the first interlayer insulating film 25 and the first metal 27 , which are leveled in the step in FIG. 15 , as a barrier metal 28 , non-ohmic elements 29 , which are first elements, first electrodes 30 , variable resistive elements 31 , which are second elements, and second electrodes 32 .
- the non-ohmic elements 29 are PN junction diodes made of polysilicon (p-Si) doped in-situ having a P type semiconductor (semiconductor of a first conductivity type) and an N type semiconductor (semiconductor of a second conductivity type) from the bottom layer up.
- p-Si polysilicon
- a resist pattern is formed through photolithography, so that memory cells can be formed at cross points between the word lines WL (first metal 27 ) and the bit lines BL (second metal 36 ) to be formed afterward.
- anisotropic etching is carried out, and the etched portions have such a depth as to hit the bottom of the layer 28 a, so that memory cells MC are formed in pillar form.
- a second interlayer insulating film 134 is layered so as to cover the exposed first interlayer insulating film 25 , the first metal 27 and the memory cells MC.
- the second interlayer insulating film 134 is deposited up to the same height as the bit lines BL, which is formed on the top surface of the second electrodes 32 in a later process.
- bit lines BL is formed through photolithography in order to form bit lines BL as damascene wires after the second interlayer insulating film 134 is deposited. After that, the oxide film in parts where there is no resist is etched, so that the top surface of the second electrodes 32 is exposed. As a result, second trenches 142 extending in the direction of columns, which is the second direction, are created.
- the second trenches 142 are filled with a wire material that becomes the second metal 36 , such as TiN or W, after which the top surface of the second interlayer insulating film 134 and the second metal 36 is leveled through CMP. As a result, bit lines BL extending in the direction of columns are formed.
- a wire material that becomes the second metal 36 such as TiN or W
- the second interlayer insulating film 134 is deposited and then CMP is carried out so that the second interlayer insulating film is leveled.
- a stopper for CMP may be deposited on top of the upper electrodes.
- an interlayer insulating film for forming damascene wires is deposited, a pattern for photolithography is formed, a material for bit lines BL is deposited, and CMP is carried out, so that bit lines BL are formed.
- FIG. 20 is a cross-sectional view showing part of a memory cell array manufactured in accordance with the above-described process in the direction of columns.
- memory cells MC formed at cross points between the word lines WLj and bit lines BLi have a structure where an electrode EL 1 , a diode made of a P type semiconductor/N type semiconductor, which is a non-ohmic element NO, an electrode EL 2 , a variable resistance element VR and an electrode EL 3 are layered in sequence from the bottom layer up.
- memory cells MCโฒ formed at cross points between the bit lines BLi and word lines WLj+i in the upper layer have the same multilayer structure as the memory cells MC, except that a P type semiconductor is layered on top of an N type semiconductor.
- the upper and lower electrodes EL 3 and EL 2 for the variable resistance element VR can be switched in the same manner. In this case, the materials and the thicknesses of the upper and lower electrodes of the lower memory cell MC and the upper memory cell MCโฒ can be switched.
- the P type semiconductor and the N type semiconductor for the diodes are layered in the opposite order between the upper and lower layers, and as a result, two adjacent memory cell layers can share one wire (bit line BLi in the case in FIG. 20 ) without changing the basic multilayer structure of the memory cell layers.
- FIG. 29 is a cross-sectional view showing part of a memory cell array having a mirror structure with a word line WL or a bit line BL at the center as a comparative example.
- the memory cells MC formed at cross points between word lines WLj and bit lines BLi are the same as in the case of the present embodiment shown in FIG. 20 .
- the memory cells MCโฒ have a multilayer structure layered in the opposite order to the memory cells MC. That is to say, an electrode EL 3 , a variable resistance element VR, an electrode EL 2 , a diode made of an N type semiconductor/P type semiconductor which is a non-ohmic element NO, and an electrode EL 1 are layered from the bottom layer up.
- the memory cells MC In the case where memory cells MC are formed through etching, the memory cells usually have a tapered form where the area in a cross section becomes gradually smaller from the bottom layer towards the top layer.
- diodes-variable resistance elements VR and variable resistance elements VR-diodes alternate layer by layer in the comparative example, and therefore, the properties of the memory cells are inconsistent between memory cell layers.
- variable resistance elements VR and the non-ohmic elements are layered in the same order for all of the memory cell layers, and therefore, the variable resistance elements and the non-ohmic elements have the same size in all of the memory cells, and thus, the inconsistency in the properties between the memory cell layers can be reduced, as in the first embodiment.
- the variable resistance elements VR are provided in the upper layer, the cell current that flows at the time of switching can be small, because of the dependency of the cell current on the size during the setting/resetting operation, and thus, the power consumption can be reduced.
- the switching probability and the durability can be expected to increase.
- the size of the diodes is relatively large, and therefore, the current flowing through the diodes in the forward direction can be increased, and as a result, the withstand voltage of the diodes can be increased.
- the variable resistance elements VR are provided in the lower layer, the cell current can be increased, and the switching probability and the durability can be expected to increase.
- the size of the diodes is small, and therefore, the current flowing through the diodes in the backward direction can be reduced.
- variable resistance elements are layered in the layer above the non-ohmic elements (first elements), for example the diodes, as in the above description, in the case where non-ohmic elements (second elements) are layered in the layer above the variable resistance elements (first elements) instead, the inconsistency in the properties of the memory cells between the memory cell layers can be reduced. In this case, the area of the variable resistance elements is large in a cross section, and the switching probability can be increased.
- FIGS. 22 to 27 show the process for a nonvolatile memory in this case.
- the steps up to the layering of the layer 36 a as a second metal 36 are the same as in the process according to the first embodiment in FIGS. 7 to 10 , except that the layer 33 a, which becomes a stopper 33 , is inserted between the layer 32 a, which becomes a second electrode 32 , and the layer 36 a, which becomes a second metal 36 .
- the stopper 33 helps to detect the completion of CMP.
- layers 28 c, 29 c, 30 c, 31 c, 32 c and 33 c are deposited in sequence on the top surface of the layer 36 a, which becomes the second metal 36 , as the barrier metal 28 โฒ of the memory cells MCโฒ in the upper memory cell layer, the non-ohmic elements 29 โฒ, the first electrodes 30 โฒ, the variable resistance elements 31 โฒ, the second electrodes 32 โฒ and the stopper 33 โฒ, respectively.
- a second etching process for L/S is carried out, so that the etched portion hits the bottom surface of the layer 28 a, which becomes a barrier metal 28 , in the direction of columns.
- second trenches 242 are created along the bit lines BLi, which are perpendicular to the word lines Wlj, and at the same time, separate memory cells MC in pillar form are formed in the lower layer at cross points between the word lines WLj and the bit lines BLi in a self-aligned manner.
- the second trenches 242 are filled with a third interlayer insulating film 235 , and the third interlayer insulating film 235 is leveled.
- a layer 27 c is deposited on the top surface of the leveled layer 33 c and the third interlayer insulating film 235 as a third metal 27 โฒ.
- the third etching process is carried out so as to have such a depth that the etched portions hit the bottom surface of the layer 28 c in the direction of rows.
- third trenches 243 are created along the word lines WLj+1, which are perpendicular to the bit lines BLi, and at the same time, separate memory cells MCโฒ in pillar form are formed in the upper layer at cross points between the bit lines BLi and the word lines WLj+ 1 in a self-aligned manner.
- the third trenches 243 are filled with a fourth interlayer insulating film 34 โฒ, and the fourth interlayer insulating film 34 โฒ is leveled.
- a non-volatile memory having two memory cell layers can be manufactured.
- deposition of a metal layer and a memory cell material, anisotropic etching in the direction of rows, deposition of an interlayer insulating film, deposition of a metal layer and a memory cell material, anisotropic etching in the direction of columns and deposition of an interlayer insulating film can be repeated after the process up to deposition of the layer 27 c as the third metal layer 27 in FIG. 24 , so that a memory cell array with a multilayer structure can be manufactured.
- FIG. 28 shows part of the memory cell array manufactured in accordance with the above-described process; the left and right diagrams are cross-sectional views in the direction of columns and the direction of rows, respectively.
- memory cells MC are provided in the lower layer at cross points between the word lines WLj and bit lines BLi, and memory cells MCโฒ are provided in the upper layer at cross points between the bit lines BLi and word lines WLj+ 1 .
- the memory cells MC have a structure where an electrode EL 1 , a P type semiconductor/N type semiconductor for a diode, which is a non-ohmic element NO, an electrode EL 2 , a variable resistance element VR, an electrode EL 3 and a stopper ST are layered in this order from the word line WLj to the bit line BLi.
- the memory cells MCโฒ have a structure where an electrode EL 1 , an N type semiconductor/P type semiconductor for a diode, which is a non-ohmic element NO, an electrode EL 2 , a variable resistance element VR, an electrode EL 3 and a stopper ST are layered in this order from the bit line BLi to the word line WLj+1.
- an electrode EL 1 an N type semiconductor/P type semiconductor for a diode, which is a non-ohmic element NO
- an electrode EL 2 a variable resistance element VR
- an electrode EL 3 and a stopper ST are layered in this order from the bit line BLi to the word line WLj+1.
- the upper and lower electrodes EL 3 and EL 2 for the variable resistance element VR can be switched.
- the materials and the thicknesses of the upper and lower electrodes of the lower memory cell MC and the upper memory cell MCโฒ can be switched.
- the L/S process in FIG. 22 is carried out on two layers at the same time, and therefore, the memory cells MC and the memory cells MCโฒ have a tapered form where the area becomes continuously smaller from the bottom surface of the memory cells MC towards the top surface of the memory cells MCโฒ in a cross section.
- variable resistance elements VR are layered above the diodes, which are non-ohmic elements NO, in all of the memory cell layers, and therefore, the area of the diodes is greater than the area of the variable resistance elements VR in a cross section.
- the current that flows through the variable resistance elements VR is small, so that the power consumption can be reduced, and at the same time, the maximum value of the current that flows through the diodes in the forward direction can be increased.
- the above-described L/S process is carried out every two layers, and therefore, there is a possibility that the properties may be different between even-numbered memory cell layers and odd-numbered memory cell layers. Even in this case, however, it is possible for the area in a cross section at the same height to be approximately the same between even-numbered memory cell layers and odd-numbered memory cell layers, and therefore, the inconsistency in the memory cell properties can be reduced between even-numbered memory cell layers and between odd-numbered memory cell layers.
- at least one of an on-cell current and an off cell current of the memory cells being included in at least one of the even-numbered memory cell layers and the odd-numbered memory cell layers can be made substantially the same.
- at least one of an on-cell resistance and an off-cell resistance of the memory cells being included in at least one of the even-numbered memory cell layers and the odd-numbered memory cell layers can be made substantially the same.
- the cell current that flows at the time of switching can be reduced, because of the dependency of the cell current on the size during the setting and resetting operation, and thus, the power consumption can be reduced, as in the above-described embodiments.
- the switching probability and durability can be expected to increase.
- the cell current can be increased, and the switching probability and durability can be expected to increase.
- the size of the diodes is small, the current flowing through the diodes in the backward direction can be reduced.
- the present invention is not limited to memory cells made of a variable resistance element and a diode, as described above, and can be applied to various memory devices having a cross point type multilayer structure, such as phase variable memory elements, MRAM elements, PFRAM and the like.
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KR20100106212A (en) | 2010-10-01 |
US20100237320A1 (en) | 2010-09-23 |
KR101128620B1 (en) | 2012-03-26 |
US8507889B2 (en) | 2013-08-13 |
JP2010225741A (en) | 2010-10-07 |
TW201104939A (en) | 2011-02-01 |
TW201407842A (en) | 2014-02-16 |
TWI533485B (en) | 2016-05-11 |
TWI425687B (en) | 2014-02-01 |
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