USRE36305E - Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer - Google Patents

Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer Download PDF

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USRE36305E
USRE36305E US08/687,785 US68778596A USRE36305E US RE36305 E USRE36305 E US RE36305E US 68778596 A US68778596 A US 68778596A US RE36305 E USRE36305 E US RE36305E
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layer
conformal
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void
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Charles H. Dennison
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Definitions

  • the invention relates in general to a method for fabricating submicron lines on wafers and sharp tips for field effect device and, in particular, to the method for forming a close-tolerance line or sharp tip in a semiconductor wafer substrate or layer using a loose tolerance trench, or well.
  • the present invention is a novel method for producing close-tolerance sharp tips or narrow lines in a semiconductor wafer substrate or layer where the fabrication equipment, i.e., photolithography apparatus, is only capable of producing a larger, looser tolerance line.
  • the first step of the method is to fabricate a trench in a first layer over the substrate using the looser tolerance photolithography or other fabrication equipment available.
  • the next step is to deposit a non-conformal material over the wider line and substrate, thereby forming a void with a uniform, close-tolerance width regardless of variations in the previously formed trench.
  • CMP chemical mechanical polish
  • etch-resist conformal material is then deposited over the first layer and in the void.
  • the conformal material is then planarized leaving material only in the void to form a mask of a predetermined close-tolerance width.
  • the walls of the non-conformal material and the first layer are then etched away, leaving a ridge or wall under the mask of the same close-tolerance thickness as the void, disposed above the original wafer substrate in a position where a new line of close tolerance is to be formed at the predetermined desired position along the substrate.
  • This formed, two-layer ridge or wall then acts as a hard mask for subsequent patterning of the substrate by etching or other fabrication techniques.
  • the ridges or lines formed in this manner can be in the range of 0.1 to 0.15 ⁇ m.
  • the same process can be used to form a sharp, pointed tip such as that desired for high resolution field emission tips used in cold cathode emitters that are utilized in the field emitter display devices.
  • the tip mask is formed as a cylindrical vertical pillar in lieu of a line or linear trench.
  • FIG. 1 is a perspective view of a submicron line formed by the present inventive method
  • FIG. 2 is a perspective view of a sharp tip formed by the present method
  • FIG. 3 is a partial side section view of an integrated circuit (IC) semiconductor die
  • FIG. 4 is a partial side section view of an upper section the IC semiconductor die of FIG. 3 after etching
  • FIG. 5 is a partial side section view of an IC semiconductor die of FIG. 4 after non-conformal layering
  • FIG. 6 is a partial side section view of an IC semiconductor die of FIG. 5 after planarizing
  • FIG. 7 is a partial side section view of an IC semiconductor die of FIG. 6 after conformal layering
  • FIG. 8 is a partial side section view of an IC semiconductor die of FIG. 7 after a second planarizing of the conformal layer;
  • FIG. 9 is a partial side section view of an IC semiconductor die of FIG. 8 after a selective etching
  • FIG. 10 is a partial side section view of an IC semiconductor die of FIG. 9 after a second selective etching
  • FIG. 11 is a partial side section view of an IC semiconductor die of the final submicron line
  • FIG. 12 is a partial side section view of an IC semiconductor die having a pair of trenches of differing widths filled with a non-conformal layer;
  • FIG. 13 is the partial side section view of an IC semiconductor die having a pair of trenches of differing widths of FIG. 12 now filled with a non-conformal layer of deeper depth;
  • FIG. 14 is a graph of void width as a function of trench width
  • FIG. 15 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches
  • FIG. 16 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches after planarization;
  • FIG. 17 is a partial side section view of an IC semiconductor die having different width lines
  • FIG. 18 is a partial section perspective view of a sharp point "mask” process.
  • FIG. 19 is a partial section perspective view of a completed sharp point.
  • the final submicron line 10 fabricated by this inventive process can be seen in FIG. 1.
  • This line which may be used as a gate in a final integrated circuit (IC) device and can have a width dimension of 0.1 ⁇ m as at 12 which is significantly narrower than the width available by current photolithography methods.
  • the line has been fabricated in substrate 14 and has a gate oxide layer 16 under the line 10.
  • a sharp point 20 may be seen in FIG. 2 fabricated by the same basic process.
  • a sharp point is needed in the fabrication of a field emitter device having a cold cathode (point) 20, a control grid, and an anode (not shown) on a substrate 22.
  • the process for forming the point 20 is similar to the submicron line process except for the shape, i.e., a circular pyramid 20 in lieu of a line 10 (FIG. 1).
  • FIG. 3 indicates the typical beginning steps in IC semiconductor wafer.
  • the substrate 14 has a typical gate oxide layer 16 formed over substrate 14 and a typical gate polysilicon layer 24 deposited over the oxide 16.
  • a mask oxide layer 28 is deposited over the gate polysilicon layer 24.
  • FIG. 4 shows the results of the photolithography method of forming a trench through a photoresist layer 30 and the mask oxide layer 28 by an etching process. After etching, the photoresist layer 30 is removed by a stripping process. The line or trench 32 is then filled by depositing a non-conformal material 34 as in FIG.
  • a tear-drop shaped void or gap 36 at the center of line 32.
  • a good material for this layer would be plasma silicon oxide (SiO 2 ) or plasma silicon nitride (Si 3 N 4 ). Plasma oxide will be used in the described process flow.
  • the depth of layer 34 is controlled and is dependent on the width and depth of line 32. As shown, a typical void width is about 0.1 ⁇ m as at 38 when the depth of the non-conformal layer is 0.45 ⁇ m as at 40.
  • a key aspect of this invention is the ability to form a void of consistent width 38 without being affected by minor variations in the width of gap 32 which is due to the physical limitations of the photolithography and etch processes.
  • a conformal mask material 42 is deposited and may consist of any conformal material capable of having a differing plasma etch rate than layer 34.
  • polysilicon is deposited by a low pressure chemical vapor deposition (LPCVD) process and is representative of such conformal material.
  • a second chemical mechanical polishing is performed to remove all the conformal material 42 except that within void 36, as illustrated in FIG. 8.
  • An anisotropic oxide etch simultaneously etches both the plasma oxide 34 and masking oxide 28 down to gate polysilicon layer 24, as in FIG. 9.
  • a plasma polysilicon etch can be done to pattern the underlying oxide 16 and gate polysilicon 24 to form the submicron (0.1 ⁇ m) line as illustrated in FIG. 10.
  • the conformal polysilicon layer 42 is simultaneously etched away in this polysilicon etch step.
  • FIG. 11 illustrates the submicron gate material 24 and gate oxide 16 over substrate 14 after typical ion implantation at 44. The remaining steps in the process are dependent on the type of device being fabricated.
  • Trench lines 50 and 52 have a typical width dimension of 0.4 ⁇ m and 0.6 ⁇ m, respectively, and the deposition of non-conformal layer 34 to a depth of about 0.3 ⁇ m is shown at 54. Void width at 56 is shown about 0.1 ⁇ m while void 58 at this point is about 0.2 ⁇ m.
  • FIG. 13 shows the effect of continuing the deposition of layer 34 to about 0.45 ⁇ m as at 60.
  • This deposition to a depth of 0.45 ⁇ m at 60 has resulted in closing the void at the top section 61 and narrowing the void at 58 to a new void width of 0.1 ⁇ m at 62, thereby matching the void width 56.
  • the graph of FIG. 14 is used to illustrate the variation of void width as a function of trench width.
  • Using a conformal material would result in linear relationship at 64.
  • the ideal response would be a flat line as at 66, and a desired response or relationship is shown at 68 which indicates about a 0.02 ⁇ m change in void width for a 0.2 ⁇ m change in trench width as at 70.
  • the line 68 would curve upward so as to be parallel to line 64 as at 71 (FIG. 14).
  • the non-conformal layer 74 is above two significantly different width trenches 76 and 78.
  • the cross-section appears as at FIG. 16.
  • a final gate material 84 cross-section shown in FIG. 17 would have a narrow gate line 86 and wider gate line 88 after etching down to gate oxide 89.
  • the final mask width can be controlled by careful control of the non-conformal mask material depths as at 72' (FIG. 15), i.e., the deeper the mask depth deposited, the narrower the final gap as at 91 (FIG. 15).
  • FIG. 18 discloses the fabrication process to make a sharp point for a cold cathode or similar device as shown in FIG. 19.
  • polysilicon layer 90 over the substrate 92 and a non-conformal circular plug 94 in a well 95 in lieu of a trench or line (FIGS. 6-8) and the hard mask TEOS 96 or other material sets within well 95 surrounded by the plug 94.
  • Isotropic etching of the substrate 92 and mask and plug removal would expose the cone-shaped sharp point as at 98 (FIG. 19) of a very small diameter, on the order of 0.1 micron.
  • a cylindrical pillar could also be formed by use of an anisotropic etch process.

Abstract

A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography techniques. The method can also be used to create sharp emission tips for field effect display devices.

Description

FIELD OF THE INVENTION
The invention relates in general to a method for fabricating submicron lines on wafers and sharp tips for field effect device and, in particular, to the method for forming a close-tolerance line or sharp tip in a semiconductor wafer substrate or layer using a loose tolerance trench, or well.
BACKGROUND OF THE INVENTION
Often times in semiconductor wafer fabrication, it is desirable to fabricate a line having closer tolerances than photolithography or other line-forming methods. These close-tolerance lines are utilized for field effect devices and other integrated circuit devices produced on semiconductor wafers. In the past, it has been necessary to either purchase expensive precision fabrication equipment or relax the tolerances. Accordingly, it would be desirable to have a method for fabricating a close-tolerance line or sharp tip without requiring close-tolerance precise fabrication equipment. One example of use of this line would be for a narrow gate on a MOS FET device.
SUMMARY OF THE INVENTION
The present invention is a novel method for producing close-tolerance sharp tips or narrow lines in a semiconductor wafer substrate or layer where the fabrication equipment, i.e., photolithography apparatus, is only capable of producing a larger, looser tolerance line. The first step of the method is to fabricate a trench in a first layer over the substrate using the looser tolerance photolithography or other fabrication equipment available. The next step is to deposit a non-conformal material over the wider line and substrate, thereby forming a void with a uniform, close-tolerance width regardless of variations in the previously formed trench. Next, a chemical mechanical polish (CMP) process is performed to planarize and expose the close-tolerance width dimension void. An etch-resist conformal material is then deposited over the first layer and in the void. The conformal material is then planarized leaving material only in the void to form a mask of a predetermined close-tolerance width. The walls of the non-conformal material and the first layer are then etched away, leaving a ridge or wall under the mask of the same close-tolerance thickness as the void, disposed above the original wafer substrate in a position where a new line of close tolerance is to be formed at the predetermined desired position along the substrate.
This formed, two-layer ridge or wall then acts as a hard mask for subsequent patterning of the substrate by etching or other fabrication techniques. The ridges or lines formed in this manner can be in the range of 0.1 to 0.15 μm.
In a second embodiment, the same process can be used to form a sharp, pointed tip such as that desired for high resolution field emission tips used in cold cathode emitters that are utilized in the field emitter display devices. In this case, the tip mask is formed as a cylindrical vertical pillar in lieu of a line or linear trench.
Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a submicron line formed by the present inventive method;
FIG. 2 is a perspective view of a sharp tip formed by the present method;
FIG. 3 is a partial side section view of an integrated circuit (IC) semiconductor die;
FIG. 4 is a partial side section view of an upper section the IC semiconductor die of FIG. 3 after etching;
FIG. 5 is a partial side section view of an IC semiconductor die of FIG. 4 after non-conformal layering;
FIG. 6 is a partial side section view of an IC semiconductor die of FIG. 5 after planarizing;
FIG. 7 is a partial side section view of an IC semiconductor die of FIG. 6 after conformal layering;
FIG. 8 is a partial side section view of an IC semiconductor die of FIG. 7 after a second planarizing of the conformal layer;
FIG. 9 is a partial side section view of an IC semiconductor die of FIG. 8 after a selective etching;
FIG. 10 is a partial side section view of an IC semiconductor die of FIG. 9 after a second selective etching;
FIG. 11 is a partial side section view of an IC semiconductor die of the final submicron line;
FIG. 12 is a partial side section view of an IC semiconductor die having a pair of trenches of differing widths filled with a non-conformal layer;
FIG. 13 is the partial side section view of an IC semiconductor die having a pair of trenches of differing widths of FIG. 12 now filled with a non-conformal layer of deeper depth;
FIG. 14 is a graph of void width as a function of trench width;
FIG. 15 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches;
FIG. 16 is a partial side section view of an IC semiconductor die having a non-conformal layer over different width trenches after planarization;
FIG. 17 is a partial side section view of an IC semiconductor die having different width lines;
FIG. 18 is a partial section perspective view of a sharp point "mask" process; and
FIG. 19 is a partial section perspective view of a completed sharp point.
DETAILED DESCRIPTION OF THE INVENTION
The final submicron line 10 fabricated by this inventive process can be seen in FIG. 1. This line which may be used as a gate in a final integrated circuit (IC) device and can have a width dimension of 0.1 μm as at 12 which is significantly narrower than the width available by current photolithography methods. The line has been fabricated in substrate 14 and has a gate oxide layer 16 under the line 10.
In a second embodiment, a sharp point 20 may be seen in FIG. 2 fabricated by the same basic process. A sharp point is needed in the fabrication of a field emitter device having a cold cathode (point) 20, a control grid, and an anode (not shown) on a substrate 22. The process for forming the point 20 is similar to the submicron line process except for the shape, i.e., a circular pyramid 20 in lieu of a line 10 (FIG. 1).
The process for submicron line formation 10 will be described by referring to FIGS. 3-11. FIG. 3 indicates the typical beginning steps in IC semiconductor wafer. The substrate 14 has a typical gate oxide layer 16 formed over substrate 14 and a typical gate polysilicon layer 24 deposited over the oxide 16. A mask oxide layer 28 is deposited over the gate polysilicon layer 24. FIG. 4 shows the results of the photolithography method of forming a trench through a photoresist layer 30 and the mask oxide layer 28 by an etching process. After etching, the photoresist layer 30 is removed by a stripping process. The line or trench 32 is then filled by depositing a non-conformal material 34 as in FIG. 5 which in this inventive process forms a tear-drop shaped void or gap 36 at the center of line 32. A good material for this layer would be plasma silicon oxide (SiO2) or plasma silicon nitride (Si3 N4). Plasma oxide will be used in the described process flow. The depth of layer 34 is controlled and is dependent on the width and depth of line 32. As shown, a typical void width is about 0.1 μm as at 38 when the depth of the non-conformal layer is 0.45 μm as at 40.
After planarizing the non-conformal material 34 by a chemical mechanical polish, the surface and exposed void 36 appears as in FIG. 6. A key aspect of this invention is the ability to form a void of consistent width 38 without being affected by minor variations in the width of gap 32 which is due to the physical limitations of the photolithography and etch processes.
Referring now to FIG. 7, a conformal mask material 42 is deposited and may consist of any conformal material capable of having a differing plasma etch rate than layer 34. For the process flow shown, polysilicon is deposited by a low pressure chemical vapor deposition (LPCVD) process and is representative of such conformal material.
A second chemical mechanical polishing is performed to remove all the conformal material 42 except that within void 36, as illustrated in FIG. 8. An anisotropic oxide etch simultaneously etches both the plasma oxide 34 and masking oxide 28 down to gate polysilicon layer 24, as in FIG. 9. Next, a plasma polysilicon etch can be done to pattern the underlying oxide 16 and gate polysilicon 24 to form the submicron (0.1 μm) line as illustrated in FIG. 10. Also, note that the conformal polysilicon layer 42 is simultaneously etched away in this polysilicon etch step. FIG. 11 illustrates the submicron gate material 24 and gate oxide 16 over substrate 14 after typical ion implantation at 44. The remaining steps in the process are dependent on the type of device being fabricated.
Referring now to FIGS. 12 and 13, the capability to form lines of consistent close-tolerance width in spite of variations in trench width 50,52 is demonstrated. Trench lines 50 and 52 have a typical width dimension of 0.4 μm and 0.6 μm, respectively, and the deposition of non-conformal layer 34 to a depth of about 0.3 μm is shown at 54. Void width at 56 is shown about 0.1 μm while void 58 at this point is about 0.2 μm. FIG. 13 shows the effect of continuing the deposition of layer 34 to about 0.45 μm as at 60. This deposition to a depth of 0.45 μm at 60 has resulted in closing the void at the top section 61 and narrowing the void at 58 to a new void width of 0.1 μm at 62, thereby matching the void width 56.
The graph of FIG. 14 is used to illustrate the variation of void width as a function of trench width. Using a conformal material would result in linear relationship at 64. The ideal response would be a flat line as at 66, and a desired response or relationship is shown at 68 which indicates about a 0.02 μm change in void width for a 0.2 μm change in trench width as at 70. For trench widths over 0.7 μm, the line 68 would curve upward so as to be parallel to line 64 as at 71 (FIG. 14).
Referring to FIGS. 15-17, it is also demonstrated that it is also possible to purposely fabricate wide lines and narrow lines simultaneously by controlling the non-conformal layer depth 72. In this instance, the non-conformal layer 74 is above two significantly different width trenches 76 and 78. When these trenches have the conformal mask material 80 deposited and then planarized down to the polysilicon layer 82, the cross-section appears as at FIG. 16. A final gate material 84 cross-section shown in FIG. 17 would have a narrow gate line 86 and wider gate line 88 after etching down to gate oxide 89. It is noted that for the wider trench widths, the final mask width can be controlled by careful control of the non-conformal mask material depths as at 72' (FIG. 15), i.e., the deeper the mask depth deposited, the narrower the final gap as at 91 (FIG. 15).
The cross-section perspective view of FIG. 18 discloses the fabrication process to make a sharp point for a cold cathode or similar device as shown in FIG. 19. In this case, we have polysilicon layer 90 over the substrate 92 and a non-conformal circular plug 94 in a well 95 in lieu of a trench or line (FIGS. 6-8) and the hard mask TEOS 96 or other material sets within well 95 surrounded by the plug 94. Isotropic etching of the substrate 92 and mask and plug removal would expose the cone-shaped sharp point as at 98 (FIG. 19) of a very small diameter, on the order of 0.1 micron. A cylindrical pillar could also be formed by use of an anisotropic etch process.
It is also possible to fabricate circular gates and anodes surrounding the sharp tip 98 by a similar process.
While preferred embodiments of the invention have been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.

Claims (29)

What is claimed is:
1. A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:
a. depositing a first layer on top of the gate polysilicon layer;
b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm);
c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;
d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;
e. depositing a conformal mask material over the first layer and void;
f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material;
g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.
2. The method of claim 1 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm.
3. The method of claim 1 wherein the first layer is a mask oxide.
4. The method of claim 1 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
5. The method of claim 1 wherein the conformal mask material is polysilicon.
6. The method of claim 2 wherein the width of the submicron line is less than 0.15 μm.
7. A method for fabricating close-tolerance, sharp emission tip on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:
a. depositing a first layer on top of the gate polysilicon layer;
b. forming a loose-tolerance trench in the first layer having a diameter of less than 1 micrometer (μm);
c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;
d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;
e. depositing a conformal mask material over the first layer and void;
f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material;
g. isotropically etching by a photolithography process the first layer and non-conformal material thereby forming the sharp emission tip below the conformal mask material having a lesser diameter than the loose-tolerance well.
8. The method of claim 7 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter.
9. The method of claim 7 wherein the first layer is a mask oxide.
10. The method of claim 7 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
11. The method of claim 7 wherein the conformal mask material is polysilicon.
12. The method of claim 8 wherein the diameter of the sharp emission tip is less than 0.15 μm.
13. A method for fabricating close-tolerance mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:
a. depositing a first layer on top of the gate polysilicon layer;
b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm);
c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;
d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;
e. depositing a conformal mask material over the first layer and void; and then
f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material.
14. The method of claim 13 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm.
15. The method of claim 13 wherein the first layer is a mask oxide.
16. The method of claim 13 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
17. The method of claim 13 wherein the conformal mask material is polysilicon.
18. The method of claim 14 wherein the width of the mask is less than 0.15 μm.
19. A method for fabricating close-tolerance, circular mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:
a. depositing a first layer on top of the gate polysilicon layer;
b. forming a loose-tolerance well in the first layer having a width of less than 1 micrometer (μm);
c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the well, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;
d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;
e. depositing a conformal mask material over the first layer and void; and then
f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material.
20. The method of claim 19 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter.
21. The method of claim 19 wherein the first layer is a mask oxide.
22. The method of claim 19 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
23. The method of claim 19 wherein the conformal mask material is polysilicon. .Iadd.
24. A method for fabricating at least one submicron line on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising:
depositing a first layer on top of the polysilicon layer;
forming a trench in the first layer;
depositing a non-conformal material over the first layer to form a void in the trench;
removing the non-conformal material down to a top surface of the first layer to expose the void;
depositing a conformal mask material over the first layer and void;
removing the conformal mask material above the first layer; and
etching the first layer and non-conformal material..Iaddend..Iadd.25. The method of claim 24 wherein the trench includes a width of less than 1 μm..Iaddend..Iadd.26. The method of claim 24 wherein the trench is between 0.40 μm and 0.7 μm in width..Iaddend..Iadd.27. The method of claim 24 wherein the first layer is a mask oxide..Iaddend..Iadd.28. The method of claim 24 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.29. The method of claim 24 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.30. The method of claim 24 wherein the conformal mask material is polysilicon..Iaddend..Iadd.31. The method of claim 24 wherein
the submicron line is less than 0.15 μm in width..Iaddend..Iadd.32. The method of claim 24 wherein the void includes a tear-drop shaped cross section..Iaddend..Iadd.33. The method of claim 24 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.34. The method of claim 24 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.35. The method of claim 24 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.36. A method for fabricating at least one sharp emission tip on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising:
depositing a first layer on top of the polysilicon layer;
forming a well in the first layer;
depositing a non-conformal material over the first layer to form a void in the well;
removing the non-conformal material down to a top surface of the first layer to expose the void;
depositing a conformal mask material over the first layer and void;
removing the conformal mask material above the first layer; and
etching the first layer and non-conformal material..Iaddend..Iadd.37. The method of claim 36 wherein the well includes a diameter of less than 1 μm..Iaddend..Iadd.38. The method of claim 36 wherein the well is between 0.40 μm and 0.7 μm in diameter..Iaddend..Iadd.39. The method
of claim 36 wherein the first layer is a mask oxide..Iaddend..Iadd.40. The method of claim 36 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.41. The method of claim 36 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.42. The method of claim 36 wherein the conformal mask material is polysilicon..Iaddend..Iadd.43. The method of claim 36 wherein the sharp emission tip is less than 0.15 μm in diameter..Iaddend..Iadd.44. The method of claim 36 wherein the void includes a tear-drop shape..Iaddend..Iadd.45. The method of claim 36 wherein removing the non-conformal mask material down to a top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.46. The method of claim 36 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.47. The method of claim 36 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.48. The method of claim 36 wherein etching the first layer and non-conformal material
includes an isotropic etch..Iaddend..Iadd.49. A method for fabricating a mask on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising:
depositing a first layer on top on the polysilicon layer;
forming an opening in the first layer;
depositing a non-conformal material over the first layer to form a void in the opening;
removing the non-conformal material down to a top surface of the first layer to expose the void;
depositing a conformal mask material over the first layer and void; and
removing the conformal mask material above the first layer..Iaddend..Iadd.50. The method of claim 49 wherein the first layer is a mask oxide..Iaddend..Iadd.51. The method of claim 49 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.52. The method of claim 49 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.53. The method of claim 49 wherein the conformal mask material is polysilicon..Iaddend..Iadd.54. The method of claim 49 wherein the opening includes a trench..Iaddend..Iadd.55. The method of claim 54 wherein the trench is less than 1 μm in width..Iaddend..Iadd.56. The method of claim 54 wherein the trench is between 0.40 μm and 0.7 μm in width..Iaddend..Iadd.57. The method of claim 54 wherein the mask is less than 0.15 μm in width..Iaddend..Iadd.58. The method of claim 49 wherein
the opening includes a well..Iaddend..Iadd.59. The method of claim 58 wherein the well is less than 1 μm in diameter..Iaddend..Iadd.60. The method of claim 58 wherein the well is between 0.40 μm and 0.7 μm in diameter..Iaddend..Iadd.61. The method of claim 58 wherein the mask is less than 0.15 μm in diameter..Iaddend..Iadd.62. The method of claim 49 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.63. The method of claim 49 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.64. A method for fabricating a submicron structure on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising:
depositing a first layer on top of the polysilicon layer;
forming an opening in the first layer;
depositing a non-conformal material over the first layer to form a void in the trench;
removing the non-conformal material down to a top surface of the first layer to expose the void;
depositing a conformal mask material over the first layer and void;
removing the conformal mask material above the first layer; and
etching the first layer and non-conformal material..Iaddend..Iadd.65. The method of claim 64 wherein the first layer is a mask oxide..Iaddend..Iadd.66. The method of claim 64 wherein the non-conformal material is selected from the group consisting of silicon oxide and
silicon nitride..Iaddend..Iadd.67. The method of claim 64 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.68. The method of claim 64 wherein the conformal mask material is polysilicon..Iaddend..Iadd.69. The method of claim 64 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.70. The method of claim 64 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.71. The method of claim 64 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.72. The method of claim 64 wherein etching the first layer and non-conformal material includes an isotropic etch..Iaddend.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274469B1 (en) * 2000-01-26 2001-08-14 Advanced Micro Devices, Inc. Process using a plug as a mask for a gate
US6342438B2 (en) 1998-11-06 2002-01-29 Advanced Micro Devices, Inc. Method of manufacturing a dual doped CMOS gate
US20030104702A1 (en) * 2001-12-04 2003-06-05 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536193A (en) 1991-11-07 1996-07-16 Microelectronics And Computer Technology Corporation Method of making wide band gap field emitter
US5675216A (en) 1992-03-16 1997-10-07 Microelectronics And Computer Technololgy Corp. Amorphic diamond film flat field emission cathode
US5543684A (en) 1992-03-16 1996-08-06 Microelectronics And Computer Technology Corporation Flat panel display based on diamond thin films
US5686791A (en) 1992-03-16 1997-11-11 Microelectronics And Computer Technology Corp. Amorphic diamond film flat field emission cathode
US5449970A (en) 1992-03-16 1995-09-12 Microelectronics And Computer Technology Corporation Diode structure flat panel display
CN1134754A (en) 1993-11-04 1996-10-30 微电子及计算机技术公司 Methods for fabricating flat panel display systems and components
US5567553A (en) * 1994-07-12 1996-10-22 International Business Machines Corporation Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures
US6190829B1 (en) 1996-09-16 2001-02-20 International Business Machines Corporation Low “K” factor hybrid photoresist
US6114082A (en) 1996-09-16 2000-09-05 International Business Machines Corporation Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same
US6054807A (en) * 1996-11-05 2000-04-25 Micron Display Technology, Inc. Planarized base assembly and flat panel display device using the planarized base assembly
US6218704B1 (en) 1997-05-07 2001-04-17 International Business Machines Corporation ESD protection structure and method
US5882967A (en) * 1997-05-07 1999-03-16 International Business Machines Corporation Process for buried diode formation in CMOS
US5861330A (en) * 1997-05-07 1999-01-19 International Business Machines Corporation Method and structure to reduce latch-up using edge implants
US5981148A (en) * 1997-07-17 1999-11-09 International Business Machines Corporation Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby
US5972570A (en) * 1997-07-17 1999-10-26 International Business Machines Corporation Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
US5922515A (en) * 1998-02-27 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Approaches to integrate the deep contact module
US6227943B1 (en) 1998-05-01 2001-05-08 International Business Machines Corporation Method and system for pre-cleaning and post-cleaning deposited metal
US6184041B1 (en) 1998-05-13 2001-02-06 International Business Machines Corporation Fused hybrid resist shapes as a means of modulating hybrid resist space width
US6229325B1 (en) 1999-02-26 2001-05-08 Micron Technology, Inc. Method and apparatus for burn-in and test of field emission displays
US6843697B2 (en) * 1999-06-25 2005-01-18 Micron Display Technology, Inc. Black matrix for flat panel field emission displays
US6566219B2 (en) 2000-09-22 2003-05-20 Infineon Technologies Ag Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) * 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
JP2006186562A (en) * 2004-12-27 2006-07-13 Sanyo Electric Co Ltd Video signal processor
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7429536B2 (en) * 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) * 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US8123968B2 (en) * 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) * 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7572572B2 (en) * 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7538858B2 (en) * 2006-01-11 2009-05-26 Micron Technology, Inc. Photolithographic systems and methods for producing sub-diffraction-limited features
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7902074B2 (en) * 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) * 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) * 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) * 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
KR100790998B1 (en) 2006-10-02 2008-01-03 삼성전자주식회사 Method of forming pad pattern using self-align double patterning method, and method of forming contact hole using self-align double patterning method
US8129289B2 (en) * 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) * 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
CN101834136A (en) * 2010-05-12 2010-09-15 上海宏力半导体制造有限公司 Method for improving silicide layer on surface of emitting electrode of bipolar transistor
FR2963156B1 (en) * 2010-07-22 2012-08-31 St Microelectronics Grenoble 2 METHOD FOR MAKING TWO IMBRITIC PATTERNS ON A SUBSTRATE
US8822342B2 (en) * 2010-12-30 2014-09-02 Globalfoundries Singapore Pte. Ltd. Method to reduce depth delta between dense and wide features in dual damascene structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673435A (en) * 1979-11-20 1981-06-18 Nec Corp Manufacture of semiconductor device
JPS59155929A (en) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp Forming method of minute pattern
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
US4671970A (en) * 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
US5032491A (en) * 1987-08-20 1991-07-16 Kabushiki Kaisha Toshiba Method of forming a fine pattern

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673435A (en) * 1979-11-20 1981-06-18 Nec Corp Manufacture of semiconductor device
JPS59155929A (en) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp Forming method of minute pattern
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
US4671970A (en) * 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
US5032491A (en) * 1987-08-20 1991-07-16 Kabushiki Kaisha Toshiba Method of forming a fine pattern

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Van Zant, Microchip Fabrication A Practical Guide to Semiconductor Processing , McGraw Hill Publishing Company, pp. 88 89, 162 163, 222 223, 308 309, 1990. *
Van Zant, Microchip Fabrication--A Practical Guide to Semiconductor Processing, McGraw-Hill Publishing Company, pp. 88-89, 162-163, 222-223, 308-309, 1990.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342438B2 (en) 1998-11-06 2002-01-29 Advanced Micro Devices, Inc. Method of manufacturing a dual doped CMOS gate
US6274469B1 (en) * 2000-01-26 2001-08-14 Advanced Micro Devices, Inc. Process using a plug as a mask for a gate
US20030104702A1 (en) * 2001-12-04 2003-06-05 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices
US6875689B2 (en) * 2001-12-04 2005-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of patterning lines in semiconductor devices

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