US8283230B2 - Fabrication method of self-aligned trenched power semiconductor structure - Google Patents

Fabrication method of self-aligned trenched power semiconductor structure Download PDF

Info

Publication number
US8283230B2
US8283230B2 US12/797,898 US79789810A US8283230B2 US 8283230 B2 US8283230 B2 US 8283230B2 US 79789810 A US79789810 A US 79789810A US 8283230 B2 US8283230 B2 US 8283230B2
Authority
US
United States
Prior art keywords
self
polysilicon
aligned
power semiconductor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/797,898
Other versions
US20110306194A1 (en
Inventor
Chun Ying Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GREAT POWER SEMICONDUCTOR CORP
Original Assignee
GREAT POWER SEMICONDUCTOR CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GREAT POWER SEMICONDUCTOR CORP filed Critical GREAT POWER SEMICONDUCTOR CORP
Priority to US12/797,898 priority Critical patent/US8283230B2/en
Assigned to GREAT POWER SEMICONDUCTOR CORP. reassignment GREAT POWER SEMICONDUCTOR CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YEH, CHUN YING
Publication of US20110306194A1 publication Critical patent/US20110306194A1/en
Application granted granted Critical
Publication of US8283230B2 publication Critical patent/US8283230B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Definitions

  • This invention relates to a fabrication method of a trenched power semiconductor structure, and more particularly relates to a fabrication method of a self-aligned trenched power semiconductor structure.
  • FIGS. 1A to 1C are schematic views showing a fabrication process of a typical trenched power semiconductor structure.
  • a gate trench 120 is formed in a silicon substrate 110 .
  • a gate oxide layer 130 is formed to line the inner surface of the gate trench 120 .
  • a polysilicon layer is deposited on the upper surface of the silicon substrate 110 and an etching back step follows to remove the unwanted portion of the polysilicon layer so as to leave a polysilicon gate 140 in the gate trench 120 .
  • a body implantation step is carried out to implant dopants into the silicon substrate 110 so as to form a body 150 surrounding the gate trench 120 .
  • a source implantation step is carried out to implant dopants of different conductive type into the body 150 so as to form the source region 160 in the upper portion of the body 150 .
  • a dielectric layer 170 is deposited on the exposed surfaces of the silicon substrate 110 and fills the gate trench 120 .
  • a contact window 180 for exposing the source region 160 is formed in the dielectric layer 170 and the body 150 by using lithographic and etching processes.
  • the shrinkage of cell dimension of the trenched power semiconductor device is restricted by lithographic limitations. That is, due to the limitations of critical dimension for trench and contact window as well as tolerance required for alignment control, the distance between the gate trench 120 and the contact window 180 should be great enough to prevent the problems such as leakage current, variation of threshold voltage, or decreasing of avalanche ruggedness.
  • a fabrication method of a self-aligned power semiconductor structure comprises the steps of: a) forming a trenched polysilicon gate in a silicon substrate; b) forming a self-aligned polysilicon extending structure, extended upward from the trenched polysilicon gate, a width of the self-aligned polysilicon extending structure being smaller than that of the trenched polysilicon gate; c) oxidizing the self-aligned polysilicon extending structure to form a silicon oxide protruding structure on the trenched polysilicon gate; and d) forming a first spacer on a sidewall of the silicon oxide protruding structure to define a source contact window.
  • FIGS. 1A to 1C are schematic views showing a fabrication method of a typical trenched power semiconductor structure.
  • FIGS. 2A to 2I are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a first embodiment of the present invention.
  • FIGS. 3A to 3C are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a second embodiment of the present invention.
  • FIGS. 4A and 4B are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a third embodiment of the present invention.
  • FIGS. 5A to 5D are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a fourth embodiment of the present invention.
  • the main feature of the present invention is to apply the level difference resulted from the hard mask or the poly etching back process to form spacers above the polysilicon gate, and adapts the space defined by the spacers to form a polysilicon protruding structure with a smaller width.
  • the polysilicon protruding structure is then oxidized by using thermal oxidation process to form a silicon oxide protruding structure.
  • the level difference resulted from the silicon oxide protruding structure can be utilized to form spacers for defining the location of contact window. Thus, the problem of alignment error can be prevented.
  • FIGS. 2A to 2I are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a first embodiment of the present invention.
  • a mask layer 220 is formed on an upper surface of a silicon substrate 210 .
  • the mask layer 220 has an open 222 to define at least a gate trench 230 .
  • the typical hard mask which is made by silicon oxide or silicon nitride, can be applied in the present embodiment as the mask layer 220 .
  • the silicon substrate 210 is etched with the mask layer 220 as an etching mask to form the gate trench 230 in the silicon substrate 210 .
  • a gate dielectric layer 232 is formed to line the inner surface of the gate trench 230 .
  • a polysilicon layer is deposited on the silicon substrate 210 and fills the gate trench 230 , and an etching back step follows to remove the unwanted polysilicon material and leave the trenched polysilicon gate 240 within the gate trench 230 .
  • a (second) spacer 250 is formed on the sidewall of the open 222 in the mask layer 220 .
  • the second spacer 250 is extended from the upper surface of the trenched polysilicon gate 240 upward.
  • the space defined by the second spacer 250 is filled with polysilicon material so as to form a self-aligned polysilicon extending structure 242 above the trenched polysilicon gate 240 .
  • the self-aligned polysilicon extending structure 242 is substantially aligned to the center of the trenched polysilicon gate 240 .
  • the formation of the second spacer 250 guarantees the width of the self-aligned polysilicon extending structure 242 being smaller than that of the trenched polysilicon gate 240 .
  • the mask layer 220 and the second spacer 250 are removed to expose the sidewalls of the self-aligned polysilicon extending structure 242 and the upper surface of the trenched polysilicon gate 240 .
  • Typical selective etching processes can be applied in the present fabrication step.
  • the selective etching process can be further simplified when both the mask layer 220 and the second spacer 250 are made of silicon oxide.
  • an oxidation process is carried out.
  • the exposed surfaces of the self-aligned polysilicon extending structure 242 and the trenched polysilicon gate 240 are oxidized during this oxidation process and a silicon oxide protruding structure 260 is formed above the trenched polysilicon gate 240 . It is noted that because the whole side surface of the self-aligned polysilicon structure 242 are exposed and the width of the self-aligned polysilicon structure 242 is quite small. When the whole self-aligned polysilicon structure 242 is oxidized, only a thin surface region of the trenched polysilicon gate 240 is oxidized.
  • the cross-section area of the trenched polysilicon gate 240 would not be too much influenced by the oxidation process.
  • an oxide layer 262 is also formed on the upper surface of the silicon substrate 210 in the present oxidation process to meet the need of the following ion implantation steps.
  • an ion implantation process is carried out to implant dopants of first conductive type into the silicon substrate 210 .
  • a body 270 is thus formed in the silicon substrate 210 surrounding the trenched polysilicon gate 240 .
  • another ion implantation process is used to implant dopants of second conductive type into the surface region of the silicon substrate 210 so as to foam the source doped region 280 in the upper portion of the body 270 .
  • the above mentioned first conductive type and second conductive type may be P-type and N-type or N-type and P-type respectively.
  • a first spacer 265 is formed on the sidewall of the silicon oxide protruding structure 260 to define the location of the source contact window.
  • the oxide layer 262 and a portion of the source region 280 are removed by etching to form a source contact window 282 extending into the silicon substrate 210 .
  • an ion implantation process is carried out to implant dopants of first conductive type into the bottom of the source contact window 282 so as to form a heavily doped region 285 in the body 270 .
  • a source metal layer 290 is formed on the silicon substrate 210 . The source metal layer 290 is electrically connected to the source region 280 and the body 270 .
  • the silicon oxide protruding structure 260 should be aligned to the center of the trenched polysilicon gate 240 also.
  • the present embodiment using the first spacer 265 on the sidewall of the silicon oxide protruding structure 260 to define the location of the source contact window 282 is able to prevent alignment error.
  • the distance between the source contact window 282 and the trenched polysilicon gate 240 is mainly decided by the thickness of the first spacer 265 , which is irrelevant to the critical dimension of the lithographic process.
  • the narrow silicon oxide protruding structure 260 on the trenched polysilicon gate 240 is helpful for reducing the distance between the source contact window 282 and the trenched polysilicon gate 240 to meet the need of high cell density.
  • FIGS. 3A to 3C are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a second embodiment of the present invention. The difference between the present embodiment and the first embodiment is described below. Firstly, as shown in FIG. 3A , a photo-resist layer (not shown) is used to form a gate trench 330 in the silicon substrate 310 . Then, a gate dielectric layer 332 is formed to line the inner surface of the gate trench 330 . Afterward, a trenched polysilicon gate 340 is formed in the gate trench 330 by filling polysilicon material into the gate trench 330 .
  • the trenched polysilicon gate 340 is located in the lower portion of the gate trench 330 , and a predetermined distance is kept between the upper surface of the trenched polysilicon gate 340 and the upper surface of the silicon substrate 310 . Thereafter, a second spacer 350 is formed on the sidewall of the upper portion of the gate trench 330 .
  • a polysilicon layer is deposited to fill the space defined by the second spacer 350 and an etching back process follows to form the self-aligned polysilicon extending structure 342 on the trenched polysilicon gate 340 .
  • a protection layer 352 is formed on the upper surface of the self-aligned polysilicon extending structure 342 , and then an oxidation process follows.
  • the protection layer 352 is capable to shield the self-aligned polysilicon extending structure 342 from being oxidized in this oxidation process.
  • a thick oxide layer 362 is formed to surround the self-aligned polysilicon extending structure 342 .
  • the material, which is able to prevent the diffusion of oxygen atoms, such as silicon nitride and silicon oxide, can be used to form the protection layer 352 .
  • the thick oxide layer 362 , the second spacer 350 , and the protection layer 352 are removed to expose the self-aligned polysilicon extending structure 342 .
  • the self-aligned polysilicon extending structure is now protruded from the upper surface of the silicon substrate 310 .
  • both the second spacer 350 and the protection layer 352 are formed of silicon oxide, a single etching process is able to remove the thick oxide layer 362 , the second spacer 350 , and the protection layer 352 .
  • the thick oxide layer 362 may be removed first by selectively etching, and then the second spacer 350 and the protection layer 352 .
  • the above mentioned second spacer 350 and the protection layer 352 may be formed of different materials. The following steps of the present embodiment are similar to that of the first embodiment, which are not repeated here.
  • FIGS. 4A and 4B are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a third embodiment of the present invention. The difference between the present embodiment and the second embodiment is described below.
  • FIG. 4A which follows the step of FIG. 3B , after the formation of the self-aligned polysilicon extending structure 342 on the trenched polysilicon gate 340 , the protection layer 352 is formed to shield the upper surface of the self-aligned polysilicon extending structure 342 . Then, in contrast with the oxidation process as shown in FIG. 3C , referring to FIG.
  • an etching process such as the selective etching process, is directly applied to the silicon substrate 310 with the protection layer 352 and the second spacer 350 as the etching mask.
  • the self-aligned polysilicon extending structure 342 is protruded from the silicon substrate 310 .
  • the protection layer 352 and the second spacer 350 are removed to expose the self-aligned polysilicon extending structure 342 .
  • the protection layer 352 and the second spacer 350 may be formed of silicon oxide or silicon nitride to facilitate the selective etching process.
  • the protection layer 352 and the second spacer 350 are used as the etching mask for etching the silicon substrate 310 .
  • the silicon substrate 310 can be etched by using the anisotropic etching process, such as reactive ion etching (RIE), with merely the protection layer 352 as the etching mask.
  • RIE reactive ion etching
  • FIGS. 5A to 5D are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a fourth embodiment of the present invention. The difference between the present embodiment and the first embodiment is described below.
  • a mask layer 420 is formed on the upper surface of a silicon substrate 410 .
  • the mask layer 420 as the etching mask, at least a gate trench 430 is formed in silicon substrate 410 .
  • a gate dielectric layer 432 is formed to line the inner surface of the gate trench 430 .
  • a polysilicon layer is deposited on the silicon substrate 410 .
  • the polysilicon layer fills the gate trench 430 and the open 422 of the mask layer 420 .
  • an etching back process is carried out to remove the unwanted portion of the polysilicon layer and leave a polysilicon structure 440 extended from the gate trench 430 into the open 422 of the mask layer 420 .
  • the mask layer 420 is removed to expose the upper portion of the polysilicon structure 440 .
  • the exposed surface of the polysilicon structure 440 is oxidized.
  • the oxidized portion of the polysilicon structure 440 is removed such that the width of the upper portion 400 a of the polysilicon structure 440 is reduced.
  • the resulted polysilicon structure 440 has an exposed upper portion 440 a and a lower portion located in the silicon substrate 410 .
  • the exposed upper portion 440 a can be regarded as the self-aligned polysilicon extending structure described in the above mentioned embodiments, and the lower portion 440 b can be regarded as the trenched polysilicon gate.
  • the exposed surface of the polysilicon structure 440 is oxidized before the etching step is carried out to reduce the width of the upper portion 440 a of the polysilicon structure 440 .
  • the exposed polysilicon structure 440 can be etched right after the mask layer 420 is removed, and the oxidation step can be skipped.
  • FIG. 5D another oxidation process is used to oxidize the whole self-aligned polysilicon extending structure 440 a so as to form the silicon oxide protruding structure 460 on the trenched polysilicon gate 440 b .
  • the following steps of the present embodiment which are similar to that as shown in FIGS. 2E to 2I of the first embodiment, are not repeated here.
  • the fabrication method of the present invention applies the self-alignment process to overcome the limitation of lithographic process, such that the distance between the trenched polysilicon gate and the source contact window can be reduced.
  • the fabrication method of the present invention is also helpful for enhancing fabrication yield and is benefit for increasing uniformity of cells on the wafer.
  • the fabrication method of the present invention can be easily integrated into the traditional trenched power semiconductor fabrication process, and is especially suitable for the narrow trench process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window.

Description

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a fabrication method of a trenched power semiconductor structure, and more particularly relates to a fabrication method of a self-aligned trenched power semiconductor structure.
(2) Description of the Prior Art
FIGS. 1A to 1C are schematic views showing a fabrication process of a typical trenched power semiconductor structure. As shown in FIG. 1A, firstly, a gate trench 120 is formed in a silicon substrate 110. Then, a gate oxide layer 130 is formed to line the inner surface of the gate trench 120. Afterward, a polysilicon layer is deposited on the upper surface of the silicon substrate 110 and an etching back step follows to remove the unwanted portion of the polysilicon layer so as to leave a polysilicon gate 140 in the gate trench 120.
After the formation of the polysilicon gate 140, as shown in FIG. 1B, a body implantation step is carried out to implant dopants into the silicon substrate 110 so as to form a body 150 surrounding the gate trench 120. Then, a source implantation step is carried out to implant dopants of different conductive type into the body 150 so as to form the source region 160 in the upper portion of the body 150. Thereafter, as shown in FIG. 1C, a dielectric layer 170 is deposited on the exposed surfaces of the silicon substrate 110 and fills the gate trench 120. Then, a contact window 180 for exposing the source region 160 is formed in the dielectric layer 170 and the body 150 by using lithographic and etching processes.
It is noted that the shrinkage of cell dimension of the trenched power semiconductor device is restricted by lithographic limitations. That is, due to the limitations of critical dimension for trench and contact window as well as tolerance required for alignment control, the distance between the gate trench 120 and the contact window 180 should be great enough to prevent the problems such as leakage current, variation of threshold voltage, or decreasing of avalanche ruggedness.
Accordingly, how to increase cell density of trenched power semiconductor structure under the limitations of critical dimension for trench and contact window as well as tolerance required for alignment control is an important issue to be resolved.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-density trenched power semiconductor structure and the fabrication method thereof, which applies the technology of self-alignment to overcome the limitations of critical dimension for the gate trench and the contact window as well as tolerance for alignment control.
A fabrication method of a self-aligned power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming a trenched polysilicon gate in a silicon substrate; b) forming a self-aligned polysilicon extending structure, extended upward from the trenched polysilicon gate, a width of the self-aligned polysilicon extending structure being smaller than that of the trenched polysilicon gate; c) oxidizing the self-aligned polysilicon extending structure to form a silicon oxide protruding structure on the trenched polysilicon gate; and d) forming a first spacer on a sidewall of the silicon oxide protruding structure to define a source contact window.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which:
FIGS. 1A to 1C are schematic views showing a fabrication method of a typical trenched power semiconductor structure.
FIGS. 2A to 2I are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a first embodiment of the present invention.
FIGS. 3A to 3C are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a second embodiment of the present invention.
FIGS. 4A and 4B are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a third embodiment of the present invention.
FIGS. 5A to 5D are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a fourth embodiment of the present invention.
 DESCRIPTION OF THE PREFERRED EMBODIMENT
The main feature of the present invention is to apply the level difference resulted from the hard mask or the poly etching back process to form spacers above the polysilicon gate, and adapts the space defined by the spacers to form a polysilicon protruding structure with a smaller width. The polysilicon protruding structure is then oxidized by using thermal oxidation process to form a silicon oxide protruding structure. The level difference resulted from the silicon oxide protruding structure can be utilized to form spacers for defining the location of contact window. Thus, the problem of alignment error can be prevented.
FIGS. 2A to 2I are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a first embodiment of the present invention. As shown in FIG. 2A, firstly, a mask layer 220 is formed on an upper surface of a silicon substrate 210. The mask layer 220 has an open 222 to define at least a gate trench 230. The typical hard mask, which is made by silicon oxide or silicon nitride, can be applied in the present embodiment as the mask layer 220. Then, the silicon substrate 210 is etched with the mask layer 220 as an etching mask to form the gate trench 230 in the silicon substrate 210. Afterward, a gate dielectric layer 232 is formed to line the inner surface of the gate trench 230. Then, as shown in FIG. 2B, a polysilicon layer is deposited on the silicon substrate 210 and fills the gate trench 230, and an etching back step follows to remove the unwanted polysilicon material and leave the trenched polysilicon gate 240 within the gate trench 230.
Referring to FIG. 2B, after the formation of the trenched polysilicon gate 240, a (second) spacer 250 is formed on the sidewall of the open 222 in the mask layer 220. The second spacer 250 is extended from the upper surface of the trenched polysilicon gate 240 upward. Thereafter, as shown in FIG. 2C, the space defined by the second spacer 250 is filled with polysilicon material so as to form a self-aligned polysilicon extending structure 242 above the trenched polysilicon gate 240. The self-aligned polysilicon extending structure 242 is substantially aligned to the center of the trenched polysilicon gate 240. In addition, the formation of the second spacer 250 guarantees the width of the self-aligned polysilicon extending structure 242 being smaller than that of the trenched polysilicon gate 240.
Next, as shown in FIG. 2D, the mask layer 220 and the second spacer 250 are removed to expose the sidewalls of the self-aligned polysilicon extending structure 242 and the upper surface of the trenched polysilicon gate 240. Typical selective etching processes can be applied in the present fabrication step. As a preferred embodiment, the selective etching process can be further simplified when both the mask layer 220 and the second spacer 250 are made of silicon oxide.
Next, as shown in FIG. 2E, an oxidation process is carried out. The exposed surfaces of the self-aligned polysilicon extending structure 242 and the trenched polysilicon gate 240 are oxidized during this oxidation process and a silicon oxide protruding structure 260 is formed above the trenched polysilicon gate 240. It is noted that because the whole side surface of the self-aligned polysilicon structure 242 are exposed and the width of the self-aligned polysilicon structure 242 is quite small. When the whole self-aligned polysilicon structure 242 is oxidized, only a thin surface region of the trenched polysilicon gate 240 is oxidized. The cross-section area of the trenched polysilicon gate 240 would not be too much influenced by the oxidation process. Moreover, an oxide layer 262 is also formed on the upper surface of the silicon substrate 210 in the present oxidation process to meet the need of the following ion implantation steps.
Next, as shown in FIG. 2F, an ion implantation process is carried out to implant dopants of first conductive type into the silicon substrate 210. A body 270 is thus formed in the silicon substrate 210 surrounding the trenched polysilicon gate 240. Thereafter, another ion implantation process is used to implant dopants of second conductive type into the surface region of the silicon substrate 210 so as to foam the source doped region 280 in the upper portion of the body 270. The above mentioned first conductive type and second conductive type may be P-type and N-type or N-type and P-type respectively. Then, as shown in FIG. 2F, a first spacer 265 is formed on the sidewall of the silicon oxide protruding structure 260 to define the location of the source contact window.
Next, as shown in FIGS. 2G and 2H, by using the first spacer 265 as an etching mask, the oxide layer 262 and a portion of the source region 280 are removed by etching to form a source contact window 282 extending into the silicon substrate 210. Then, as shown in FIG. 2H, an ion implantation process is carried out to implant dopants of first conductive type into the bottom of the source contact window 282 so as to form a heavily doped region 285 in the body 270. Finally, as shown in FIG. 2I, a source metal layer 290 is formed on the silicon substrate 210. The source metal layer 290 is electrically connected to the source region 280 and the body 270.
As mentioned above, because the self-aligned polysilicon extending structure 242 is aligned to the center of the trenched polysilicon gate 240, the silicon oxide protruding structure 260 should be aligned to the center of the trenched polysilicon gate 240 also. Thus, the present embodiment using the first spacer 265 on the sidewall of the silicon oxide protruding structure 260 to define the location of the source contact window 282 is able to prevent alignment error. In addition, in the present embodiment, the distance between the source contact window 282 and the trenched polysilicon gate 240 is mainly decided by the thickness of the first spacer 265, which is irrelevant to the critical dimension of the lithographic process. Moreover, the narrow silicon oxide protruding structure 260 on the trenched polysilicon gate 240 is helpful for reducing the distance between the source contact window 282 and the trenched polysilicon gate 240 to meet the need of high cell density.
FIGS. 3A to 3C are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a second embodiment of the present invention. The difference between the present embodiment and the first embodiment is described below. Firstly, as shown in FIG. 3A, a photo-resist layer (not shown) is used to form a gate trench 330 in the silicon substrate 310. Then, a gate dielectric layer 332 is formed to line the inner surface of the gate trench 330. Afterward, a trenched polysilicon gate 340 is formed in the gate trench 330 by filling polysilicon material into the gate trench 330. As shown, the trenched polysilicon gate 340 is located in the lower portion of the gate trench 330, and a predetermined distance is kept between the upper surface of the trenched polysilicon gate 340 and the upper surface of the silicon substrate 310. Thereafter, a second spacer 350 is formed on the sidewall of the upper portion of the gate trench 330.
Next, as shown in FIG. 3B, a polysilicon layer is deposited to fill the space defined by the second spacer 350 and an etching back process follows to form the self-aligned polysilicon extending structure 342 on the trenched polysilicon gate 340. Thereafter, as shown in FIG. 3C, a protection layer 352 is formed on the upper surface of the self-aligned polysilicon extending structure 342, and then an oxidation process follows. The protection layer 352 is capable to shield the self-aligned polysilicon extending structure 342 from being oxidized in this oxidation process. Thus, only the surface region of the silicon substrate 310 is oxidized, and a thick oxide layer 362 is formed to surround the self-aligned polysilicon extending structure 342. The material, which is able to prevent the diffusion of oxygen atoms, such as silicon nitride and silicon oxide, can be used to form the protection layer 352.
Then, the thick oxide layer 362, the second spacer 350, and the protection layer 352 are removed to expose the self-aligned polysilicon extending structure 342. The self-aligned polysilicon extending structure is now protruded from the upper surface of the silicon substrate 310. When both the second spacer 350 and the protection layer 352 are formed of silicon oxide, a single etching process is able to remove the thick oxide layer 362, the second spacer 350, and the protection layer 352. When both the second spacer 350 and the protection layer 352 are formed of silicon nitride, the thick oxide layer 362 may be removed first by selectively etching, and then the second spacer 350 and the protection layer 352. Certainly, the above mentioned second spacer 350 and the protection layer 352 may be formed of different materials. The following steps of the present embodiment are similar to that of the first embodiment, which are not repeated here.
FIGS. 4A and 4B are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a third embodiment of the present invention. The difference between the present embodiment and the second embodiment is described below. As shown in FIG. 4A, which follows the step of FIG. 3B, after the formation of the self-aligned polysilicon extending structure 342 on the trenched polysilicon gate 340, the protection layer 352 is formed to shield the upper surface of the self-aligned polysilicon extending structure 342. Then, in contrast with the oxidation process as shown in FIG. 3C, referring to FIG. 4B, an etching process, such as the selective etching process, is directly applied to the silicon substrate 310 with the protection layer 352 and the second spacer 350 as the etching mask. After the etching process, the self-aligned polysilicon extending structure 342 is protruded from the silicon substrate 310. Then, the protection layer 352 and the second spacer 350 are removed to expose the self-aligned polysilicon extending structure 342. The protection layer 352 and the second spacer 350 may be formed of silicon oxide or silicon nitride to facilitate the selective etching process.
In the present embodiment, the protection layer 352 and the second spacer 350 are used as the etching mask for etching the silicon substrate 310. However, according to another embodiment of the present invention, the silicon substrate 310 can be etched by using the anisotropic etching process, such as reactive ion etching (RIE), with merely the protection layer 352 as the etching mask.
FIGS. 5A to 5D are schematic views showing a fabrication method of a trenched power semiconductor structure in accordance with a fourth embodiment of the present invention. The difference between the present embodiment and the first embodiment is described below. Firstly, as shown in FIG. 5A, a mask layer 420 is formed on the upper surface of a silicon substrate 410. Then, by using the mask layer 420 as the etching mask, at least a gate trench 430 is formed in silicon substrate 410. Then, a gate dielectric layer 432 is formed to line the inner surface of the gate trench 430. Afterward, a polysilicon layer is deposited on the silicon substrate 410. The polysilicon layer fills the gate trench 430 and the open 422 of the mask layer 420. Thereafter, an etching back process is carried out to remove the unwanted portion of the polysilicon layer and leave a polysilicon structure 440 extended from the gate trench 430 into the open 422 of the mask layer 420.
Next, as shown in FIG. 5B, the mask layer 420 is removed to expose the upper portion of the polysilicon structure 440. Then, the exposed surface of the polysilicon structure 440 is oxidized. Thereafter, as shown in FIG. 5C, the oxidized portion of the polysilicon structure 440 is removed such that the width of the upper portion 400 a of the polysilicon structure 440 is reduced. As shown, the resulted polysilicon structure 440 has an exposed upper portion 440 a and a lower portion located in the silicon substrate 410. The exposed upper portion 440 a can be regarded as the self-aligned polysilicon extending structure described in the above mentioned embodiments, and the lower portion 440 b can be regarded as the trenched polysilicon gate.
In the present embodiment, the exposed surface of the polysilicon structure 440 is oxidized before the etching step is carried out to reduce the width of the upper portion 440 a of the polysilicon structure 440. However, also referring to FIGS. 5A and 5C, according to another embodiment, the exposed polysilicon structure 440 can be etched right after the mask layer 420 is removed, and the oxidation step can be skipped.
Next, as shown in FIG. 5D, another oxidation process is used to oxidize the whole self-aligned polysilicon extending structure 440 a so as to form the silicon oxide protruding structure 460 on the trenched polysilicon gate 440 b. The following steps of the present embodiment, which are similar to that as shown in FIGS. 2E to 2I of the first embodiment, are not repeated here.
According to the above mentioned embodiments, the fabrication method of the present invention applies the self-alignment process to overcome the limitation of lithographic process, such that the distance between the trenched polysilicon gate and the source contact window can be reduced. In addition, the fabrication method of the present invention is also helpful for enhancing fabrication yield and is benefit for increasing uniformity of cells on the wafer. Moreover, the fabrication method of the present invention can be easily integrated into the traditional trenched power semiconductor fabrication process, and is especially suitable for the narrow trench process.
While the preferred embodiments of the present invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the present invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the present invention.

Claims (13)

1. A fabrication method of a self-aligned power semiconductor structure, comprising the steps of:
forming a trenched polysilicon gate in a silicon substrate;
forming a self-aligned polysilicon extending structure, extended upward from the trenched polysilicon gate, a width of the self-aligned polysilicon extending structure being smaller than that of the trenched polysilicon gate;
oxidizing the self-aligned polysilicon extending structure to form a silicon oxide protruding structure on the trenched polysilicon gate; and
forming a first spacer on a sidewall of the silicon oxide protruding structure to define a source contact window.
2. The fabrication method of a self-aligned power semiconductor structure of claim 1, wherein the step of forming the trenched polysilicon gate comprises:
forming a mask layer, which has an open to define a gate trench, on an upper surface of the silicon substrate;
etching the silicon substrate through the mask layer to form the gate trench;
forming a gate dielectric layer to line an inner surface of the gate trench; and
filling polysilicon material into the gate trench.
3. The fabrication method of a self-aligned power semiconductor structure of claim 2, wherein the step of forming the self-aligned polysilicon extending structure comprises:
forming a second spacer on a sidewall of the open of the mask layer; and
filling polysilicon material into the open to form the self-aligned polysilicon extending structure.
4. The fabrication method of a self-aligned power semiconductor structure of claim 3, wherein the second spacer is formed of silicon oxide or silicon nitride.
5. The fabrication method of a self-aligned power semiconductor structure of claim 2, wherein the mask layer is formed of silicon oxide.
6. The fabrication method of a self-aligned power semiconductor structure of claim 1, wherein the whole self-aligned polysilicon extending structure is oxidized to form the silicon oxide protruding structure protruded from the silicon substrate.
7. The fabrication method of a self-aligned power semiconductor structure of claim 1, wherein an upper surface of the trenched polysilicon gate is oxidized in the step of oxidizing the self-aligned polysilicon extending structure.
8. The fabrication method of a self-aligned power semiconductor structure of claim 2, wherein the polysilicon material is filled into the gate trench and the open to form a polysilicon structure having a lower portion as the trenched polysilicon structure, and the step of forming the self-aligned polysilicon extending structure comprises:
removing the mask layer to expose an upper portion of the polysilicon structure; and
reducing a width of the upper portion of the polysilicon structure by etching to form the self-aligned polysilicon extending structure.
9. The fabrication method of a self-aligned power semiconductor structure of claim 2, wherein the step of reducing a width of the upper portion comprises:
oxidizing the upper portion to form an oxide layer thereon; and
removing the oxide layer to form the self-aligned polysilicon extending structure protruded from the silicon substrate.
10. The fabrication method of a self-aligned power semiconductor structure of claim 1, wherein the step of forming the trenched polysilicon gate comprises:
forming a gate trench in the silicon substrate via a photo-resist layer;
forming a gate dielectric layer to line an inner surface of the gate trench; and
filling polysilicon material into the gate trench to form the trenched polysilicon gate in a lower portion of the gate trench.
11. The fabrication method of a self-aligned power semiconductor structure of claim 10, wherein the step of forming the self-aligned polysilicon extending structure comprises:
forming a second spacer on a sidewall of an upper portion of the gate trench;
filling polysilicon material into the upper portion of the gate trench to form the self-aligned polysilicon extending structure;
forming a protection layer to shield the self-aligned polysilicon extending structure; and
etching an upper surface of the silicon substrate to have the self-aligned polysilicon extending structure protruded from the silicon substrate.
12. The fabrication method of a self-aligned power semiconductor structure of claim 11, wherein the step of etching the upper surface of the silicon substrate comprises:
oxidizing the upper surface of the silicon substrate to form a thick oxide layer; and
removing the thick oxide layer to have the self-aligned polysilicon extending structure protruded from the silicon substrate.
13. The fabrication method of a self-aligned power semiconductor structure of claim 11, wherein the step of etching the upper surface of the silicon substrate uses the protection layer as an etching mask.
US12/797,898 2010-06-10 2010-06-10 Fabrication method of self-aligned trenched power semiconductor structure Expired - Fee Related US8283230B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/797,898 US8283230B2 (en) 2010-06-10 2010-06-10 Fabrication method of self-aligned trenched power semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/797,898 US8283230B2 (en) 2010-06-10 2010-06-10 Fabrication method of self-aligned trenched power semiconductor structure

Publications (2)

Publication Number Publication Date
US20110306194A1 US20110306194A1 (en) 2011-12-15
US8283230B2 true US8283230B2 (en) 2012-10-09

Family

ID=45096559

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/797,898 Expired - Fee Related US8283230B2 (en) 2010-06-10 2010-06-10 Fabrication method of self-aligned trenched power semiconductor structure

Country Status (1)

Country Link
US (1) US8283230B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108039372A (en) * 2017-12-21 2018-05-15 深圳迈辽技术转移中心有限公司 Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100843244B1 (en) * 2007-04-19 2008-07-02 삼성전자주식회사 Semiconductor device and method of fabricating the same
US8612477B2 (en) 2010-09-24 2013-12-17 Aol Inc. Systems and methods for customized electronic communications

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057194A (en) * 1996-10-30 2000-05-02 Advanced Micro Devices, Inc. Method of forming trench transistor in combination with trench array
US6312989B1 (en) * 2000-01-21 2001-11-06 Taiwan Semiconductor Manufacturing Company Structure with protruding source in split-gate flash
US6359309B1 (en) * 1999-01-04 2002-03-19 Industrial Technology Research Institute Power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US20030008450A1 (en) * 2001-03-16 2003-01-09 Taiwan Semiconductor Manufacturing Company Self-aligned process for a stacked gate RF MOSFET device
US6838734B2 (en) * 2001-10-05 2005-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications
US6965146B1 (en) * 2004-11-29 2005-11-15 Silicon-Based Technology Corp. Self-aligned planar DMOS transistor structure and its manufacturing methods

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057194A (en) * 1996-10-30 2000-05-02 Advanced Micro Devices, Inc. Method of forming trench transistor in combination with trench array
US6359309B1 (en) * 1999-01-04 2002-03-19 Industrial Technology Research Institute Power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6312989B1 (en) * 2000-01-21 2001-11-06 Taiwan Semiconductor Manufacturing Company Structure with protruding source in split-gate flash
US20030008450A1 (en) * 2001-03-16 2003-01-09 Taiwan Semiconductor Manufacturing Company Self-aligned process for a stacked gate RF MOSFET device
US6838734B2 (en) * 2001-10-05 2005-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications
US6965146B1 (en) * 2004-11-29 2005-11-15 Silicon-Based Technology Corp. Self-aligned planar DMOS transistor structure and its manufacturing methods

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108039372A (en) * 2017-12-21 2018-05-15 深圳迈辽技术转移中心有限公司 Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof
CN108039372B (en) * 2017-12-21 2021-12-07 上海领矽半导体有限公司 Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof

Also Published As

Publication number Publication date
US20110306194A1 (en) 2011-12-15

Similar Documents

Publication Publication Date Title
JP5862729B2 (en) Manufacturing method of trench gate type semiconductor device
US8507349B2 (en) Semiconductor device employing fin-type gate and method for manufacturing the same
US20130221431A1 (en) Semiconductor device and method of manufacture thereof
US9379187B2 (en) Vertically-conducting trench MOSFET
JP2002076112A (en) Semiconductor element capable of reducing junction leakage current and narrow width effect and its manufacturing method
US9991347B2 (en) Semiconductor device having a cavity
CN112242305A (en) Semiconductor device and method for manufacturing the same
US8283230B2 (en) Fabrication method of self-aligned trenched power semiconductor structure
US20110215397A1 (en) High cell density trenched power semiconductor structure and fabrication method thereof
US9012985B2 (en) Semiconductor device having a trench whose upper width is wider than a lower width thereof, and a method for fabricating the same
CN112271134B (en) Method for manufacturing semiconductor power device
CN106024898B (en) Groove power device and manufacturing method
TWI412088B (en) Fabrication method of self-aligned trenched power semiconductor structure
KR100626908B1 (en) A method for forming a field oxide of semiconductor device
CN110379850B (en) Method for manufacturing trench type power transistor
KR20100079968A (en) Semiconductor device and method for fabricating the same
KR20070002661A (en) Method for forming transistor of semiconductor device
KR20060000552A (en) Method for manufacturing semiconductor device having recess channel transistor
CN116565002A (en) High gate lock threshold split gate power MOSFET structure and manufacturing method
KR100951570B1 (en) Semiconductor device with recess gate and method for manufacturing the same
CN116825621A (en) Method for manufacturing silicon carbide device
CN117790536A (en) Junction terminal structure, preparation method thereof and semiconductor device
US20120309177A1 (en) Trenched power semiconductor structure with reduced gate impedance and fabrication method thereof
KR20060075000A (en) Transistor in semiconductor memory device and method for manufacturing the same
KR20080074528A (en) Method of forming gate electrode of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: GREAT POWER SEMICONDUCTOR CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YEH, CHUN YING;REEL/FRAME:024517/0857

Effective date: 20100518

CC Certificate of correction
REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20161009