US7548822B2 - Apparatus and method for determining the slew rate of a signal produced by an integrated circuit - Google Patents
Apparatus and method for determining the slew rate of a signal produced by an integrated circuit Download PDFInfo
- Publication number
- US7548822B2 US7548822B2 US11/777,329 US77732907A US7548822B2 US 7548822 B2 US7548822 B2 US 7548822B2 US 77732907 A US77732907 A US 77732907A US 7548822 B2 US7548822 B2 US 7548822B2
- Authority
- US
- United States
- Prior art keywords
- output
- slew rate
- integrated circuit
- signal
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3016—Delay or race condition test, e.g. race hazard test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
Definitions
- IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
- This invention relates to semiconductor devices and, more particularly, to techniques for determining the slew rate of a signal produced by an integrated circuit.
- Slew rate represents the maximum rate of change of signal at any point in an electronic circuit. Limitations in the slew rate capability of an integrated circuit may give rise to undesirable non-linear effects. For example, in order for a sinusoidal waveform not to be subject to slew rate limitations, the slew rate capability at all points in an amplifier or other circuit must exceed 2 ⁇ fV pk , where f is the frequency, and V pk is the peak value of the waveform. Slew rate is generally expressed in units of Volts per microseconds ( ⁇ s). The output slew rate of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals.
- SR max ⁇ ( ⁇ d ⁇ out ⁇ ( t ) d t ⁇ ) where ⁇ out (t) is the output produced by the amplifier as a function of time t.
- the slew rate of an amplifier may be measured using a square wave generator and an oscilloscope.
- an integrated circuit may utilize an input stage in the form of a differential amplifier having a transconductance characteristic.
- Transconductance refers to the input stage accepting a differential input voltage and, in response thereto, generating an output current in an additional stage.
- the transconductance of many integrated circuits is designed to be quite high, so as to provide a large amount of open loop gain. This high current gain means that a fairly small input voltage can cause the input stage to saturate, thereby producing a nearly constant output current.
- the additional stage of the integrated circuit may be utilized to implement a frequency compensation function. More specifically, the additional stage may have a low pass characteristic approximating an integrator. A constant current input will therefore produce a linearly increasing output. If the additional stage has a compensation capacitance C and gain A 2 , then slew rate in this example can be expressed as:
- slew rate detection may be employed to provide an indication of short-circuit current flowing through a sink gate. If the slew rate is large, this signifies that a set of voltage pull-up semiconductor devices in the integrated circuit and a set of voltage pull-down semiconductor devices in the integrated circuit are partially on for the duration that a signal is greater than the threshold voltage (VTN) of an N-type field effect transistor (NFET), but less than the supply voltage (Vdd) minus the threshold voltage (VTP) of a P-type field effect transistor (PFET), thereby providing a low-resistance path between the supply voltage and ground.
- VTN threshold voltage
- NFET N-type field effect transistor
- Vdd supply voltage
- VTP threshold voltage
- PFET P-type field effect transistor
- NMOS n-type metal-oxide semiconductor
- PMOS p-type metal-oxide semiconductor
- the delay impact of a performance variation may be minimal, whereas the power impact of a performance variation may be significant.
- other microprocessors may fail to meet the target frequency but show nominal leakage power.
- slew rate detectors that can detect mismatches between two different types of semiconductor devices. With the availability of such information, it is then possible to compensate for these mismatches and thus improve the yield of a given microprocessor design.
- the shortcomings of the prior art are overcome and additional advantages are provided by methods and apparatuses for determining a slew rate of a signal produced by an integrated circuit under test.
- These apparatuses include a first comparator for comparing the signal with a first reference voltage, a second comparator for comparing the signal with a second reference voltage different from the first reference voltage, an exclusive OR (XOR) gate operatively coupled to the first and second comparators for generating an output pulse having a pulse width indicative of a slew rate of the signal, and an integrator for integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.
- XOR exclusive OR
- Methods for determining a slew rate of a signal produced by an integrated circuit under test comprise: comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.
- FIG. 1 illustrates one example of a slew rate monitor for detecting the slew rate of a signal produced by an integrated circuit
- FIG. 2 illustrates one example of a PMOS comparator for use with the slew rate monitor of FIG. 1 ;
- FIG. 3 illustrates one example of a unity gain buffer for use with the slew rate monitor of FIG. 1 ;
- FIG. 4 is a plot showing the relationship between sense voltage and slew for the slew rate monitor of FIG. 1 .
- FIG. 1 illustrates one example of a slew rate monitor for detecting the slew rate of a signal produced by an integrated circuit.
- This slew rate monitor may be employed, for example, to estimate the extent of a mismatch between a first type of semiconductor device and a second type of semiconductor device used in the integrated circuit.
- a signal under test (SUT) 101 representing a signal produced by an integrated circuit under test, is connected to two comparators, a comparator-N 105 and a comparator-P 103 .
- Comparator-N 105 is an NMOS comparator comprised of thick-oxide long channel NMOS devices and capable of comparing SUT 101 with a first reference voltage less than a second reference voltage.
- this first reference voltage could, but need not, be substantially equal to 20% of a supply voltage being supplied to the integrated circuit under test.
- Comparator-P 103 is a PMOS comparator comprised of thick-oxide long channel PMOS devices and capable of comparing SUT 101 with the second reference voltage.
- this second reference voltage could, but need not, be substantially equal to 80% of the supply voltage being supplied to the integrated circuit under test.
- the first and second reference voltages each represent any value within a range of amplitudes defined by the input signal. The first and second voltages could, but need not, add up to the supply voltage.
- first reference voltage substantially equal to 20% of supply voltage and a second reference voltage substantially equal to 80% of the supply voltage is advantageous in that good resolution may be obtained for a sense voltage 123 produced by the slew rate monitor of FIG. 1 , along with a wider range of voltages for sense voltage 123 .
- these values for first and second reference voltages are used to provide a sufficient noise margin against any power supply noise appealing on SUT 101 .
- the slew rate monitor of FIG. 1 could alternatively or additionally be configured for a first reference voltage substantially equal to 10% of supply voltage with a second reference voltage substantially equal to 90% of supply voltage, or alternatively or additionally configured for any set of first and second reference voltages, the sum of which total to substantially 100% of supply voltage.
- the first and second reference voltages are used to characterize a rise slew for SUT 101 .
- rise slew of SUT 101 is defined as time taken for the signal to rise from 20% of the supply voltage to 80% of the supply voltage, or from 10% of the supply voltage to 90% of the supply voltage.
- a fall slew of the signal is defined as time taken for the signal to fall from 80% of the supply voltage to 20% of the supply voltage, or from 90% of the supply voltage to 10% of the supply voltage.
- the output of one comparator switches before the output of the other comparator, depending upon the slew of SUT 101 and the direction of transition.
- an output U 107 of comparator-P 103 may switch before an output V 109 of comparator-N 105 switches, or the output V 109 of comparator-N 105 may switch before the output U 107 of comparator-P 103 switches.
- Outputs U 107 and V 109 are fed to an input of an exclusive-OR (XOR) 111 gate.
- XOR 111 gate generates an output in the form of a pulse 113 having a pulse width W. Pulse width W is indicative of the slew rate of SUT 101 .
- Pulse 113 is integrated over time by an integrator 117 to generate an output voltage 119 proportional to pulse width W. Integrator 117 thus functions as a time-to-voltage converter. Therefore, output voltage 119 is proportional to the slew rate of SUT 101 .
- Discharge circuit 115 operably coupled to integrator 117 , acts as a reset mechanism. This reset mechanism enables output voltage 119 of integrator 117 to be reset to zero before a new SUT 101 is applied to the slew rate monitor of FIG. 1 .
- Output voltage 119 is fed to a very low output offset unity gain buffer 121 , the output of which is represented as sense voltage 123 indicative of the extent of semiconductor device mismatch in the integrated circuit under test.
- one or more of the elements shown in FIG. 1 may be fabricated using thick oxide semiconductor devices.
- Comparator-P 103 may be implemented using a PMOS high speed comparator that exhibits high transconductance gain G M .
- comparator-N 105 may be implemented using an NMOS high speed comparator that exhibits high transconductance gain G M .
- FIG. 2 illustrates one example of a PMOS comparator for use with the slew rate monitor of FIG. 1 to implement comparator-P 103 .
- comparator-N 105 could be implemented with an identical architecture as used for comparator-P 103 , with the exception that the PMOS devices of comparator-P 103 would be replaced with NMOS devices for comparator-N 105 .
- the PMOS comparator of FIG. 2 includes a cross-coupled input (i/p) stage 201 providing high transconductance gain G M for the purpose of achieving faster output response.
- Input stage 201 functions as a preamplifier with a very high bandwidth for providing an amplified signal with minimal delay to a latched output (o/p) stage 203 .
- Latched output stage 203 is providing a positive feedback to achieve a high positive exponential response at its output.
- the combination of input stage 201 and latched output stage 203 provides a minimum delay output with a fast slew rate.
- Latched output stage 203 drives an output (o/p) driver stage 205 .
- Output driver stage 205 may be implemented using a suitably sized inverter based buffer with an output drive current capacity determined in accordance with specified load parameters for the PMOS comparator.
- the P comparator may be designed to provide an output slew of 30 picoseconds (ps) and an output delay of 2 nanoseconds (ns) for an SUT 101 ( FIG. 1 ) slew of 25 ps.
- Integrator 117 may be implemented using a simple current mirror based linear integrator having a discharge path connected to a first capacitor designated as an output capacitor.
- a second capacitor designated as a decoupling capacitor, is used as an integrating capacitor.
- the integrating time constant is dependent upon the value of the integrating capacitor and the integrating current of integrator 117 and, hence, can be tuned as required, depending upon the pulse width W of pulse 113 .
- FIG. 3 illustrates one example of a suitable architecture for implementing unity gain buffer 121 of FIG. 1 .
- the unity gain buffer may be implemented using a rail-to-rail input stage operational amplifier (OPAMP) in the unity-gain-buffer mode to provide a rail-to-rail output dynamic range.
- Biasing circuitry 301 is employed to bias an NMOS/PMOS coupled input stage 303 .
- NMOS/PMOS coupled input stage 303 may represent an N-channel and a P-channel differential input stage coupled in parallel to achieve an extended input common mode range (ICMR) of supply voltage.
- ICMR extended input common mode range
- the desired high output gain is achieved using a cascode output stage 305 which drives an output driver stage 307 .
- NMOS/PMOS coupled input stage 303 is coupled to the output of output driver stage 307 to operate the OPAMP as a unity gain buffer.
- This OPAMP exhibits a very low output offset voltage on the order of 1-2 millivolts (mV).
- FIG. 4 is a plot showing the relationship between sense voltage 123 ( FIG. 1 ) and input slew of SUT 101 for the slew rate monitor of FIG. 1 .
- the input slew representing signal SUT 101 ( FIG. 1 ) produced by an integrated circuit under test, is varied from 25 ps to 250 ps and the output of unity gain buffer 121 is then plotted.
- the slew rate monitor of FIG. 1 exhibits an output sensitivity of 0.5 mV per ps.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
where νout(t) is the output produced by the amplifier as a function of time t. As a practical matter, the slew rate of an amplifier may be measured using a square wave generator and an oscilloscope.
where Isat is the output current of the first stage in saturation.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/777,329 US7548822B2 (en) | 2007-07-13 | 2007-07-13 | Apparatus and method for determining the slew rate of a signal produced by an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/777,329 US7548822B2 (en) | 2007-07-13 | 2007-07-13 | Apparatus and method for determining the slew rate of a signal produced by an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090018787A1 US20090018787A1 (en) | 2009-01-15 |
US7548822B2 true US7548822B2 (en) | 2009-06-16 |
Family
ID=40253850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/777,329 Active 2027-07-23 US7548822B2 (en) | 2007-07-13 | 2007-07-13 | Apparatus and method for determining the slew rate of a signal produced by an integrated circuit |
Country Status (1)
Country | Link |
---|---|
US (1) | US7548822B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9425795B2 (en) | 2013-03-07 | 2016-08-23 | Stichting Imec Nederland | Circuit and method for detection and compensation of transistor mismatch |
US10175297B2 (en) | 2016-07-13 | 2019-01-08 | International Business Machines Corporation | Measuring a slew rate on-chip |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103905028B (en) * | 2012-12-25 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Signal receiver and signal transmission apparatus |
JP2014134498A (en) * | 2013-01-11 | 2014-07-24 | Advantest Corp | Detection device, wafer and electronic device |
US20160036373A1 (en) * | 2014-07-31 | 2016-02-04 | Fraunhofer Usa, Inc. | Photovoltaic systems and related techniques |
US9264187B1 (en) * | 2014-10-09 | 2016-02-16 | Intel Corporation | Measuring bit error rate during runtime of a receiver circuit |
US10311966B2 (en) * | 2016-02-22 | 2019-06-04 | International Business Machines Corporation | On-chip diagnostic circuitry monitoring multiple cycles of signal samples |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4612654A (en) * | 1984-08-27 | 1986-09-16 | Analog And Digital Systems, Inc. | Digital encoding circuitry |
JPH04225177A (en) | 1990-12-27 | 1992-08-14 | Mitsubishi Electric Corp | Measuring apparatus for slew rate of semiconductor device |
US6573767B1 (en) | 2001-10-11 | 2003-06-03 | Lsi Logic Corporation | Power ground short circuit, with adjustable activation delay and activation time period |
US6650174B2 (en) | 1998-07-15 | 2003-11-18 | Linear Technology Corporation | Active pullup circuitry for open-drain signals |
US20040189363A1 (en) * | 2003-03-26 | 2004-09-30 | Midori Takano | Phase interpolator and receiver |
US6864731B2 (en) | 2001-03-30 | 2005-03-08 | Intel Corporation | Method and device for symmetrical slew rate calibration |
US20050201491A1 (en) * | 2004-03-09 | 2005-09-15 | Jason Wei | System and method for selecting optimal data transition types for clock and data recovery |
-
2007
- 2007-07-13 US US11/777,329 patent/US7548822B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4612654A (en) * | 1984-08-27 | 1986-09-16 | Analog And Digital Systems, Inc. | Digital encoding circuitry |
JPH04225177A (en) | 1990-12-27 | 1992-08-14 | Mitsubishi Electric Corp | Measuring apparatus for slew rate of semiconductor device |
US6650174B2 (en) | 1998-07-15 | 2003-11-18 | Linear Technology Corporation | Active pullup circuitry for open-drain signals |
US6864731B2 (en) | 2001-03-30 | 2005-03-08 | Intel Corporation | Method and device for symmetrical slew rate calibration |
US6573767B1 (en) | 2001-10-11 | 2003-06-03 | Lsi Logic Corporation | Power ground short circuit, with adjustable activation delay and activation time period |
US20040189363A1 (en) * | 2003-03-26 | 2004-09-30 | Midori Takano | Phase interpolator and receiver |
US20050201491A1 (en) * | 2004-03-09 | 2005-09-15 | Jason Wei | System and method for selecting optimal data transition types for clock and data recovery |
Non-Patent Citations (1)
Title |
---|
ESP, [online]; [retrieved on Jul. 12, 2007]; retrieved from the Internet http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=JP4225177&F=0; Japanese Paten Abstract; "Measuring Apparatus for Slew Rate of Semiconductor Device"; Aug. 14, 1992; 1p; JP4225177, Japan. |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9425795B2 (en) | 2013-03-07 | 2016-08-23 | Stichting Imec Nederland | Circuit and method for detection and compensation of transistor mismatch |
US10175297B2 (en) | 2016-07-13 | 2019-01-08 | International Business Machines Corporation | Measuring a slew rate on-chip |
Also Published As
Publication number | Publication date |
---|---|
US20090018787A1 (en) | 2009-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7548822B2 (en) | Apparatus and method for determining the slew rate of a signal produced by an integrated circuit | |
US8111090B2 (en) | Voltage comparator having improved kickback and jitter characteristics | |
US7548117B2 (en) | Differential amplifier having an improved slew rate | |
US8319526B2 (en) | Latched comparator circuit | |
US6798250B1 (en) | Current sense amplifier circuit | |
US20050270077A1 (en) | Method and apparatus for providing a power-on reset signal | |
US8405439B2 (en) | Duty cycle adjusting system | |
US7498847B2 (en) | Output driver that operates both in a differential mode and in a single mode | |
Sangeetha et al. | An overview of dynamic cmos comparators | |
US9130793B2 (en) | Constant delay zero standby differential logic receiver and method | |
US11435382B2 (en) | High-speed AFE for current monitoring applications | |
JP3739646B2 (en) | Input buffer circuit | |
US8324950B2 (en) | Schmitt trigger circuit operated based on pulse width | |
US6759878B2 (en) | Voltage comparator circuit and substrate bias adjusting circuit using same | |
US7034598B2 (en) | Switching point detection circuit and semiconductor device using the same | |
US7560936B1 (en) | Method and apparatus for ground bounce and power supply bounce detection | |
Chow et al. | A high performance peak detector sample and hold circuit for detecting power supply noise | |
Ghosh et al. | On-chip process variation detection using slew-rate monitoring circuit | |
US7782111B2 (en) | Narrow pulse generator | |
US7279909B1 (en) | Signal coincidence detection circuit | |
US9490808B2 (en) | Sensing circuit | |
US6583670B2 (en) | CMOS current amplifier | |
Ateşavcı et al. | Degradation Sensor Circuits for Indirect Measurements in Re-configurable Analog Circuit Design | |
Siskos et al. | A simple built-in current sensor for current monitoring in mixed-signal circuits | |
Ketchen et al. | Circuit to measure high speed pulse IV characteristics with only DC I/O's |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUANG, CHING-TE K.;GHOSH, AMLAN;KIM, JAE-JOON;AND OTHERS;REEL/FRAME:019553/0883 Effective date: 20070711 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
SULP | Surcharge for late payment | ||
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |