US7450663B2 - Interpolation for use in channel estimation - Google Patents
Interpolation for use in channel estimation Download PDFInfo
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- US7450663B2 US7450663B2 US10/508,928 US50892805A US7450663B2 US 7450663 B2 US7450663 B2 US 7450663B2 US 50892805 A US50892805 A US 50892805A US 7450663 B2 US7450663 B2 US 7450663B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
- H04L25/0224—Channel estimation using sounding signals
- H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
- H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
- H04L25/0232—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals
Definitions
- the present invention is related to telecommunications systems and in particular it concerns a method and a device for the estimation of the transfer function of a transmission channel.
- W-CDMA Wideband-Code Division Multiple Access
- FDD Frequency Division Duplexing
- This type of signal tracking requires a very accurate estimation of the transfer function of the transmission channel, referenced to in the sequel as “channel estimation”, in the presence of fading and multiple reflections due to user's motion in the covering area, without giving any details about a user's displacement velocity.
- the channel estimation function may be assigned to processing devices (for example, DSPs, microcontrollers, etc) and in such a case this is achieved by means of software or through dedicated devices (for example FPGAs, ASICs, etc.) and therefore the implementation modality is mainly hardware based.
- processing devices for example, DSPs, microcontrollers, etc
- dedicated devices for example FPGAs, ASICs, etc.
- the design engineer has to find out the best distribution of the different tasks among programmed devices and wired devices.
- the communication bus between the DSP device and the hardware resources acts as a bottleneck of the system.
- the load of the bus becomes greater and greater as the number of users increases, and when the functions involved require the transfer between DSP and hardware resources of considerable bulks of data.
- Channel estimation is one of said functionalities, since it has to be repeated for any fingers (sub-channels) of each individual user.
- the device can be fully implemented through hardware and therefore can be easily integrated into a Rake receiver for base stations, keeping the same performance as of the software solutions based on DSP processors. Since no data transfer with the DSP processor is required, the communication bus is left free for other tasks.
- a particular subject matter of the present invention are a method and a device for the estimation of the transfer function of a transmission channel, as described in the appended claims.
- the method and the device subject matter of this invention make use of an algorithm of a low complexity, for the estimation of the transfer function of a transmission channel, suitable for both the transmission path toward a base station, called “up-link”, and for the transmission path toward a mobile terminal, called “down-link”.
- the method according to the invention envisages the computation of a plurality of channel coefficients, included among known channel coefficients corresponding to pilot symbols, through the reiteration of an interpolation algorithm, capable of calculating an intermediate point between a first extreme and a second extreme of a determined interval.
- the first extreme is formed by at least two known points and the second extreme is formed by at least one known point.
- the intermediate point to be calculated has an abscissa equal to the abscissa value of a mean point between the points defining the interval rounded off to the integer closest to the first extreme, and has an ordinate equal to the arithmetic average between the ordinate of the known point of the second extreme and the ordinate of a point, chosen between the two known points of the first extreme, having a distance from the intermediate point equal to the distance between the intermediate point and the known point of the second extreme.
- FIG. 1 is a schematic representation of the symbols of a data channel DPDCH and of a control channel DPCCH, in the case of a transmission path toward a radio mobile station;
- FIG. 2 is a graph illustrating a plurality of channel coefficients obtained through linear interpolation between two known channel coefficients.
- FIG. 3 is a flow chart illustrating a first interpolation algorithm implemented according to this invention.
- FIG. 10 is a state diagram summarising the operations required for computing the channel coefficients in the cases depicted in FIGS. 4 to 9 ;
- FIG. 12 is a block diagram of a circuit performing an interpolation algorithm, implemented according to the present invention.
- the coherent tracking for the radio interface of UMTS systems may be obtained by using time-multiplexed pilot symbols in the control channel DPCCH (Dedicated Physical Control Channel).
- DPCCH Dedicated Physical Control Channel
- FIG. 1 there is schematically depicted the time relation between the symbols of the data channel DPDCH (Dedicated Physical Data Control Channel) and the symbols of control channel DPCCH in a time interval called “time slot”.
- DPDCH Dedicated Physical Data Control Channel
- time slot a time interval called “time slot”.
- X Q ( 0 ), X Q ( 1 ) and X Q ( 2 ) are at the beginning of the slot.
- TFCI Transport-Format Combination Indicator
- FBI Feeback Information
- TPC Transmit Power Control
- the number of pilot symbols within an individual slot may vary from a minimum of three to a maximum of eight; therefore the number of channel coefficients that will have to be estimated through interpolation, shall vary between seven and two, being ten the total number of symbols present in a slot of a control channel DPCCH.
- FIG. 2 depicts for instance the case in which seven channel coefficients (in the figure are represented the in the phase components only), globally indicated with reference 2 , have been computed through interpolation between the last coefficient C I (N PILOT ⁇ 1) of the current slot, corresponding to a value of abscissa value A and a first coefficient of the following slot, indicated in the figure as C I ( 10 ) and corresponding to a value of abscissa B.
- the pilot symbols thus also the channel coefficients, always correspond by common assumption to integer abscissa values (0, 1, 2, 3, . . . ) on a horizontal time axis (Time).
- the interpolation method and device implemented according to the present invention allow computation of the components C I (k) ⁇ C Q (k) of the channel coefficients without using complex operations such as multiplication and division, but only utilising additions and divisions by two (the latter ones of easy implementation in hardware through a shift operation on the right side of a register) allowing a considerable reduction in the hardware architecture complexity of the interpolation unit.
- the interpolation method according to the present invention will now be described in detail with reference to the flow chart of FIG. 3 .
- the algorithm shown in FIG. 3 allows the computation, through interpolation of a plurality of points, included between a last channel coefficient of abscissa A, a current slot L, and a first channel coefficient of abscissa B, of a slot L+1 subsequent to said current slot. Since the minimum number of channel coefficients in each slot is equal to three, the coefficient, of abscissa A ⁇ 1, immediately preceding the last channel coefficient of each slot is always known and therefore can be used for the interpolation computation.
- Y abscissa of the known right-hand point, used for the interpolation, a value initially corresponding to B;
- W abscissa of the extreme left point, actually used for the interpolation, corresponding, depending on the case, to point X or to point X ⁇ 1;
- Variables X e Y are initialised as being equal to the extremes A and B in the initial block indicated by reference 32 in FIG. 3 .
- abscissa Z is obviously calculated as an integer of the intermediate point between X an Y.
- the value of abscissa Z is rounded off to the lower integer through function FLOOR (symbolically indicated in the figure).
- the ordinate f(Z) of the intermediate point Z is calculated by arithmetically averaging between the ordinate of the extreme left-hand point W and the ordinate of the right-hand extreme Y, which are known.
- Block 36 algorithm is recursively applied to the half-interval at the left side of the point previously computed, until the abscissa point X+1 is attained.
- variable Z the next step is to assign to variable X the value Z ⁇ 1 that represents the first known left-hand point, and to search, by subsequent attempts, for the first known right-hand point of Z, that is. the value which is assigned to variable Y. To perform the latter operation, variable Y is increased by a unit each time, until a corresponding known coefficient has been reached.
- the previously-mentioned algorithm shown in FIG. 3 , allows computation, exclusively by sums, divisions by two and compare operations between registers, of any number of channel coefficients contained in an interval defined on the left side by two known coefficients (of abscissa A and A ⁇ 1) and on the right side by a known coefficient (of abscissa B).
- the channel coefficients are plotted corresponding to the three pilot symbols of the current slot, namely to abscissa positions 0 , (A ⁇ 1) and 2 (A), and to the first pilot symbol of the subsequent slot, to the abscissa position 10 (B) respectively.
- the channel coefficients to be computed are therefore those corresponding to the abscissa positions 3 to 9 .
- the interpolation operation is carried out by subsequent steps; the number of steps directly depends upon the number of channel coefficients to be computed. In case of FIG. 4 the computation is performed in seven steps (Step 1 to Step 7 ).
- the interpolation plan illustrated in FIG. 5 uses the abscissa point A ⁇ 1 as the left-hand extreme for the interpolation. Even if it introduces a slight degradation of the overall characteristics of the system, this approximation greatly simplifies the computation of the interpolated coefficients.
- X 8;
- C I (9) [ C I (8)+ C I (10)]/2
- C Q (9) [ C Q (8)+ C Q (10)]/2
- the interpolation plan of FIG. 7 is based on four consecutive steps, summarised hereinafter:
- FIG. 10 The six cases previously described and illustrated with reference to FIGS. 4 to 9 , can be schematised in the state diagram shown in FIG. 10 .
- the diagram of FIG. 10 whose sequence of operations essentially depends on the value of the N PILOT parameter, shows how it is possible to implement, by means of a simple state machine, a hardware or software device, which is the embodiment of the method of this invention.
- the diagram there is shown only the phase component C I (k) of the channel components, owing to the fact that the formulas for the computation of the corresponding quadrature component C Q (k) are equivalent.
- N PILOT 6
- the example of FIG. 11 for the computation of a plurality of channel coefficients, corresponding to the abscissa positions 6 to 9 , use is made of the known channel coefficients, corresponding to the last pilot symbol, of abscissa A, of the current slot L and to the first two pilot symbols, of abscissas B and B+1, of the slot L+1 subsequent to the current one.
- This second method allows the computation, by interpolation, of a plurality of points comprised between a last channel coefficient, of abscissa A, of a current slot L, and the first two channel coefficients, of abscissas B and B+1, of a subsequent slot L+1.
- X abscissa of the known left-hand point, used for the interpolation, a value which initially corresponds to A;
- Y abscissa of the known right-hand point of the interpolation interval, a value which initially corresponds to B;
- W abscissa of the right-hand extreme point, actually used for the interpolation corresponding from time to time either to point Y or to point Y+1;
- the variables X and Y are initially set to be equal to the extremes A and B.
- abscissa Z obviously meant as an integer number, of the intermediate point between X and Y.
- the value of abscissa Z is rounded off to the higher integer through the function CEIL [(X+Y)/2].
- the calculation is then carried out of the ordinate f(Z) of intermediate point Z by arithmetic averaging between the ordinate of the right-hand extreme point W and the ordinate of the left-hand extreme X, which are known.
- the procedure applied is by decreasing abscissas starting from the last calculated point Y ⁇ 1 and searching for a first point still to be computed. If the left-hand extreme A of the interval is reached, the algorithm is terminated, since all the points have already been calculated.
- variable Y is assigned the value Z+1, which represents the first known right-hand point, and the search is made by subsequent attempts for the first known left-hand point of Z, a value which is assigned to variable X.
- variable X is decreased each time by a unit, until a corresponding known coefficient is reached.
- the algorithm described in the second interpolation method may be regarded as a “mirror” version of the algorithm previously described with reference to FIG. 3 .
- this method allows computations exclusively through additions, divisions by two and compare operations between registers, of any number of channel coefficients contained in an interval defined at the left side by a known coefficient (of abscissa A) and at the right side by two known coefficients (of abscissas B and B+1).
- Coefficient C(1) is calculated as a linear combination of the same pilots:
- CL I C I (1)/2+[ C I (0)+ C I (2)]/4
- CL Q C Q (1)/2+[ C Q (0)+ C Q (2)]/4
- Linear combinations are so chosen as to be implemented in the form of sums and shifts of bits, in a similar way as has been illustrated for the interpolation.
- the interpolation algorithm for the calculation of the missing coefficients can therefore be applied following the plan already illustrated for three pilots and reported in FIG. 4 .
- This variation of the method is applicable in the extremely frequent case of the pilots being affected by noise: a linear combination, which represents a weighed average of the known channel coefficients, albeit affected by noise, provides a more reliable estimate of the known points for the interpolation.
- FIG. 12 shows a possible hardware implementation of a device for the channel estimation according to the present invention, in case of a transmission path towards a radio base station and a spreading factor of the channel DPDCH equal to 256.
- CEU Channel Estimation Unit
- the CEU unit receives at its input the channel symbols received after performing the operations of “descrambling”, “despreading” with the code of channelling DPCCH and integration.
- the first operation performed by the CEU unit is the multiplication of the received pilot symbols by the reference pilot symbols X Q (k).
- the reference pilot symbols are known to the receiver.
- the logic control unit 102 is a finite state machine (FSM) that performs a predefined sequence of operations, as a function of input parameter N PILOT (corresponding to the number of pilot symbols present in the current slot). For instance, in case of the interpolation method previously described with reference to FIG. 3 , the logic control unit 102 carries out the sequence of operations shown in the state diagram of FIG. 10 .
- FSM finite state machine
- the basic operation effected by the logic control unit 102 is divided into the following three steps:
- the computation of the arithmetic average of the two operands requires an addition and a division by two; the sum is effected in adder 108 and the division by two in block 110 which carries out a right-hand shift, discarding in practice the less significant bit (LSB) of the data resulting from adder 108 .
- LSB less significant bit
- M 2 The multiplying factor shown in FIG. 12 as M 2 is required to invert the sign of the quadrature component and to provide the complex conjugate of the channel estimations to the channel compensation unit (CCU).
- M2 is equal to +1 for the phase component and to a ⁇ 1 for the quadrature component.
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- Mobile Radio Communication Systems (AREA)
- Eye Examination Apparatus (AREA)
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Abstract
Description
Nb·Nf·Nu/Ts=400·8·128/666·10−6=615 Mbit/s
X=A=2
Y=B=10
C I(6)=[C I(2)+C I(10)]/2
and
C Q(6)=[C Q(2)+C Q(10)]/2
X=2; Y=6
Z=FLOOR [(2+6)/2]=4
W=2·4−6=2
C I(4)=[C i(2)+C i(6)]/2
and
C Q(4)=[C Q(2)+C Q(6)]/2
X=2; Y=Z=4
Z=FLOOR [(2+4)/2]=3
W=2·3−4=2
C I(3)=[C I(2)+C I(4)]/2
and
C Q(3)=[C Q(2)+C Q(4)]/2
X=4; Y=6
Z=FLOOR [(4+6)/2]=5
W=2·5−6=4
C I(5)=[C I(4)+C I(6)]/2
and
C Q(5)=[C Q(4)+C Q(6)]/2
X=6; Y=10
Z=FLOOR [(6+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)[C Q(6)+C Q(10)]/2
X=6; Y=Z=8
Z=FLOOR [(6+8)/2]=7
W=2·7−8=6
C I(7)=[C I(6)+C I(8)]/2
and
C Q(7)=[C Q(6)+C Q(8)]/2
X=8; Y=10
Z=FLOOR [(8+10)/2]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=A (A=3)
Y=B (B=10)
C I(6)=[C I(2)+C I(10)]/2
and
C Q(6)=[C Q(2)+C Q(10)]/2
X=3; Y=6
Z=FLOOR [(3+6)/2]=4
W=2·4−6=2
C I(4)=[C I(2)+C I(6)]/2
and
C Q(4)=[C Q(2)+C Q(6)]/2
X=4; Y=6
Z=FLOOR [(4+6)/2]=5
W=2·5−6=4
C I(5)=[C I(4)+C I(6)]/2
and
C Q(5)=[C Q(4)+C Q(6)]/2
X=6; Y=10
Z=FLOOR [(6+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)=[C Q(6)+C Q(10)]/2
X=6; Y=Z=8
Z=FLOOR [(6+8)/]=7
W=2·7−8=6
C I(7)=[C I(6)+C I(8)]/2
and
C Q(7)=[C Q(6)+C Q(8)]/2
X=8; Y=10
Z=FLOOR [(8+10)/]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=4; Y=10
Z=FLOOR [(4+10)/2]=7
W=2·7−10=4
C I(7)=[C I(4)+C I(10)]/2
and
C Q(7)=[C Q(4)+C Q(10)]/2
X=4; Y=7
Z=FLOOR [(4+7)/2]=5
W=2·5−7=3
C I(5)=[C I(3)+C I(7)]/2
and
C Q(5)=[C Q(3)+C Q(7)]/2
X=5; Y=7
Z=FLOOR [(5+7)/2]=6
W=2·6−7=5
C I(6)=[C I(5)+C I(7)]/2
and
C Q(6)=[C Q(5)+C Q(7)]/2
X=7; Y=10
Z=FLOOR [(7+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)=[C Q(6)+C Q(10)]/2
X=8; Y=10
Z=FLOOR [(8+10)/2]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=5; Y=10
Z=FLOOR [(5+10)/2]=7
W=2·7−10=4
C I(7)=[C I(4)+C I(10)]/2
and
C Q(7)=[C Q(4)+C Q(10)]/2
X=5; Y=7
Z=FLOOR [(5+7)/2]=6
W=2·6−7=5
C I(6)=[C I(5)+C I(7)]/2
and
C Q(6)=[C Q(5)+C Q(7)]/2
X=7; Y=10
Z=FLOOR [(7+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)=[C Q(6)+C Q(10)]/2
X=8; Y=10
Z=FLOOR [(8+10)/2]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=6; Y=10
Z=FLOOR [(6+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)=[C Q(6)+C Q(10)]/2
X=6; Y=8
Z=FLOOR [(6+8)/2]=7
W=2·7−8=6
C I(7)=[C I(6)+C I(8)]/2
and
C Q(7)=[C Q(6)+C Q(8)]/2
X=8; Y=10
Z=FLOOR [(8+10)/2]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=6; Y=10
Z=FLOOR [(6+10)/2]=8
W=2·8−10=6
C I(8)=[C I(6)+C I(10)]/2
and
C Q(8)=[C Q(6)+C Q(10)]/2
X=8; Y=10
Z=FLOOR [(8+10)/2]=9
W=2·9−10=8
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=A=5; Y=B=10
Z=CEIL [(5+10)/2]=8
W=2·8−5=11
C I(8)=[C I(5)+C I(11)]/2
and
C Q(8)=[C Q(5)+C Q(11)]/2
X=8; Y=10
Z=CEIL [(8+10)/2]=9
W=2·9−8=10
C I(9)=[C I(8)+C I(10)]/2
and
C Q(9)=[C Q(8)+C Q(10)]/2
X=5; Y=8
Z=CEIL [(5+8)/2]=7
W=2·7−5=9
C I(7)=[C I(5)+C I(9)]/2
and
C Q(7)=[C Q(5)+C Q(9)]/2
X=5; Y=7
Z=FLOOR [(5+7)/2]=6
W=2·6−5=7
C I(6)=[C I(5)+C I(7)]/2
and
C Q(6)=[C Q(5)+C Q(7)]/2
CL I =C I(2)/2+[C I(0)+C I(1)]/4
CL Q =C Q(2)/2+[C Q(0)+C Q(1)]/4,
and the result is assigned to coefficient C(2):
CI(2)=CLI
CQ(2)=CLQ
CL I =C I(1)/2+[C I(0)+C I(2)]/4
CL Q =C Q(1)/2+[C Q(0)+C Q(2)]/4
CI(1)=CLI
CQ(1)=CLQ
CL I =C I(10)/2+[C I(11)+C I(12)]/4
CL Q =C Q(10)/2+[C Q(11)+C Q(12)]/4,
and then assigned to coefficient C(10)
CI(10)=CLI
CQ(10)=CLQ
-
- reading the first operand from
memory 100 and loading it into thefirst register 104; - reading the second operand from
memory 100 and loading it into thesecond register 106; - writing the arithmetic average of the two operands into
memory 100 through its Input_port_1.
- reading the first operand from
Claims (19)
C I(6)=[C I(2)+C I(10)]/2; C Q(6)=[C Q(2)+C Q(10)]/2;
C I(4)=[C I(2)+C I(6)]/2; C Q(4)=[C Q(2)+C Q(6)]/2;
C I(3)=[C I(2)+C I(4)]/2; C Q(3)=[C Q(2)+C Q(4)]/2;
C I(5)=[C I(4)+C I(6)]/2; C Q(5)=[C Q(4)+C Q(6)]/2;
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(7)=[C I(6)+C I(8)]/2; C Q(7)=[C Q(6)+C Q(8)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
C I(6)=[C I(2)+C I(10)]/2; C Q(6)=[C Q(2)+C Q(10)]/2;
C I(4)=[C I(2)+C I(6)]/2; C Q(4)=[C Q(2)+C Q(6)]/2;
C I(5)=[C I(4)+C I(6)]/2; C Q(5)=[C Q(4)+C Q(6)]/2;
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(7)=[C I(6)+C I(8)]/2; C Q(7)=[C Q(6)+C Q(8)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
C I(7)=[C I(4)+C I(10)]/2; C Q(7)=[C Q(4)+C Q(10)]/2;
C I(5)=[C I(3)+C I(7)]/2; C Q(5)=[C Q(3)+C Q(7)]/2;
C I(6)=[C I(5)+C I(7)]/2; C Q(6)=[C Q(5)+C Q(7)]/2;
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
C I(7)=[C I(4)+C I(10)]/2; C Q(7)=[C Q(4)+C Q(10)]/2;
C I(6)=[C I(5)+C I(7)]/2; C Q(6)=[C Q(5)+C Q(7)]/2;
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(7)=[C I(6)+C I(8)]/2; C Q(7)=[C Q(6)+C Q(8)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
C I(8)=[C I(6)+C I(10)]/2; C Q(8)=[C Q(6)+C Q(10)]/2;
C I(9)=[C I(8)+C I(10)]/2; C Q(9)=[C Q(8)+C Q(10)]/2.
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Application Number | Priority Date | Filing Date | Title |
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EP02425177.9 | 2002-03-21 | ||
EP02425177A EP1347608B1 (en) | 2002-03-21 | 2002-03-21 | Interpolation for use in channel estimation |
PCT/EP2003/002773 WO2003081862A1 (en) | 2002-03-21 | 2003-03-17 | Interpolation for use in channel estimation |
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US7450663B2 true US7450663B2 (en) | 2008-11-11 |
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EP (1) | EP1347608B1 (en) |
CN (1) | CN1647472A (en) |
AT (1) | ATE408291T1 (en) |
AU (1) | AU2003219066A1 (en) |
BR (1) | BR0303569A (en) |
CA (1) | CA2480074A1 (en) |
DE (1) | DE60228816D1 (en) |
WO (1) | WO2003081862A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090262944A1 (en) * | 2006-03-31 | 2009-10-22 | Golitschek Edler Von Elbwart A | Scrambling of data and reference symbols |
Families Citing this family (3)
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KR100630043B1 (en) * | 2003-11-06 | 2006-09-27 | 삼성전자주식회사 | Frequency error detector and frequency error combiner for receiver in a mobile communication system |
US8996309B2 (en) | 2007-07-21 | 2015-03-31 | Aspen Avionics, Inc. | Apparatus and method to indicate instrument saturation |
EP2167917B1 (en) * | 2007-07-21 | 2015-03-11 | Peter Lyons | Apparatus and method to indicate course deviation instrument saturation |
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2002
- 2002-03-21 EP EP02425177A patent/EP1347608B1/en not_active Expired - Lifetime
- 2002-03-21 AT AT02425177T patent/ATE408291T1/en not_active IP Right Cessation
- 2002-03-21 DE DE60228816T patent/DE60228816D1/en not_active Expired - Lifetime
-
2003
- 2003-03-17 CA CA002480074A patent/CA2480074A1/en not_active Abandoned
- 2003-03-17 WO PCT/EP2003/002773 patent/WO2003081862A1/en not_active Application Discontinuation
- 2003-03-17 AU AU2003219066A patent/AU2003219066A1/en not_active Abandoned
- 2003-03-17 BR BR0303569-7A patent/BR0303569A/en not_active IP Right Cessation
- 2003-03-17 US US10/508,928 patent/US7450663B2/en not_active Expired - Fee Related
- 2003-03-17 CN CNA038089416A patent/CN1647472A/en active Pending
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US5875215A (en) * | 1995-08-25 | 1999-02-23 | Nec Corporation | Carrier synchronizing unit |
US5903280A (en) * | 1996-05-30 | 1999-05-11 | Nec Corporation | Image display apparatus that reduces necessary memory capacity for operation |
US5886911A (en) | 1997-01-29 | 1999-03-23 | Winbond Electronics Corp. | Fast calculation method and its hardware apparatus using a linear interpolation operation |
EP0912019A2 (en) | 1997-10-22 | 1999-04-28 | Telital S.p.A. | Probe sequences intercalating method with information data for the estimation of communication channel characteristics and correct reception of data sequences |
EP1032168A2 (en) | 1999-02-22 | 2000-08-30 | Lucent Technologies Inc. | Channel estimation, using interpolation based on Lagrange polynomials |
US6141393A (en) * | 1999-03-03 | 2000-10-31 | Motorola, Inc. | Method and device for channel estimation, equalization, and interference suppression |
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US20090262944A1 (en) * | 2006-03-31 | 2009-10-22 | Golitschek Edler Von Elbwart A | Scrambling of data and reference symbols |
Also Published As
Publication number | Publication date |
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WO2003081862A1 (en) | 2003-10-02 |
DE60228816D1 (en) | 2008-10-23 |
EP1347608A1 (en) | 2003-09-24 |
BR0303569A (en) | 2004-04-20 |
AU2003219066A1 (en) | 2003-10-08 |
ATE408291T1 (en) | 2008-09-15 |
US20050153701A1 (en) | 2005-07-14 |
EP1347608B1 (en) | 2008-09-10 |
CA2480074A1 (en) | 2003-10-02 |
CN1647472A (en) | 2005-07-27 |
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