US7152177B2 - Microcomputer and computer system - Google Patents
Microcomputer and computer system Download PDFInfo
- Publication number
- US7152177B2 US7152177B2 US09/939,751 US93975101A US7152177B2 US 7152177 B2 US7152177 B2 US 7152177B2 US 93975101 A US93975101 A US 93975101A US 7152177 B2 US7152177 B2 US 7152177B2
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- US
- United States
- Prior art keywords
- oscillation
- signal
- wakeup
- circuit
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 186
- 230000006870 function Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- 230000007704 transition Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
Definitions
- the present invention relates to a microcomputer and a computer system. More particularly, this invention relates to a one-chip microcomputer, for example used in vehicles, and having a stop releasing function for prime oscillation. This invention also relates to a computer system that uses such a microcomputer.
- deadlock there is a state known as deadlock as an abnormal operation in the microcomputer.
- prime oscillation is stopped unexpectedly and the operation mode shifted from run to stop due to the generation of broken data in some latch circuits.
- the broken data is generated because of sudden changes in supply voltage or influence of external noise etc.
- the CPU has no control on the occurrence of the deadlock.
- One-chip microcomputer are used in vehicles for controlling electronic equipment. It is very important to provide a fail safe function in such microcomputers to prevent generation of a deadlock.
- an external reset function to realize the fail safe function.
- a reset signal is input into a reset terminal of the microcomputer from outside and the CPU is reset to initial state.
- an external interrupt function or non-maskable interrupt (NMI) function to realize the fail safe function.
- an interrupt requesting signal is input into an external interrupt (INT) terminal or a non-maskable terminal of the microcomputer from outside. As a consequence, an interrupt occurs, and an interrupt processing is executed.
- the microcomputer comprises an oscillation circuit which oscillates and outputs an oscillation signal and stops the oscillation during a period in which it receives an oscillation stop signal; a wakeup terminal that receives from outside a wakeup signal of a predetermined cycle; and a clock control circuit which receives the wakeup signal, outputs the oscillation stop signal, and stops output of the oscillation stop signal based on the wakeup signal.
- the oscillation signal is supplied from the oscillation circuit to the clock control circuit.
- the clock control circuit generates a main clock signal based on the oscillation signal. Moreover, in normal state of run, the clock control circuit ignores the wakeup signal in order not to affect its operation state.
- the clock control circuit supplies an oscillation stop signal to the oscillation circuit, thereby the oscillation circuit stops oscillation.
- the clock control circuit forces the oscillation stop signal to release.
- the oscillation stop signal is released, the oscillation circuit resumes oscillation.
- the microcomputer becomes normal state of run through state of oscillation stability wait.
- the computer system comprises the above-mentioned microcomputer and a wakeup signal supplying unit that supplies the wakeup signal on predetermined cycle constantly.
- FIG. 1 is a block diagram showing a main section of the microcomputer of the embodiment of the present invention.
- FIG. 2 is a state transition diagram for explaining the transition of operation state of the microcomputer of the embodiment of the present invention
- FIG. 3 is a block diagram showing a main section of the microcomputer of a first embodiment of the present invention.
- FIG. 4 is a state transition diagram for explaining the transition of operation state of the microcomputer of the first embodiment
- FIG. 5 is a block diagram showing a main section of the microcomputer of a second embodiment of the present invention.
- FIG. 6 is a state transition diagram for explaining the transition of operation state of the microcomputer of the second embodiment
- FIG. 7 is a block diagram showing a main section of the microcomputer of a third embodiment of the present invention.
- FIG. 8 is a state transition diagram for explaining the transition of operation state of the microcomputer of the third embodiment.
- FIG. 1 is a block diagram showing required sections of the microcomputer according to an embodiment of the present invention.
- FIG. 2 is a state transition diagram of the microcomputer.
- the microcomputer has the wakeup terminal 11 to which the wakeup signal 21 is supplied from outside on suitable cycle. The wakeup signal 21 is then supplied to the clock control circuit 12 .
- a not shown oscillator is connected with the oscillation circuit 13 through oscillation terminals 14 , 15 shown by X 0 , X 1 .
- the oscillation signal (HCLK) 22 is supplied from the oscillation circuit 13 to the clock control circuit 12 .
- the clock control circuit 12 generates the main clock signal 23 based on the oscillation signal 22 to supply the signal 23 to various circuits (not shown) in the microcomputer.
- the clock control circuit 12 ignores the wakeup signal 21 in order not to affect its operation state.
- the clock control circuit 12 supplies the oscillation stop signal 26 (KLHI) to the oscillation circuit 13 , thereby the oscillation circuit 13 stops oscillation.
- the clock control circuit 12 forces the oscillation stop signal 26 to release.
- the oscillation stop signal 26 is released, the oscillation circuit 13 resumes oscillation.
- the microcomputer becomes normal state of run through state of oscillation stability wait.
- the microcomputer executes interrupt processing when the interrupt requesting signal 24 is supplied to the interrupt control circuit 17 from outside through the external interrupt (INT) terminal 16 .
- the microcomputer returns to initial state when the reset signal 25 is supplied from outside through the reset (RSTX) terminal 18 .
- FIG. 3 is a block diagram showing only required sections of the microcomputer according to a first embodiment of the present embodiment.
- FIG. 4 is a state transition diagram of the microcomputer according to the first embodiment.
- the microcomputer 1 shown in FIG. 3 has the same configuration as the microcomputer shown in FIG. 1 , therefore, repetition of explanation will be omitted.
- the oscillator 2 is connected with oscillation terminals 14 , 15 .
- the oscillator 2 is a crystal oscillator whose oscillation frequency is 4 MHz, for example.
- the wakeup signal supplying unit 3 is connected with the wakeup terminal 11 .
- the wakeup signal supplying unit 3 always generates H level signal whose potential level is relatively high by constant cycle, for example, 4 sec. to supply it to the wakeup terminal 11 .
- the signal input from the wakeup terminal 11 is supplied to the clock control circuit 12 as the wakeup signal 21 .
- the oscillator 2 and the wakeup signal supplying unit 3 are arranged out of the microcomputer 1 .
- the external interrupt terminal, the interrupt control circuit and the reset terminal are not shown and omitted.
- the clock control circuit 12 ignores the input the wakeup signal 21 in normal state of run, that is, in state in which the oscillation signal 22 is supplied from the oscillation circuit 13 . Thus, even if the wakeup signal 21 is input into the clock control circuit 12 in normal state of run, state of the microcomputer 1 dose not change, and it is not transited to state of stop.
- the clock control circuit 12 supplies the oscillation stop signal 26 to the oscillation circuit 13 .
- the oscillation stop signal 26 By input of the oscillation stop signal 26 , the oscillation circuit 13 stops oscillation, and the microcomputer 1 transits to state of stop. At this time, internal register value is held as it is, thereby state of Input/Output is stored.
- the clock control circuit 12 comprises function that the circuit 12 forces the oscillation stop signal 26 to release when the wakeup signal 21 is input at the time of state of stop.
- the oscillation stop signal 26 is released forcedly, and the oscillation circuit 13 resumes oscillation.
- the microcomputer 1 After resumption of oscillation, the microcomputer 1 returns to normal state of run through state of oscillation stability wait and resumes processing from the following instruction of the instruction executed just before state of stop using register value which has been held when stopping.
- the clock control circuit 12 forces the oscillation stop signal 26 to release based on input of the wakeup signal 21 in state of stop, the oscillation circuit 13 resumes oscillation speedily even if it is transited from normal state of run to state of stop with external interrupt request prohibited. Therefore, since state of stop of prime oscillation can be released by only hardware without software, state of deadlock can be avoided.
- FIG. 5 is a block diagram showing a main section of the microcomputer according to a second embodiment of the present embodiment.
- FIG. 6 is a state transition diagram of the microcomputer according to the second embodiment.
- the second embodiment differs from the first embodiment in that a microcomputer 101 according to the second embodiment is constituted so that the signal of H level supplied from the wakeup signal supplying unit 3 is supplied to the clock control circuit 12 as the wakeup signal 21 and also to the interrupt control circuit 17 through the external interrupt terminal 16 as the interrupt requesting signal 24 .
- the same reference letters are added with respect to the same constitution as the first embodiment and description about them is omitted.
- the oscillation stop signal 26 is released forcedly by input of the wakeup signal 21 and the oscillation circuit 13 resume so scillation.
- the interrupt requesting signal 24 is input into the interrupt control circuit 17 , for example, leading edge of the interrupt requesting signal 24 is detected, thereby interrupt is created, and then after state of oscillation stability wait the CPU not shown executes interrupt processing.
- the oscillation circuit 13 resumes oscillation speedily even if it is transited from normal state of run to state of stop.
- the interrupt request signal 24 is supplied to the interrupt control circuit 17 , if prime oscillation is resumed from state that it is transited to state of stop after permission of external interrupt request, the microcomputer 101 executes interrupt processing. Therefore, since state of stop of prime oscillation can be released and interrupt processing can be executed by only hardware without software, state of deadlock can be avoided.
- FIG. 7 is a block diagram showing a main section of the microcomputer according to a third embodiment of the present embodiment.
- FIG. 8 is a state transition diagram of the microcomputer according to the third embodiment.
- the third embodiment differs from the first embodiment in that a microcomputer 201 according to the third embodiment comprises an address generating circuit 19 outputting predetermined address and is constituted so that the signal of H level supplied from the wakeup signal supplying unit 3 is supplied to the clock control circuit 12 as the wakeup signal 21 and also to the address generating circuit 19 .
- the same reference letters are added with respect to the same constitution as the first embodiment and description about them is omitted.
- the oscillation stop signal 26 is released forcedly by input of the wakeup signal 21 and the oscillation circuit 13 resumes oscillation.
- the microcomputer 201 is transited to state of oscillation stability wait.
- the address generating circuit 19 outputs specific address set beforehand, for example, FFA000h. Then, after state of oscillation stability wait, the CPU not shown executes processing from instruction in memory space of FFA000h.
- the oscillation circuit 13 resumes oscillation speedily even if it is transited from normal state of run to state of stop with external interrupt request prohibited.
- specific address is output from the address generating circuit 19 , the microcomputer 201 executes processing from instruction in memory space corresponding to its address. Therefore, since state of stop of prime oscillation can be released by only hardware without software and processing can be executed from instruction in memory space of specific address, state of deadlock can be avoided.
- the invention is not limited to the specific embodiments thereof and various changes and modifications may be made in the invention.
- the present invention may be applied to not only one-chip microcomputer but also a microcomputer carried on the same LSI package, one-board microcomputer and system microcomputer.
- the address generating circuit 19 may be arranged outside the microcomputer 201 .
- state of stop of prime oscillation can be released by only hardware without software. Therefore, a microcomputer having a fail safe function that prevents generation of deadlock can be obtained.
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001035177A JP3913991B2 (en) | 2001-02-13 | 2001-02-13 | Microcomputer and computer system |
JP2001-035177 | 2001-02-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020112192A1 US20020112192A1 (en) | 2002-08-15 |
US7152177B2 true US7152177B2 (en) | 2006-12-19 |
Family
ID=18898656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/939,751 Expired - Lifetime US7152177B2 (en) | 2001-02-13 | 2001-08-28 | Microcomputer and computer system |
Country Status (2)
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US (1) | US7152177B2 (en) |
JP (1) | JP3913991B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9354681B2 (en) * | 2013-06-28 | 2016-05-31 | Intel Corporation | Protected power management mode in a processor |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101233A (en) | 1981-12-10 | 1983-06-16 | Japan Electronic Control Syst Co Ltd | Fuel cutoff method of electronic control fuel injection device |
JPS63157254A (en) | 1986-12-20 | 1988-06-30 | Fujitsu Ltd | Single chip microcomputer |
JPS63211417A (en) | 1987-02-27 | 1988-09-02 | Nec Corp | Microcomputer |
JPH03278210A (en) | 1990-03-28 | 1991-12-09 | Nec Corp | Microcomputer |
JPH03282804A (en) | 1990-03-30 | 1991-12-13 | Nec Corp | Microcomputer |
JPH06195160A (en) | 1992-12-24 | 1994-07-15 | Fujitsu Ltd | External interruption edge detecting circuit for microcomputer |
US5392437A (en) * | 1992-11-06 | 1995-02-21 | Intel Corporation | Method and apparatus for independently stopping and restarting functional units |
JPH0863451A (en) | 1994-08-25 | 1996-03-08 | Mitsubishi Denki Semiconductor Software Kk | Microcomputer |
US5546588A (en) * | 1992-05-08 | 1996-08-13 | Motorola Inc. | Method and apparatus for preventing a data processing system from entering a non-recoverable state |
JPH10133714A (en) | 1996-10-29 | 1998-05-22 | Mitsubishi Electric Corp | Integrated circuit device |
US5886582A (en) * | 1996-08-07 | 1999-03-23 | Cypress Semiconductor Corp. | Enabling clock signals with a phase locked loop (PLL) lock detect circuit |
JPH11338572A (en) * | 1998-05-22 | 1999-12-10 | Mitsubishi Electric Corp | Clock generator |
US6085325A (en) * | 1996-12-16 | 2000-07-04 | Intel Corporation | Method and apparatus for supporting power conservation operation modes |
-
2001
- 2001-02-13 JP JP2001035177A patent/JP3913991B2/en not_active Expired - Fee Related
- 2001-08-28 US US09/939,751 patent/US7152177B2/en not_active Expired - Lifetime
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101233A (en) | 1981-12-10 | 1983-06-16 | Japan Electronic Control Syst Co Ltd | Fuel cutoff method of electronic control fuel injection device |
JPS63157254A (en) | 1986-12-20 | 1988-06-30 | Fujitsu Ltd | Single chip microcomputer |
JPS63211417A (en) | 1987-02-27 | 1988-09-02 | Nec Corp | Microcomputer |
JPH03278210A (en) | 1990-03-28 | 1991-12-09 | Nec Corp | Microcomputer |
JPH03282804A (en) | 1990-03-30 | 1991-12-13 | Nec Corp | Microcomputer |
US5546588A (en) * | 1992-05-08 | 1996-08-13 | Motorola Inc. | Method and apparatus for preventing a data processing system from entering a non-recoverable state |
US5392437A (en) * | 1992-11-06 | 1995-02-21 | Intel Corporation | Method and apparatus for independently stopping and restarting functional units |
JPH06195160A (en) | 1992-12-24 | 1994-07-15 | Fujitsu Ltd | External interruption edge detecting circuit for microcomputer |
JPH0863451A (en) | 1994-08-25 | 1996-03-08 | Mitsubishi Denki Semiconductor Software Kk | Microcomputer |
US5886582A (en) * | 1996-08-07 | 1999-03-23 | Cypress Semiconductor Corp. | Enabling clock signals with a phase locked loop (PLL) lock detect circuit |
JPH10133714A (en) | 1996-10-29 | 1998-05-22 | Mitsubishi Electric Corp | Integrated circuit device |
US6085325A (en) * | 1996-12-16 | 2000-07-04 | Intel Corporation | Method and apparatus for supporting power conservation operation modes |
JPH11338572A (en) * | 1998-05-22 | 1999-12-10 | Mitsubishi Electric Corp | Clock generator |
Also Published As
Publication number | Publication date |
---|---|
US20020112192A1 (en) | 2002-08-15 |
JP2002236675A (en) | 2002-08-23 |
JP3913991B2 (en) | 2007-05-09 |
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