US6534341B2 - Methods of wafer level fabrication and assembly of chip scale packages - Google Patents
Methods of wafer level fabrication and assembly of chip scale packages Download PDFInfo
- Publication number
- US6534341B2 US6534341B2 US09/920,970 US92097001A US6534341B2 US 6534341 B2 US6534341 B2 US 6534341B2 US 92097001 A US92097001 A US 92097001A US 6534341 B2 US6534341 B2 US 6534341B2
- Authority
- US
- United States
- Prior art keywords
- glass
- semiconductor wafer
- wafer substrate
- plate
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
Images
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
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- H01L2924/14—Integrated circuits
Abstract
Description
Claims (57)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/920,970 US6534341B2 (en) | 1998-05-21 | 2001-08-02 | Methods of wafer level fabrication and assembly of chip scale packages |
US10/357,656 US6787394B2 (en) | 1998-05-21 | 2003-02-03 | Methods of wafer level fabrication and assembly of chip scale packages |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/082,745 US6008070A (en) | 1998-05-21 | 1998-05-21 | Wafer level fabrication and assembly of chip scale packages |
US09/388,033 US6284573B1 (en) | 1998-05-21 | 1999-09-01 | Wafer level fabrication and assembly of chip scale packages |
US09/920,970 US6534341B2 (en) | 1998-05-21 | 2001-08-02 | Methods of wafer level fabrication and assembly of chip scale packages |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/388,033 Continuation US6284573B1 (en) | 1998-05-21 | 1999-09-01 | Wafer level fabrication and assembly of chip scale packages |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/357,656 Continuation US6787394B2 (en) | 1998-05-21 | 2003-02-03 | Methods of wafer level fabrication and assembly of chip scale packages |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020001922A1 US20020001922A1 (en) | 2002-01-03 |
US6534341B2 true US6534341B2 (en) | 2003-03-18 |
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Application Number | Title | Priority Date | Filing Date |
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US09/082,745 Expired - Lifetime US6008070A (en) | 1998-05-21 | 1998-05-21 | Wafer level fabrication and assembly of chip scale packages |
US09/208,906 Expired - Lifetime US6326697B1 (en) | 1998-05-21 | 1998-12-10 | Hermetically sealed chip scale packages formed by wafer level fabrication and assembly |
US09/388,033 Expired - Lifetime US6284573B1 (en) | 1998-05-21 | 1999-09-01 | Wafer level fabrication and assembly of chip scale packages |
US09/920,970 Expired - Fee Related US6534341B2 (en) | 1998-05-21 | 2001-08-02 | Methods of wafer level fabrication and assembly of chip scale packages |
US10/357,656 Expired - Fee Related US6787394B2 (en) | 1998-05-21 | 2003-02-03 | Methods of wafer level fabrication and assembly of chip scale packages |
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US09/082,745 Expired - Lifetime US6008070A (en) | 1998-05-21 | 1998-05-21 | Wafer level fabrication and assembly of chip scale packages |
US09/208,906 Expired - Lifetime US6326697B1 (en) | 1998-05-21 | 1998-12-10 | Hermetically sealed chip scale packages formed by wafer level fabrication and assembly |
US09/388,033 Expired - Lifetime US6284573B1 (en) | 1998-05-21 | 1999-09-01 | Wafer level fabrication and assembly of chip scale packages |
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Application Number | Title | Priority Date | Filing Date |
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US10/357,656 Expired - Fee Related US6787394B2 (en) | 1998-05-21 | 2003-02-03 | Methods of wafer level fabrication and assembly of chip scale packages |
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US (5) | US6008070A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030139021A1 (en) * | 1998-05-21 | 2003-07-24 | Farnworth Warren M. | Methods of wafer level fabrication and assembly of chip scale packages |
US6670206B2 (en) * | 2001-12-07 | 2003-12-30 | Samsung Electro-Mechanics Co., Ltd. | Method for fabricating surface acoustic wave filter packages |
US20060024900A1 (en) * | 2004-07-29 | 2006-02-02 | Lee Teck K | Interposer including at least one passive element at least partially defined by a recess formed therein, method of manufacture, system including same, and wafer-scale interposer |
US20060113639A1 (en) * | 2002-10-15 | 2006-06-01 | Sehat Sutardja | Integrated circuit including silicon wafer with annealed glass paste |
US7067397B1 (en) | 2005-06-23 | 2006-06-27 | Northrop Gruman Corp. | Method of fabricating high yield wafer level packages integrating MMIC and MEMS components |
US20060255457A1 (en) * | 2002-10-15 | 2006-11-16 | Sehat Sutardja | Integrated circuit package with glass layer and oscillator |
US20070176705A1 (en) * | 2002-10-15 | 2007-08-02 | Sehat Sutardja | Crystal oscillator emulator |
US20070176690A1 (en) * | 2002-10-15 | 2007-08-02 | Sehat Sutardja | Crystal oscillator emulator |
US20070188254A1 (en) * | 2002-10-15 | 2007-08-16 | Sehat Sutardja | Crystal oscillator emulator |
US20080006931A1 (en) * | 2006-07-06 | 2008-01-10 | Micron Technology, Inc. | Semiconductor constructions and assemblies, electronic systems, and methods of forming semiconductor constructions and assemblies |
Families Citing this family (128)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Also Published As
Publication number | Publication date |
---|---|
US6787394B2 (en) | 2004-09-07 |
US6008070A (en) | 1999-12-28 |
US6326697B1 (en) | 2001-12-04 |
US20030139021A1 (en) | 2003-07-24 |
US20020001922A1 (en) | 2002-01-03 |
US6284573B1 (en) | 2001-09-04 |
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