US6378058B1 - Method of and apparatus for processing information, and providing medium - Google Patents
Method of and apparatus for processing information, and providing medium Download PDFInfo
- Publication number
- US6378058B1 US6378058B1 US09/339,220 US33922099A US6378058B1 US 6378058 B1 US6378058 B1 US 6378058B1 US 33922099 A US33922099 A US 33922099A US 6378058 B1 US6378058 B1 US 6378058B1
- Authority
- US
- United States
- Prior art keywords
- logical address
- address
- logical
- physical
- determining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
Definitions
- the present invention relates to a method of and an apparatus for processing information, and a providing medium, and more particularly to a method of and an apparatus for processing information to be able to associate one logical address with numbers of bits making up one word on a physical address for reading and writing words made up of different numbers of bits according to common address management, and a providing medium for providing a program and/or data to carry out such a method.
- Information processing apparatus e.g., personal computers, require a large-scale main memory for storing a program if the program is large in size.
- main memory e.g., main memory having a storage capacity large enough to store a large program may not necessarily be available.
- One solution to the above problems is to use a virtual memory that produces an apparent storage space larger than the storage space of a main memory.
- the user can use the virtual memory as if the apparent storage space were actually present for data storage.
- Addresses used by the virtual memory are referred to as virtual addresses or logical addresses. Addresses used by the main memory are referred to as real addresses or physical addresses.
- FIG. 6 of the accompanying drawings shows a conventional information processing apparatus.
- a process of converting a logical address into a physical address when a controller 70 reads data stored in a main memory 74 will be described below with reference to FIG. 6 .
- the number of bits of each word of data handled by the controller 70 is fixed to “16”, for example. Even with the fixed number of bits assigned to each word, it is possible that 16 bits are treated as one word, 8 bits as half word, and 32 bits as double word.
- Each word of data handled by the main memory 74 is also fixed to a certain number of bits, though the main memory 74 is also capable of treating different numbers of bits.
- the controller 70 When the controller 70 reads data stored in the main memory 74 , the controller 70 outputs a logical address to a bit decision unit 71 , which determines the type of data that the entered logical address belongs to, i.e., how many bits make up one word of data that the entered logical address belongs to.
- the bit decision unit 71 then outputs the result of the decision and the logical address to a mode converter 72 .
- the mode converter 72 selects a mode (program) for converting a logical address into a physical address. If the bit decision unit 71 determines that one word is made up of 32 bits, then the mode converter 72 selects a 32-bit mode. If the bit decision unit 71 determines that one word is made up of 16 bits, then the mode converter 72 selects a 16-bit mode.
- an address indicator 73 calculates a physical address using the selected mode and the logical address, and supplies the calculated physical address to the main memory 74 .
- the main memory 74 reads data at the supplied physical address and supplies the data to the controller 70 .
- the logical address is converted into the physical address after the mode corresponding to the number of bits of one word of data that the logical address belongs to has been selected.
- the conventional information processing apparatus needs to change modes for reading data from physical addresses based on logical addresses, and cannot quickly generate physical addresses from logical addresses.
- FIG. 1 is a block diagram of an entertainment system which incorporates an information processing apparatus according to the present invention
- FIG. 2 is a block diagram of the information processing apparatus
- FIG. 3 is a diagram illustrative of a logical address space and a physical address space
- FIG. 4 is a table held by an address converter
- FIG. 5 is a flowchart of an operation sequence of the information processing apparatus shown in FIG. 2;
- FIG. 6 is a block diagram of a conventional information processing apparatus.
- An information processing apparatus comprises input means (e.g., step S 1 in FIG. 5) for entering a logical address, decision means (e.g., steps S 2 , S 4 , S 6 in FIG. 5) for deciding a base address of the logical address entered by the input means, and determining means (e.g., step S 9 in FIG. 5) for determining a physical address corresponding to the logical address based on the base address decided by the decision means.
- input means e.g., step S 1 in FIG. 5
- decision means e.g., steps S 2 , S 4 , S 6 in FIG.
- determining means e.g., step S 9 in FIG. 5
- FIG. 1 shows in block form an entertainment system which incorporates the information processing apparatus according to the present invention.
- a media processor 60 is connected to a host CPU (Central Processing Unit) 57 by a host bus 55 .
- the media processor 60 comprises a processor that can be constructed as one chip.
- the media processor 60 has a host interface 1 comprising an FIFO (First-In, First-Out) memory 31 , a register 32 , and a direct path 33 , which are connected to the host bus 55 .
- FIFO First-In, First-Out
- the media processor 60 has a CPU bus 11 to which there are connected the register 32 , the direct path 33 , a CPU 3 , an instruction cache 6 , an SRAM (Static Random-Access Memory) 7 , and a bit converter 10 .
- the media processor 60 also has a main bus 12 to which there are connected the FIFO memory 31 , a bus arbiter 2 , the instruction cache 6 , the SRAM 7 , the bit converter 10 , a DMAC (Direct Memory Access Controller) 4 , a DRAM (Dynamic Random-Access Memory) 5 , and DSPs (Digital Signal Processors) 8 - 1 , 8 - 2 .
- DMAC Direct Memory Access Controller
- DRAM Dynamic Random-Access Memory
- DSPs Digital Signal Processors
- the host CPU 57 performs various processing operations according to a program stored in a memory (not shown). For example, the host CPU 57 reads programs and data from a recording medium such as a CD-ROM (Compact Disk—Read-Only Memory), not shown, and stores the read programs and data into the DRAM 5 , and fetches stored programs and data from the DRAM 5 . At this time, the host CPU 57 requests the DMAC 4 to perform DMA transfer of data between the FIFO memory 31 and the DRAM 5 . The host CPU 57 is also capable of directly accessing the DRAM 5 and other units via the direct path 33 .
- a recording medium such as a CD-ROM (Compact Disk—Read-Only Memory)
- the bus arbiter 2 serves to coordinate use of the main bus 12 . For example, when the host CPU 57 sends a request for data transfer to the DMAC 4 , the bus arbiter 2 grants the DMAC 4 exclusive use of the main bus 12 so that DMA data transfer can be performed from the host CPU 57 to the DRAM 5 .
- the FIFO memory 31 temporarily stores data outputted from the host CPU 57 and outputs the stored data via the main bus 12 to the DRAM 5 , and also temporarily stores data transferred from the DRAM 5 and outputs the stored data to the host CPU 57 .
- the register 32 is a register used when handshaking takes place between the host CPU 57 and the CPU 3 , and stores commands and data representing processing statuses.
- the CPU 3 accesses the instruction cache 6 , loads a program stored therein, executes the program, and, if necessary, accesses the SRAM 7 and is supplied with certain data therefrom. If necessary data is not stored in the SRAM 7 , then the CPU 3 requests the DMAC 4 to perform DMA data transfer from the DRAM 5 to the SRAM 7 . If a necessary program is not stored in the instruction cache 6 , the CPU 3 reads the program from the DRAM 5 into the instruction cache 6 .
- the SRAM 7 can be accessed at arbitrary addresses from both the CPU 3 and the DMAC 4 at the same time for reading and writing data.
- the SRAM 7 comprises a dual-port SRAM and used as a data cache, for example.
- the SRAM 7 serves to store those of the data stored in the DRAM 5 which are accessed highly frequently from the CPU 3 .
- the SRAM 7 may be of a 2-bank memory arrangement, with one bank connected to the CPU bus 11 and the other bank to the main bus 12 .
- the instruction cache 6 is a memory cache whose arbitrary addresses can be accessed for reading a program therefrom.
- the instruction cache 6 serves to store those of the programs stored in the DRAM 5 which are accessed highly frequently from the CPU 3 .
- the bit converter 10 changes a bit width (e.g., 32 bits) of data entered via the CPU bus 11 to a bit width (e.g., 128 bits) matching the main bus 12 and outputs the data with the changed bit width, and also changes a bit width of data entered via the main bus 12 to a bit width matching the CPU bus 11 and outputs the data with the changed bit width.
- a bit width e.g., 32 bits
- a bit width e.g., 128 bits
- DSP 8 - 1 comprises a DSP Core 23 - 1 for executing a DSP program, a DMAC 20 - 1 for effecting DMA transfer of data required when the DSP Core 23 - 1 executes the program between the DSP Core 23 - 1 and the DRAM 5 , and an I/F (interface) 24 - 1 for transferring data between the DSP Core 23 - 1 and a circuit external to the media processor 60 .
- the DSP 8 - 1 For data transfer between the DSP Core 23 - 1 and the DRAM 5 , the DSP 8 - 1 requests the bus arbiter 2 for use of the main bus 12 . After the DSP 8 - 1 acquires the right to use the main bus 12 , DMA transfer of data is carried out by the DMAC 20 - 1 . When the DSP 8 - 1 addresses the DRAM 5 , a logic address generated by the DMAC 20 - 1 is converted by an address converter 21 - 1 into a physical address for the DRAM 5 .
- Data is read from the DRAM 5 into the DSP 8 - 1 via an FIFO memory 22 a - 1 and a read-data bit converter 22 b - 1 .
- the read-data bit converter 22 b - 1 serves to convert bit width (e.g., 128 bits) of data entered from the DRAM 5 via the main bus 12 into a bit width (e.g., 24 bits) matching the DSP 8 - 1 .
- Data is written from the DSP 8 - 1 into the DRAM 5 via a write-data bit converter 22 c - 1 and an FIFO memory 22 d - 1 .
- the write-data bit converter 22 c - 1 serves to convert a bit width matching the DSP 8 - 1 into a bit width of data outputted from the main bus 12 to the DRAM 5 .
- the FIFO memory 22 a - 1 allows data to be read from the DRAM 5 and to be written into the DSP 8 - 1 efficiently even in asynchronous operation.
- the FIFO memory 22 d - 1 allows data to be read from the DSP 8 - 1 and to be written into the DRAM 5 efficiently even in asynchronous operation.
- the I/F 24 - 1 is used to transfer audio data, for example, between the DSP 8 - 1 and a circuit external to the media processor 60 .
- Audio data generated by the DSP Core 23 - 1 is outputted via the I/F 24 - 1 from a multiplexer 9 , and supplied via a D/A converter 50 a and an output amplifier 50 b to a speaker 50 c .
- An audio signal entered from a microphone 51 a may be supplied via an input amplifier 51 b and an A/D converter 51 c to the multiplexer 9 , and entered via the I/F 24 - 1 to the DSP Core 23 - 1 . Which one of these processes is to be carried out is determined by the program executed by the DSP Core 23 - 1 .
- the media processor 60 also has a DSP 8 - 2 , an address converter 21 - 2 , an FIFO memory 22 a - 2 , a read-data bit converter 22 b - 2 , a write-data bit converter 22 c - 2 , and an FIFO memory 22 d - 2 , which are functionally and structurally identical to the DSP 8 - 1 , the address converter 21 - 1 , the FIFO memory 22 a - 1 , the read-data bit converter 22 b - 1 , the write-data bit converter 22 c -c, and the FIFO memory 22 d - 1 .
- the multiplexer 9 selects one of the DSP 8 - 1 and the DSP 8 - 2 , and connects the selected DSP to the D/A converter 50 a or the A/D converter 51 c .
- the D/A converter 50 a and the A/D converter 51 c can be connected to different DSPs (e.g., the D/A converter 50 a can be connected to the DSP 8 - 1 and the A/D converter 51 c to the DSP 8 - 2 ) or the same DSP.
- FIG. 2 is a block diagram illustrative of an address conversion between a controller 41 and a main memory 43 .
- the controller 41 corresponds to either one of the CPU 3 , the DSP Core 23 - 1 , and the DSP Core 23 - 2 , and the main memory 43 to the DRAM 5 and the SRAM 7 .
- An address converter 42 corresponds to the instruction cache 6 , the SRAM 7 , and the address converters 21 - 1 , 21 - 2 , or a dedicated hardware unit (not shown).
- the controller 41 For reading data from the main memory 43 , the controller 41 outputs a logical address of a virtual memory to the address converter 42 .
- the address converter 42 converts the logical address into a physical address, and outputs the physical address to the main memory 43 .
- the main memory 43 reads data at the physical address and outputs the data to the controller 41 .
- FIG. 3 schematically shows the relationship between a logical address space managed by logical addresses and a physical address space managed by physical addresses.
- the physical address space is a space created in the main memory 43 , and has a predetermined size of 4 KB (kilobytes) in this embodiment.
- numerical Values in each of the spaces represent addresses in respective areas, but not stored data.
- the logical address space includes three word spaces including a 8-bit word space, a 16-bit word space, and a 32-bit word space. These word spaces are created depending on the number of bits of data making up each of words handled by the controller 41 . If the controller 41 handles words of another number of bits than 8 bits, 16 bits, and 32 bits, then a word space of data made up of the other number of bits is also created in the logical address space. These word spaces store words made up of the corresponding numbers of bits.
- Each of the word spaces of the logical address space has a size of 4 KB. Therefore, the logical address space has a total size of 12 KB, which is larger than the physical address space.
- the logical address space and the physical address space are not limited to the above sizes. The size of each of the word spaces of the logical address space may not be the same as the size of the physical address space.
- each of the word spaces is set to 8 bits, 16 bits, or 32 bits.
- Each of the word spaces of the logical address space and the physical address space are of a rectangular shape as shown in FIG. 3 .
- the 8-bit physical address space and the 8-bit word space of the logical address space have a horizontal width of 8 bits.
- the 16-bit word space of the logical address space has a horizontal width of 16 bits.
- the 32-bit word space of the logical address space has a horizontal width of 32 bits.
- Each of the 8-bit word spaces is capable of storing 4096 words as indicated by addresses ranging from 0000h to 0FFFh (h represents a hexadecimal notation).
- the 16-bit word spaces is capable of storing 2048 words as indicated by addresses ranging from 1000h to 17FFh.
- the 32-bit word spaces is capable of storing 1024 words as indicated by addresses ranging from 2000h to 23FFh.
- One word in each of the 8-bit word spaces corresponds to one word in the physical address space
- one word in the 16-bit word space corresponds to two words in the physical address space
- One word in the 32-bit word space corresponds to four words in the physical address space.
- the address converter 42 In order to read words of data from the physical address space at a ratio of 1:1 for the 8-bit word spaces, 1:2 for the 16-bit word space, and 1:4 for the 32-bit word space depending on the number of bits of data of one word in the logical address space, the address converter 42 has a table shown in FIG. 4 .
- logical addresses ranging from 0000h to 0FFFh are used. If one word is made up of 16 bits, then logical addresses ranging from 1000h to 17FFh are used. If one word is made up of 32 bits, then logical addresses ranging from 2000h to 23FFh are used. These logical addresses are represented by numbers that increment successively by 1. Stated otherwise, the address 0000h serves as a base address in the 8-bit word spaces, the address 1000h as a base address in the 16-bit word space, and the address 2000h as a base address in the 32-bit word space. If one word is made up of 8 bits, then physical addresses increment by 1. If one word is made up of 16 bits, then physical addresses increment by 2. If one word is made up of 32 bits, then physical addresses increment by 4.
- the controller 41 outputs a logical address “0000h” in the 8-bit word space to the address converter 42 , then the address converter 42 associates the entered logical address “0000h” with a physical address “0000h”, and outputs the physical address “0000h” to the main memory 43 .
- the main memory 43 outputs data at the physical address “0000h” to the controller 41 .
- the address converter 42 associates the entered logical address “1000h” with physical addresses “0000h”, “0001h” for two words and outputs the physical addresses “0000h”, “0001h” to the main memory 43 . If the controller 41 outputs a logical address “1001h” in the 16-bit word space to the address converter 42 , then the address converter 42 associates the entered logical address “1001h” with physical addresses “0002h”, “0003h”. That is, if a logical address increments by 1, then the address converter 42 converts the address such that physical addresses increment by 2, and two-word data at the converted physical addresses are read from the main memory 43 .
- the address converter 42 associates the entered logical address “2000h” with physical addresses “0000h”-“0003h” for four words, and outputs the physical addresses “0000h”-“0003h” to the main memory 43 . If the controller 41 outputs a logical address “2001h” in the 32-bit word space to the address converter 42 , then the address converter 42 associates the entered logical address “2001h” with physical address “0004h”-“0007h”. That is, if a logical address increments by 1, then the address converter 42 converts the address such that physical addresses increment by 4 , and four-word data at the converted physical addresses are read from the main memory 43 .
- step S 1 the address converter 42 is supplied with a logical address outputted by the controller 41 .
- step S 2 the address converter 42 decides whether the entered logical address is of a value in the range from “0000h” to “0FFFh”. Stated otherwise, the address converter 42 decides in step S 2 whether the base address of the entered logical address is “0000h” or not, i.e., whether the number of bits of data making up one word is “8” or not.
- step S 2 If the address converter 42 determines in step S 2 that the entered logical address is of a value in the range from “0000h” to “0FFFh”, i.e., if the base address of the entered logical address is “0000h” or the number of bits of data making up one word is “8”, then the address converter 42 sets up a mode for associating a logical address with a physical address at a ratio of 1:1 in step S 3 .
- step S 2 If the address converter 42 determines in step S 2 that the entered logical address is not of a value in the range from “0000h” to “0FFFh”, then the address converter 42 decides whether the entered logical address is of a value in the range from “1000h” to “17FFh” in step S 4 . Stated otherwise, the address converter 42 decides whether the base address of the entered logical address is “1000h” or not, i.e., whether the number of bits of data making up one word is “16” or not.
- step S 4 If the address converter 42 determines in step S 4 that the entered logical address is of a value in the range from “1000h” to “17FFh”, then the address converter 42 sets up a mode for associating a logical address with a physical address at a ratio of 1:2 in step S 5 .
- step S 4 determines in step S 4 that the entered logical address is not of a value in the range from “1000h” to “17FFh”, then the address converter 42 decides whether the entered logical address is of a value in the range from “2000h” to “23FFh” in step S 6 . Stated otherwise, the address converter 42 decides whether the base address of the entered logical address is “2000h” or not, i.e., whether the number of bits of data making up one word is “32” or not.
- step S 6 If the address converter 42 determines in step S 6 that the entered logical address is of a value in the range from “2000h” to “23FFh”, then the address converter 42 sets up a mode for associating a logical address with a physical address at a ratio of 1:4 in step S 7 .
- step S 6 If the address converter 42 determines in step S 6 that the entered logical address is not of a value in the range from “2000h” to “23FFh”, then the address converter 42 performs an error process in step S 8 . That is, the size of one word is not of 8 bits, 16 bits, or 32 bits, and the words cannot be handled by the controller 41 .
- the address converter 42 determines the number of bits of data making up one word, and sets up a mode suitable for the determined number of bits. Thereafter, the address converter 42 refers to the table shown in FIG. 4 and determines a physical address corresponding to the entered logical address in step S 9 .
- the logical address space includes a plurality of word spaces depending on the number of bits of data making up one word, and the address increments by one in each of those word spaces.
- the address increments by different numbers for the respective word spaces. Accordingly, it is possible to use words of different numbers of bits without having to change programs.
- a providing medium for providing a computer program and/or data which carries out the above processing to the user may comprise any of various information recording mediums including a magnetic disk, a CD-ROM, etc., and any of various transmission mediums used in networks including the Internet, digital satellite systems, etc.
- a physical address is determined depending on the base address of a logical address, words of different numbers of bits can be handled without changing programs, and hence a logical address can quickly be converted into a physical address.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (21)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10-176825 | 1998-06-24 | ||
JP10176825A JP2000010863A (en) | 1998-06-24 | 1998-06-24 | Device and method for information processing, and provision medium |
Publications (1)
Publication Number | Publication Date |
---|---|
US6378058B1 true US6378058B1 (en) | 2002-04-23 |
Family
ID=16020508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/339,220 Expired - Lifetime US6378058B1 (en) | 1998-06-24 | 1999-06-24 | Method of and apparatus for processing information, and providing medium |
Country Status (3)
Country | Link |
---|---|
US (1) | US6378058B1 (en) |
EP (1) | EP0967553A3 (en) |
JP (1) | JP2000010863A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003065224A1 (en) * | 2002-01-31 | 2003-08-07 | Ubicom, Inc. | Communication protocol packet buffering using paged memory |
US20040003198A1 (en) * | 2002-03-27 | 2004-01-01 | Yoshihiro Tamura | Address conversion apparatus, address conversion method and computer program |
US20060236041A1 (en) * | 2005-03-16 | 2006-10-19 | Samsung Electronics Co., Ltd. | System having memory device accessible to multiple processors |
US20080189506A1 (en) * | 2007-02-07 | 2008-08-07 | Brian Joseph Kopec | Address Translation Method and Apparatus |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7836285B2 (en) * | 2007-08-08 | 2010-11-16 | Analog Devices, Inc. | Implementation of variable length instruction encoding using alias addressing |
JP5324676B2 (en) * | 2012-02-17 | 2013-10-23 | ルネサスエレクトロニクス株式会社 | Processor, bus interface device, and computer system |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4079451A (en) * | 1976-04-07 | 1978-03-14 | Honeywell Information Systems Inc. | Word, byte and bit indexed addressing in a data processing system |
US4473878A (en) * | 1981-11-23 | 1984-09-25 | Motorola, Inc. | Memory management unit |
US4604695A (en) * | 1983-09-30 | 1986-08-05 | Honeywell Information Systems Inc. | Nibble and word addressable memory arrangement |
US4819152A (en) * | 1985-04-05 | 1989-04-04 | Raytheon Company | Method and apparatus for addressing a memory by array transformations |
US4873521A (en) * | 1986-09-25 | 1989-10-10 | Siemens Aktiengesellschaft | Address administration unit of a multi-processor central control unit of a communications switching system |
US5155823A (en) * | 1988-04-18 | 1992-10-13 | Matsushita Electric Industrial Co., Ltd. | Address generating unit |
US5410671A (en) * | 1990-05-01 | 1995-04-25 | Cyrix Corporation | Data compression/decompression processor |
US5960465A (en) * | 1997-02-27 | 1999-09-28 | Novell, Inc. | Apparatus and method for directly accessing compressed data utilizing a compressed memory address translation unit and compression descriptor table |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE424581B (en) * | 1981-08-21 | 1982-07-26 | Ibm Svenska Ab | METHOD AND DEVICE FOR ADDRESSING A MEMORY |
US4868740A (en) * | 1986-06-04 | 1989-09-19 | Hitachi, Ltd. | System for processing data with multiple virtual address and data word lengths |
JP3024156B2 (en) * | 1990-02-16 | 2000-03-21 | ヤマハ株式会社 | Variable length data memory interface circuit |
US5555387A (en) * | 1995-06-06 | 1996-09-10 | International Business Machines Corporation | Method and apparatus for implementing virtual memory having multiple selected page sizes |
ATE278988T1 (en) * | 1994-03-24 | 2004-10-15 | Discovision Ass | METHOD AND DEVICE FOR INTERFACE FORMATION WITH RAM MEMORY |
-
1998
- 1998-06-24 JP JP10176825A patent/JP2000010863A/en active Pending
-
1999
- 1999-06-24 US US09/339,220 patent/US6378058B1/en not_active Expired - Lifetime
- 1999-06-24 EP EP99304970A patent/EP0967553A3/en not_active Ceased
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4079451A (en) * | 1976-04-07 | 1978-03-14 | Honeywell Information Systems Inc. | Word, byte and bit indexed addressing in a data processing system |
US4473878A (en) * | 1981-11-23 | 1984-09-25 | Motorola, Inc. | Memory management unit |
US4604695A (en) * | 1983-09-30 | 1986-08-05 | Honeywell Information Systems Inc. | Nibble and word addressable memory arrangement |
US4819152A (en) * | 1985-04-05 | 1989-04-04 | Raytheon Company | Method and apparatus for addressing a memory by array transformations |
US4873521A (en) * | 1986-09-25 | 1989-10-10 | Siemens Aktiengesellschaft | Address administration unit of a multi-processor central control unit of a communications switching system |
US5155823A (en) * | 1988-04-18 | 1992-10-13 | Matsushita Electric Industrial Co., Ltd. | Address generating unit |
US5410671A (en) * | 1990-05-01 | 1995-04-25 | Cyrix Corporation | Data compression/decompression processor |
US5960465A (en) * | 1997-02-27 | 1999-09-28 | Novell, Inc. | Apparatus and method for directly accessing compressed data utilizing a compressed memory address translation unit and compression descriptor table |
Non-Patent Citations (2)
Title |
---|
U.S. Patent Application Serial No. 09/339,815 by Makoto Furuhashi, filed on Jun. 25, 1999, status pending. |
U.S. Patent Application Serial No. 09/346,673 by Makoto Furuhashi, filed on Jul. 2, 1999, status pending. |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003065224A1 (en) * | 2002-01-31 | 2003-08-07 | Ubicom, Inc. | Communication protocol packet buffering using paged memory |
US6654865B2 (en) * | 2002-01-31 | 2003-11-25 | Ubicom, Inc. | Netbufs: communication protocol packet buffering using paged memory management |
US20040024985A1 (en) * | 2002-01-31 | 2004-02-05 | Hudson David J. | Netbufs: communication protocol packet buffering using paged memory management |
US6973558B2 (en) | 2002-01-31 | 2005-12-06 | Ubicom, Inc. | Netbufs: communication protocol packet buffering using paged memory management |
US20040003198A1 (en) * | 2002-03-27 | 2004-01-01 | Yoshihiro Tamura | Address conversion apparatus, address conversion method and computer program |
US6990565B2 (en) * | 2002-03-27 | 2006-01-24 | Matsushita Electric Industrial Co., Ltd. | Address conversion apparatus, address conversion method and computer program |
US20060236041A1 (en) * | 2005-03-16 | 2006-10-19 | Samsung Electronics Co., Ltd. | System having memory device accessible to multiple processors |
US8055854B2 (en) * | 2005-03-16 | 2011-11-08 | Samsung Electronics Co., Ltd. | System having memory device accessible to multiple processors |
US20080189506A1 (en) * | 2007-02-07 | 2008-08-07 | Brian Joseph Kopec | Address Translation Method and Apparatus |
US8239657B2 (en) * | 2007-02-07 | 2012-08-07 | Qualcomm Incorporated | Address translation method and apparatus |
Also Published As
Publication number | Publication date |
---|---|
EP0967553A2 (en) | 1999-12-29 |
JP2000010863A (en) | 2000-01-14 |
EP0967553A3 (en) | 2004-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4792897A (en) | Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure | |
JP2974526B2 (en) | Data transfer processing method and data transfer processing device | |
JPH0312339B2 (en) | ||
US6684267B2 (en) | Direct memory access controller, and direct memory access control method | |
US6378058B1 (en) | Method of and apparatus for processing information, and providing medium | |
JP3803196B2 (en) | Information processing apparatus, information processing method, and recording medium | |
JPH07281948A (en) | Memory controller | |
KR960008320B1 (en) | System equipped with processor and method of converting addresses in the said system | |
US6981122B2 (en) | Method and system for providing a contiguous memory address space | |
JPS59173828A (en) | Data processing system | |
JP3216965B2 (en) | Data receiving apparatus, method, and system | |
JP3511529B2 (en) | Complex arithmetic processing unit | |
JPH04348442A (en) | Address converter | |
CN116745754A (en) | System and method for accessing remote resource | |
JPH08314797A (en) | Memory access system | |
JPH03150647A (en) | High speed access device for input/output device | |
JPH04266140A (en) | Address conversion buffer device | |
JPH1040213A (en) | Method for transferring dma data of information processor | |
JPH04337851A (en) | Memory access system | |
JPS6048789B2 (en) | Prefix conversion control method | |
JP2001101072A (en) | Memory access device | |
JPH04101249A (en) | Busy checking system | |
JPS58169616A (en) | Dma transfer system | |
JPS63261446A (en) | Extended virtual memory control system | |
JPH04506125A (en) | calculator with cache |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SONY COMPUTER ENTERTAINMENT INC., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FURUHASHI, MAKOTO;REEL/FRAME:010072/0463 Effective date: 19990601 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: SONY NETWORK ENTERTAINMENT PLATFORM INC., JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:SONY COMPUTER ENTERTAINMENT INC.;REEL/FRAME:027437/0369 Effective date: 20100401 |
|
AS | Assignment |
Owner name: SONY COMPUTER ENTERTAINMENT INC., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONY NETWORK ENTERTAINMENT PLATFORM INC.;REEL/FRAME:027449/0108 Effective date: 20100401 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 12 |
|
SULP | Surcharge for late payment |
Year of fee payment: 11 |
|
AS | Assignment |
Owner name: DROPBOX INC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONY ENTERTAINNMENT INC;REEL/FRAME:035532/0507 Effective date: 20140401 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NE Free format text: SECURITY INTEREST;ASSIGNOR:DROPBOX, INC.;REEL/FRAME:042254/0001 Effective date: 20170403 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:DROPBOX, INC.;REEL/FRAME:042254/0001 Effective date: 20170403 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:DROPBOX, INC.;REEL/FRAME:055670/0219 Effective date: 20210305 |