US6346820B1 - Characteristics evaluation circuit for semiconductor wafer and its evaluation method - Google Patents

Characteristics evaluation circuit for semiconductor wafer and its evaluation method Download PDF

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US6346820B1
US6346820B1 US09/585,491 US58549100A US6346820B1 US 6346820 B1 US6346820 B1 US 6346820B1 US 58549100 A US58549100 A US 58549100A US 6346820 B1 US6346820 B1 US 6346820B1
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characteristics evaluation
mos transistor
evaluation circuit
set forth
semiconductor wafer
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US09/585,491
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Minoru Yamagami
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a characteristics evaluation circuit incorporated into a semiconductor wafer and its evaluation method.
  • characteristics of semiconductor chips are measured at each step. For example, threshold voltage characteristics of MOS transistors, resistance characteristics of conductive layers, capacitance characteristics of conductive layers and the like are measured to check the manufacturing steps.
  • a characteristics evaluation circuit is incorporated into each of the semiconductor chips, a scribe area between the semiconductor chips or a characteristics evaluation area having the same size as the semiconductor chips.
  • a prior art characteristics evaluation circuit is constructed by a dummy element associated with at least two pads. This will be explained later in detail.
  • the characteristics evaluation circuit After the characterisctics of the characteristics evaluation circuit are measured, the characteristics evaluation circuit become unneccessary. If the semiconductor chips or the semiconductor wafer associated with such a characteristics evaluation circuit is shipped, any third party can easily analyse the characteristics of the semiconductor chips by placing probes on the pads of the characteristics evaluation circuit.
  • a first approach is that fuses are connected to the pads of the dummy element. After the characteristics of the characteristics evaluation circuit are measured, the fuses are melted down by a laser trimming process or the like. This also will be explained later in detail.
  • a second approach is to directly destroy the dummy element by applying laser or mechanical stress thereto. This also will be explained later in detail.
  • Another object is to provide an improved characteristics evaluation method for a semiconductor wafer.
  • a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads.
  • a fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.
  • the gate of the depletion type MOS transistor when the fuse is cut, the gate of the depletion type MOS transistor is in a floating state. In this state, since the pad is not connected to the gate of the depletion type MOS transistor, the gate of the depletion type MOS transistor is very small. Therefore, since only a small charge is injected into the floating state gate, the gate voltage of the depletion type MOS transistor remains at zero (ground), so that the depletion type MOS transistor is always in an ON state.
  • FIG. 1 is a layout diagram illustrating a prior art semiconductor wafer
  • FIGS. 2A, 2 B and 2 C are layout diagrams for explaining the location of the characteristics evaluation areas of FIG. 1 ;
  • FIGS. 3A, 3 B and 3 C are circuit diagrams of the characteristics evaluation circuit used in the characteristics evaluation of FIGS, 2 A, 2 B and 2 C;
  • FIGS. 4A, 4 B and 4 C are also circuit diagrams of the characteristics evaluation circuit used in the characteristics evaluation areas of FIGS, 2 A, 2 B and 2 C;
  • FIG. 5A is a circuit diagram illustrating a first embodiment of the characteristics evaluation circuit according to the present invention.
  • FIG. 5B is a circuit diagram illustrating a second embodiment of the characteristics evaluation circuit according to the present invention.
  • FIG. 5C is a circuit diagram illustrating a third embodiment of the characteristics evaluation circuit according to the present invention.
  • FIG. 1 is a layout diagram illustrating a prior art semiconductor wafer
  • semiconductor chips 101 are arranged in rows, columns.
  • the semiconductor chips 101 ale separated from each other, and will be shipped.
  • the characteristics of the senor chips 101 are arranged in rows, columns. The semiconductor chips 101 ale separated from each other, and will be shipped.
  • characteristics evaluation circuits are incorporated into the semiconductor wafer of FIG. 1, as illustrated in FIGS. 2A, 2 B and 2 C.
  • a plurality of characteristics evaluation areas 103 for characteristics evaluation circuits are provided in scribe areas 104 between the semiconductor chips 101 .
  • each of the characteristics evaluation areas 105 has the same size as the semiconductor chips 101 .
  • the characteristics evaluation areas 105 are called test elementary group (TEG) areas.
  • the characteristics evaluation circuit used in the characteristics evaluation areas 102 , 103 and 105 of FIGS. 2A, 2 B and 2 C is illustrated in FIG. 3A, 3 B and 3 C.
  • a dummy MOS transistor 301 has a source connected to a pad P 1 , a drain connected to a pad P 2 and a gate connected to a pad P 3 .
  • the characteristics of the dummy MOS transistor 301 can be measured by placing probes (not shown) on the pads P 1 , P 2 and P 3 .
  • a dummy resistor 302 has a terminal connected to a pad P 4 and a terminal connected to a pad P 5 .
  • the characteristics of the resistor 302 can be measured by placing probes (not shown) on the pads P 4 and P 5 ,
  • a dummy capacitor 303 has a terminal connected to a pad P 6 and a terminal connected to a pad P 7 .
  • the characteristics of the capacitor 303 can be measured by placing probes (not shown) on the pads P 6 and P 7
  • the characteristics evaluation circuits of FIGS. 3A, 3 B and 3 C After the characteristics of the characteristics evaluation circuits of FIGS. 3A, 3 B and 3 C are measured, the characteristics evaluation circuits become unnecessary. If the semiconductor chips 101 associated with such characteristics evaluation circuits are shipped, any third party can easily analyse the characteristics of the semiconductor chips 101 by placing probes on the pads of the characteristics evaluation areas 102 , 103 or 105 . Therefore, the characteristics evaluation circuits should be destroyed prior to the shipping.
  • the characteristics evaluation circuits are provided in the characteristics evaluation areas 103 or 105 of FIG. 2B or 2 C, it is easy to destroy or inactivate the characteristics evaluation circuits. In this case, however, if a wafer without splitting the semiconductor chips 101 is shipped to another semiconductor manufacturer through an original equipment manufacturing (OEM) system or the like, it is also difficult to destroy or inactivate the characteristics evaluation circuits.
  • OEM original equipment manufacturing
  • a first approach is that fuses F 1 through F 7 are connected to the pads P 1 through P 7 , respectively, as illustrated in FIGS. 4A, 4 B and 4 C. After the characteristics of the characteristics evaluation circuits of FIGS. 4A, 4 B and 4 C are measured, the fuses F 1 through F 7 are melted down by a laser trimming process or the like.
  • a second approach is to directly destroy the dummy MOS transistor 301 , the dummy resistor 302 and the dummy capacitor 303 of FIGS. 3A, 3 B and 3 C by applying laser or mechanical stress thereto.
  • a depletion type MOS transistor 501 is connected between the drain and the gate of the dummy MOS transistor 301 of FIG. 3 A.
  • the gate of the depletion type MOS transistor 501 is connected via a fuse F 8 to a pad P 8 .
  • the depletion type MOS transistor 501 can be of a P-channel type or of an N-channel type.
  • the characteristics of the dummy MOS transistor 301 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P 8 to surely turn OFF the depletion type MOS transistor 501 . Then, the characteristics of the dummy MOS transistor 301 are measured by placing probes on the pads P 1 , P 2 and P 3 .
  • the fuse F 8 is melted down by a laser trimming process or the like.
  • the depletion type MOS transistor 501 becomes in an ON state, so that the pad P 2 is electrically connected to the pad P 3 , In this state, it is no longer possible for the characteristics of the dummy MOS transistor 301 to be correctly measured.
  • a depletion type MOS transistor associated with a fuse and a pad can be connected between the source and the gate of the dummy MOS transistor 301 or between the source and the drain of the dummy MOS transistor 301 .
  • a depletion type MOS transistor 502 is connected between the terminals of the dummy resistor 302 of FIG. 3 B.
  • the gate of the depletion type MOS transistor 502 is connected via a fuse F 9 to a pad P 9 .
  • the depletion type MOS transistor 502 can be of a P-channel type or of an N-channel type.
  • the characteristics of the dummy resistor 302 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P 9 to surely turn OFF the depletion type MOS transistor 502 . Then, the characteristics of the dummy resistor 302 are be measured by placing probes on the pads P 4 and P 5 .
  • the fuse F 9 is melted down by a laser trimming process or the like.
  • the depletion type MOS transistor 502 becomes in an ON state, so that the pad P 4 is electrically connected to the pad P 5 . In this state, it is no longer possible for the characteristics of the dummy resistor 302 to be correctly measured.
  • a depletion type MOS transistor 503 is connected between the terminals of the dummy capacitor 303 of FIG. 3 C.
  • the gate of the depletion type MOS transistor 503 is connected via a fuse F 10 to a pad P 10 .
  • the depletion type MOS transistor 503 can be of a P-channel type or of an N-channel type.
  • the characteristics of the dummy capacitor 303 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P 10 to surely turn OFF the depletion type MOS transistor 503 . Then, the characteristics of the dummy capacitor 303 are measured by placing probes on the pads P 6 and P 7 .
  • the fuse F 10 is melted down by a laser trimming process or the like.
  • the depletion type MOS transistor 503 becomes in an ON state, so that the pad P 6 is electrically connected to the pad P 7 In this state, it is no longer possible for the characteristics of the dummy capacitor 303 to be correctly measured.
  • the fuses F 8 , F 9 and F 10 do not need to supply currents to the gates of the depletion type MOS transistors 501 , 502 and 503 , respectively, the fuses F 8 , F 9 and F 10 can be very slim. As a result, the fuses F 8 , F 9 and F 10 can be easily melted down by a laser trimming process or the like. Also, the fuses F 8 , F 9 and F 10 can be made of materials other than aluminum.
  • dummy elements than the dummy MOS transistor 301 , the dummy resistor 302 and the dummy capacitor 303 can be introduced into the characteristics evaluation circuits.
  • characteristics evaluation circuits of FIGS. 5A, 5 B and 5 C can be incorporated into any of the characteristics evaluation areas of FIGS. 2A, 2 B and 2 C.
  • characteristics evaluation circuits incorporated into a semiconductor wafer can be easily destroyed or inactivated.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

In a characteristics evaluation circuit incorporated into a semiconductor wafer, a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads. A fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a characteristics evaluation circuit incorporated into a semiconductor wafer and its evaluation method.
2. Description of the Related Art
In a process for manufacturing a semiconductor wafer, characteristics of semiconductor chips are measured at each step. For example, threshold voltage characteristics of MOS transistors, resistance characteristics of conductive layers, capacitance characteristics of conductive layers and the like are measured to check the manufacturing steps.
In order to measure the above-mentioned characteristics of the semiconductor chips, a characteristics evaluation circuit is incorporated into each of the semiconductor chips, a scribe area between the semiconductor chips or a characteristics evaluation area having the same size as the semiconductor chips.
A prior art characteristics evaluation circuit is constructed by a dummy element associated with at least two pads. This will be explained later in detail.
After the characterisctics of the characteristics evaluation circuit are measured, the characteristics evaluation circuit become unneccessary. If the semiconductor chips or the semiconductor wafer associated with such a characteristics evaluation circuit is shipped, any third party can easily analyse the characteristics of the semiconductor chips by placing probes on the pads of the characteristics evaluation circuit.
In order to destroy or inactivate the characteristics evaluation circuit, a first approach is that fuses are connected to the pads of the dummy element. After the characteristics of the characteristics evaluation circuit are measured, the fuses are melted down by a laser trimming process or the like. This also will be explained later in detail.
In the above-mentioned first approach, however, it is impossible to accurately measure the dummy element due to the presence of resistances by the fuses.
A second approach is to directly destroy the dummy element by applying laser or mechanical stress thereto. This also will be explained later in detail.
In the second approach, however, since the dummy element has various types with different sizes, it is impossible to effectively destroy the dummy element, which also increases the manufacturing cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a characteristics evaluation circuit for a semiconductor wafer, capable of being easily destroyed or inactivated.
Another object is to provide an improved characteristics evaluation method for a semiconductor wafer.
According to the present invention, in a characteristics evaluation circuit incorporated into a semiconductor wafer, a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads. A fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.
When evaluating the characteristics of the dummy element, an appropriate voltage is applied to the gate voltage control pad so as to turn OFF the depletion type MOS transistor. Then, probes are placed on the pads to measure characteristics of the dummy element. Finally, the fuse is cut.
Note that, when the fuse is cut, the gate of the depletion type MOS transistor is in a floating state. In this state, since the pad is not connected to the gate of the depletion type MOS transistor, the gate of the depletion type MOS transistor is very small. Therefore, since only a small charge is injected into the floating state gate, the gate voltage of the depletion type MOS transistor remains at zero (ground), so that the depletion type MOS transistor is always in an ON state.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
FIG. 1 is a layout diagram illustrating a prior art semiconductor wafer,
FIGS. 2A, 2B and 2C are layout diagrams for explaining the location of the characteristics evaluation areas of FIG. 1 ;
FIGS. 3A, 3B and 3C are circuit diagrams of the characteristics evaluation circuit used in the characteristics evaluation of FIGS, 2A, 2B and 2C;
FIGS. 4A, 4B and 4C are also circuit diagrams of the characteristics evaluation circuit used in the characteristics evaluation areas of FIGS, 2A, 2B and 2C;
FIG. 5A is a circuit diagram illustrating a first embodiment of the characteristics evaluation circuit according to the present invention;
FIG. 5B is a circuit diagram illustrating a second embodiment of the characteristics evaluation circuit according to the present invention; and
FIG. 5C is a circuit diagram illustrating a third embodiment of the characteristics evaluation circuit according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Before the description of the preferred embodiments, prior art semiconductor characteristics evaluation circuits will be explained with reference to FIGS. 1, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B and 4C.
In FIG. 1, which is a layout diagram illustrating a prior art semiconductor wafer, semiconductor chips 101 are arranged in rows, columns. The semiconductor chips 101 ale separated from each other, and will be shipped. In order to evaluate the characteristics of the sen
miconductorwafer, i.e., the characteristics of the semiconductor chips 101, characteristics evaluation circuits are incorporated into the semiconductor wafer of FIG. 1, as illustrated in FIGS. 2A, 2B and 2C.
In FIG. 2A, one characteristics evaluation area
102 for a semiconductor characteristics evaluation circuits is provided within each of the semiconductor chips 101.
In FIG. 2B, a plurality of characteristics evaluation areas 103 for characteristics evaluation circuits, are provided in scribe areas 104 between the semiconductor chips 101.
In FIG. 2C, some of the semiconductor chips 101 are replaced by characteristics evaluation areas 105 for characteristics evaluation circuits. In this case, each of the characteristics evaluation areas 105 has the same size as the semiconductor chips 101. Note that the characteristics evaluation areas 105 are called test elementary group (TEG) areas.
The characteristics evaluation circuit used in the characteristics evaluation areas 102, 103 and 105 of FIGS. 2A, 2B and 2C is illustrated in FIG. 3A, 3B and 3C.
In FIG. 3A, a dummy MOS transistor 301 has a source connected to a pad P1, a drain connected to a pad P2 and a gate connected to a pad P3. Thus, the characteristics of the dummy MOS transistor 301 can be measured by placing probes (not shown) on the pads P1, P2 and P3.
In FIG. 3B, a dummy resistor 302 has a terminal connected to a pad P4 and a terminal connected to a pad P5. Thus, the characteristics of the resistor 302 can be measured by placing probes (not shown) on the pads P4and P5,
In FIG. 3C, a dummy capacitor 303 has a terminal connected to a pad P6 and a terminal connected to a pad P7. Thus, the characteristics of the capacitor 303 can be measured by placing probes (not shown) on the pads P6 and P7
After the characteristics of the characteristics evaluation circuits of FIGS. 3A, 3B and 3C are measured, the characteristics evaluation circuits become unnecessary. If the semiconductor chips 101 associated with such characteristics evaluation circuits are shipped, any third party can easily analyse the characteristics of the semiconductor chips 101 by placing probes on the pads of the characteristics evaluation areas 102, 103 or 105. Therefore, the characteristics evaluation circuits should be destroyed prior to the shipping.
When the characteristics evaluation circuits are provided in the characteristics evaluation areas 102 of FIG. 2A, it is difficult to destroy or inactivate the characteristics evaluation circuits.
On the other hand, when the characteristics evaluation circuits are provided in the characteristics evaluation areas 103 or 105 of FIG. 2B or 2C, it is easy to destroy or inactivate the characteristics evaluation circuits. In this case, however, if a wafer without splitting the semiconductor chips 101 is shipped to another semiconductor manufacturer through an original equipment manufacturing (OEM) system or the like, it is also difficult to destroy or inactivate the characteristics evaluation circuits.
In order to destroy or inactivate the characteristics evaluation circuits of FIGS. 3A, 3B and 3C, a first approach is that fuses F1 through F7 are connected to the pads P1 through P7, respectively, as illustrated in FIGS. 4A, 4B and 4C. After the characteristics of the characteristics evaluation circuits of FIGS. 4A, 4B and 4C are measured, the fuses F1 through F7 are melted down by a laser trimming process or the like.
In the above-mentioned first approach, however, it is impossible to accurately measure the dummy MOS transistor 301, the dummy resistor 302 and the dummy capacitor 303 of FIGS. 4A, 4B and 4C due to the presence of resistances by the fuses F1 through F7 Even if the fuses F1 through F7 are made of aluminum having a low resistance value, the fuses F1 through F7 still have a large resistance when the aluminum is relative slim. If aluminum is widened to decrease its resistance value, it is impossible to melt down the fuses F1 through F7 by one laser trimming process, which increases the manufacturing cost.
A second approach is to directly destroy the dummy MOS transistor 301, the dummy resistor 302 and the dummy capacitor 303 of FIGS. 3A, 3B and 3C by applying laser or mechanical stress thereto.
In the second approach, however, since the dummy MOS transistor 301, the dummy resistor 302 and the capacitor 303 of FIGS. 3A, 3B and 3C have various types with different sizes, it is impossible to effectively destroy the dummy MOS transistor 301, the dummy resistor 302 and the dummy capacitor 303 of FIGS. 3A, 3B and 3C, which also increases the manufacturing cost.
In FIG. 5A, which illustrates a first embodiment of the present invention, a depletion type MOS transistor 501 is connected between the drain and the gate of the dummy MOS transistor 301 of FIG. 3A. The gate of the depletion type MOS transistor 501 is connected via a fuse F8 to a pad P8. Note that the depletion type MOS transistor 501 can be of a P-channel type or of an N-channel type.
Before the characteristics of the dummy MOS transistor 301 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P8 to surely turn OFF the depletion type MOS transistor 501. Then, the characteristics of the dummy MOS transistor 301 are measured by placing probes on the pads P1, P2 and P3.
After the characteristics of the dummy MOS transistor 301 are measured, the fuse F8 is melted down by a laser trimming process or the like. As a result, the depletion type MOS transistor 501 becomes in an ON state, so that the pad P2 is electrically connected to the pad P3, In this state, it is no longer possible for the characteristics of the dummy MOS transistor 301 to be correctly measured.
In FIG. 5A, a depletion type MOS transistor associated with a fuse and a pad can be connected between the source and the gate of the dummy MOS transistor 301 or between the source and the drain of the dummy MOS transistor 301.
In FIG. 5B, which illustrates a second embodiment of the present invention, a depletion type MOS transistor 502 is connected between the terminals of the dummy resistor 302 of FIG. 3B. The gate of the depletion type MOS transistor 502 is connected via a fuse F9 to a pad P9. Note that the depletion type MOS transistor 502 can be of a P-channel type or of an N-channel type.
Before the characteristics of the dummy resistor 302 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P9 to surely turn OFF the depletion type MOS transistor 502. Then, the characteristics of the dummy resistor 302 are be measured by placing probes on the pads P4 and P5.
After the characteristics of the dummy resistor 302 are measured, the fuse F9 is melted down by a laser trimming process or the like. As a result, the depletion type MOS transistor 502 becomes in an ON state, so that the pad P4 is electrically connected to the pad P5. In this state, it is no longer possible for the characteristics of the dummy resistor 302 to be correctly measured.
In FIG. 5C, which illustrates a third embodiment of the present invention, a depletion type MOS transistor 503 is connected between the terminals of the dummy capacitor 303 of FIG. 3C. The gate of the depletion type MOS transistor 503 is connected via a fuse F10 to a pad P10. Note that the depletion type MOS transistor 503 can be of a P-channel type or of an N-channel type.
Before the characteristics of the dummy capacitor 303 are measured, an appropriate voltage is applied by placing a probe (not shown) on the pad P10 to surely turn OFF the depletion type MOS transistor 503. Then, the characteristics of the dummy capacitor 303 are measured by placing probes on the pads P6 and P7.
After the characteristics of the dummy capacitor 303 are measured, the fuse F10 is melted down by a laser trimming process or the like. As a result, the depletion type MOS transistor 503 becomes in an ON state, so that the pad P6 is electrically connected to the pad P7 In this state, it is no longer possible for the characteristics of the dummy capacitor 303 to be correctly measured.
In the above-described embodiments, since the fuses F8, F9 and F10 do not need to supply currents to the gates of the depletion type MOS transistors 501, 502 and 503, respectively, the fuses F8, F9 and F10 can be very slim. As a result, the fuses F8, F9 and F10 can be easily melted down by a laser trimming process or the like. Also, the fuses F8, F9 and F10 can be made of materials other than aluminum.
Also, in the present invention, other dummy elements than the dummy MOS transistor 301, the dummy resistor 302 and the dummy capacitor 303 can be introduced into the characteristics evaluation circuits.
Further, the characteristics evaluation circuits of FIGS. 5A, 5B and 5C can be incorporated into any of the characteristics evaluation areas of FIGS. 2A, 2B and 2C.
As explained hereinabove, according to the present invention, characteristics evaluation circuits incorporated into a semiconductor wafer can be easily destroyed or inactivated.

Claims (14)

What is claimed is:
1. A characteristics evaluation circuit incorporated into a semiconductor wafer, comprising:
a dummy element connected to at least two pads;
a depletion type MOS transistor connected between said pads;
a fuse connected to a gate of said depletion type MOS transistor; and
a gate voltage control pad connected to said fuse.
2. The characteristics evaluation circuit as set forth in claim 1, wherein said dummy element comprises a MOS transistor.
3. The characteristics evaluation circuit as set forth in claim 1, wherein said dummy element comprises a resistor.
4. The characteristics evaluation circuit as set forth in claim 1, wherein said dummy element comprises a capacitor.
5. The characteristics evaluation circuit as set forth in claim 1, being incorporated into each semiconductor chip of said semiconductor wafer.
6. The characteristics evaluation circuit as set forth in claim 1, being incorporated into a scribe area of said semiconductor wafer.
7. The characteristics evaluation circuit as set forth in claim 1, being incorporated into a characteristics evaluation area having the same size of semiconductor chip of said semiconductor wafer.
8. A method for evaluating a semiconductor characteristics evaluation circuit comprising a dummy element connected to at least two pads, a depletion type MOS transistor connected between said pads, a fuse connected to a gate of said depletion type MOS transistor, and a gate voltage control pad connected to said fuse, said method comprising the steps of:
applying an appropriate voltage to said gate voltage control pad so as to turn OFF said depletion type MOS transistor;
placing probes on said pads to measure characteristics of said dummy element after said appropriate voltage is applied to said gate voltage control pad; and
cutting said fuse after the characteristics of said dummy element are measured.
9. The method as set forth in claim 8, wherein said dummy element comprises a MOS transistor.
10. The method as set forth in claim 8, wherein said dummy element comprises a resistor.
11. The method as set forth in claim 8, wherein said dummy element comprises a capacitor.
12. The method as set forth in claim 8, wherein said characteristics evaluation circuit is incorporated into each semiconductor chip of said semiconductor wafer.
13. The method as set forth in claim 8, wherein said characteristics evaluation circuit is incorporated into a scribe area of said semiconductor wafer.
14. The method as set forth in claim 8, wherein said characteristics evaluation circuit is incorporated into a characteristics evaluation area having the same size of semiconductor chips of said semiconductor wafer.
US09/585,491 1999-06-03 2000-06-01 Characteristics evaluation circuit for semiconductor wafer and its evaluation method Expired - Fee Related US6346820B1 (en)

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US6998865B2 (en) * 2001-12-10 2006-02-14 International Business Machines Corporation Semiconductor device test arrangement with reassignable probe pads
US7307441B2 (en) 2002-05-15 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same
CN100372091C (en) * 2003-04-24 2008-02-27 松下电器产业株式会社 Semiconductor device and method for evaluating characteristics of the same
US20080169467A1 (en) * 2007-01-12 2008-07-17 Elpida Memory, Inc. Semiconductor device
EP4239675A1 (en) * 2022-03-02 2023-09-06 Infineon Technologies Austria AG Semiconductor wafer with alignment mark indicating the wafer orientation and method for fabricating said semiconductor wafer

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KR100487530B1 (en) 2002-07-26 2005-05-03 삼성전자주식회사 Semiconductor device with test element groups
CN103178824A (en) * 2013-03-18 2013-06-26 西安华芯半导体有限公司 Integrated circuit with partial module power shutoff function and shutoff method

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US6998865B2 (en) * 2001-12-10 2006-02-14 International Business Machines Corporation Semiconductor device test arrangement with reassignable probe pads
US7307441B2 (en) 2002-05-15 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same
CN100372091C (en) * 2003-04-24 2008-02-27 松下电器产业株式会社 Semiconductor device and method for evaluating characteristics of the same
US20050040830A1 (en) * 2003-08-19 2005-02-24 Fabien Funfrock Integrated circuit for testing circuit components of a semiconductor chip
US7102362B2 (en) * 2003-08-19 2006-09-05 Infineon Technologies, Ag Integrated circuit for testing circuit components of a semiconductor chip
US20080169467A1 (en) * 2007-01-12 2008-07-17 Elpida Memory, Inc. Semiconductor device
US8704223B2 (en) * 2007-01-12 2014-04-22 Minoru Yamagami Semiconductor device
EP4239675A1 (en) * 2022-03-02 2023-09-06 Infineon Technologies Austria AG Semiconductor wafer with alignment mark indicating the wafer orientation and method for fabricating said semiconductor wafer

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TW451380B (en) 2001-08-21
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KR100331973B1 (en) 2002-04-10

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