US6326664B1 - Transistor with ultra shallow tip and method of fabrication - Google Patents

Transistor with ultra shallow tip and method of fabrication Download PDF

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US6326664B1
US6326664B1 US08/971,992 US97199297A US6326664B1 US 6326664 B1 US6326664 B1 US 6326664B1 US 97199297 A US97199297 A US 97199297A US 6326664 B1 US6326664 B1 US 6326664B1
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pair
transistor
semiconductor material
sidewall spacers
forming
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Robert S. Chau
Chan-Hong Chern
Chia-Hong Jan
Kevin R. Weldon
Paul A. Packan
Leopoldo D. Yau
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Intel Corp
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Intel Corp
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Abstract

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Description

This is a continuation of application Ser. No. 08/363,749, filed Dec. 23, 1994 now U.S. Pat. No. 5,710,450.
The structure of a conventional MOS transistor 100 is shown in FIG. 1. Transistor 100 comprises a gate electrode 102, typically polysilicon, formed on a gate dielectric layer 104 which in turn is formed on a silicon substrate 106. A pair of source/drain extensions or tip regions 110 are formed in the top surface of substrate 106 in alignment with outside edges of gate electrode 102. Tip regions 110 are typically formed by well-known ion implantation techniques. Formed adjacent to opposite sides of gate electrode 102 and over tip regions 110 are a pair of sidewall spacers 108. A pair of source/drain regions 120 are then formed, by ion implantation, in substrate 106 substantially in alignment with the outside edges of sidewall spacers 108.
As the gate length of transistor 100 is scaled down in order to fabricate a smaller transistor, the depth at which tip region 110 extends into substrate 106 must also be scaled down (i.e., decreased) in order to improve punchthrough characteristics of the fabricated transistor. Unfortunately, the length of tip region 110, however, must be larger than 0.10 μm to insure that the later, heavy dose, deep source/drain implant does not swamp and overwhelm tip region 110. Thus, in the fabrication of a small scale transistor with conventional methods, as shown in FIG. 1, the tip region 110 is both shallow and long. Because tip region 110 is both shallow and long, tip region 110 exhibits substantial parasitic resistance. Parasitic resistance adversely effects (reduces) the transistors drive current.
Thus, what is needed is a novel transistor with a low resistance ultra shallow tip region with a VLSI manufacturable method of fabrication.
SUMMARY OF THE INVENTION
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication is described. According to the preferred method of the present invention, a gate dielectric layer is formed on a first surface of a semiconductor substrate. Next, a gate electrode is formed on the gate dielectric layer. Then a first pair of sidewall spacers are formed adjacent to opposite sides of the gate electrode. Next, a pair of recesses are formed in the semiconductor substrate in alignment with the outside edges of the first pair of sidewall spacers. Next, a semiconductor material is selectively deposited into the recesses such that the semiconductor material extends both above and below the first surface of the semiconductor substrate. Dopants are then diffused from the semiconductor material into the substrate beneath the first pair of sidewall spacers to form an ultra shallow tip region. A second pair of sidewall spacers are then formed on semiconductor material adjacent to the outside edges of the first pair of sidewall spacers. Next, a deep implant is made in alignment with the outside edges of the second pair of sidewall spacers to form a deep junction source/drain contact region. Finally, silicide is formed onto the source/drain regions and gate electrode of the fabricated transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an illustration of a cross-sectional view of a conventional transistor.
FIG. 2 is an illustration of a cross-sectional view of a low resistance ultra shallow tip transistor of the present invention.
FIG. 3a is an illustration of a cross-sectional view showing the formation of a first pair of sidewall spacers on opposite sides of a gate electrode formed on a substrate.
FIG. 3b is an illustration of a cross-sectional view showing the formation of recess regions in the substrate of FIG. 3a.
FIG. 3c is an illustration of a cross-sectional view showing the deposition of semiconductor material on the substrate of FIG. 3b.
FIG. 3d is an illustration of a cross-sectional view showing the solid-state diffusion of dopants into the substrate of FIG. 3c.
FIG. 3e is an illustration of a cross-sectional view showing the formation of a second pair of sidewall spacers on the substrate of FIG. 3d.
FIG. 3f is an illustration of a cross-sectional view showing the formation of a deep junction source/drain contact regions in the substrate of FIG. 3d.
FIG. 4 is an illustration of a cross-sectional view showing another preferred embodiment of the low resistance ultra shallow tip transistor of the present invention with shallow junction deposited semiconductor source/drain contact regions.
FIG. 5 is an illustration of a cross-sectional view showing another preferred embodiment of the low resistance ultra shallow tip transistor of the present invention with a deposited semiconductor buried channel region.
FIG. 6 is an illustration of a cross-sectional view showing another preferred embodiment of the low resistance ultra shallow tip transistor of the present invention with vertically and horizontally diffused ultra shallow tip region.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
A novel transistor with a low resistance ultra shallow tip and its method of fabrication is described. In the following description numerous specific details are set forth, such as specific materials, dimensions, and processes, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art, that the invention may be practiced without these specific details. In other instances, well-known semiconductor equipment and processes have not been described in particular detail in order to avoid unnecessarily obscuring the present invention.
A preferred embodiment of a novel transistor 200 with low resistivity, ultra shallow tip of the present invention is shown in FIG. 2. Transistor 200 is formed on a silicon substrate or well 201. A gate dielectric layer 202 is formed on a surface 203 of substrate 201 and a gate electrode 204 is in turn formed on gate dielectric layer 202. A first pair of thin sidewall spacers 206 are formed on opposite sides of gate electrode 204 (spacers 206 run along the “width” of gate electrode 204). Transistor 200 also includes a second pair of substantially larger sidewall spacers 208 formed adjacent to the outside edges of the first pair of sidewall spacers 206. Transistor 200 includes a pair of source/drain regions 211 each comprising a pair of tips or source/drain extensions 210 and a source/drain contact region 212.
Tip or source/drain extension 210 is defined as the source/drain region located beneath second sidewall spacer 208, first sidewall spacer 206, and the outside edge of gate electrode 204. Tip 210 comprises an ultra shallow tip portion 214 and a raised tip portion 216. Ultra shallow tip portion 214 is comprised of a doped semiconductor substrate 215 formed by “out diffusing” dopants from selectively deposited semiconductor material 217 into substrate 201. Ultra shallow tip 214 extends from beneath first sidewall spacer 206 to the outside edges of gate electrode 204. Ultra shallow tip 214 preferably extends approximately 100 Å beneath gate electrode 204 for a transistor with an effective gate length of approximately 0.10 microns (or 1000 Å). Additionally, ultra shallow tip 214 preferably extends less than 500 Å deep into substrate 201 beneath substrate surface 203 for a 0.10 μm effective gate length. It is to be appreciated that because a novel method of fabrication is employed in the present invention, ultra shallow tip 214 is characterized by a very abrupt junction.
Tip 210 of transistor 200 also includes a raised tip portion 216. Raised tip portion 216 is located beneath second sidewall spacer 208 and is adjacent to the outside edges of first sidewall spacer 206. Raised tip 216 is preferably formed of doped semiconductor material 217 selectively deposited both above and below surface 203 of semiconductor substrate 215. Because a portion of raised tip 216 is formed above semiconductor substrate surface 203, raised tip 216 is said to be “raised”. A raised tip significantly reduces the parasitic resistance of transistor 200 and thereby improves its performance.
A pair of source/drain contact regions 212 are formed adjacent to the outside edge of second sidewall spacer 208. Source/drain contact regions 212 are deep junction source/drain contacts. Source/drain contact regions 212 are formed by ion implantation or diffusing additional dopants into a region 220 comprising selectively deposited semiconductor material 217, “out diffused” doped semiconductor substrate 215 and substrate 201 in alignment with the outside edges of second sidewall spacers 208. Source/drain contact regions 212 are partially raised source/drain regions. Silicide 218 is preferably formed on source/drain region 212 in order to reduce the contact resistance of transistor 200. Additionally, according to the present invention, first semiconductor material 217 is preferably deposited onto the top surface of gate electrode 204. Silicide 218 is also preferably formed on deposited semiconductor material 217 on gate electrode 204 to help improve contact resistance.
It is to be appreciated that a valuable feature of the present invention is the fact that transistor 200 includes a tip or source/drain extension 210 which is both ultra shallow and raised. In this way, transistor 200 has a shallow tip with a very low parasitic resistance. The novel structure of transistor 200 allows for tip scaling necessary for the fabrication of transistor 200 with effective gate length less than 0.15 μm. Because of the novel tip structure 210 of the present invention, transistor 200 has good punchthrough performance and reduced VT roll-off. Additionally, because of tip 210, transistor 200 has a low parasitic resistance, resulting in good drive current.
FIGS. 3a-3 f illustrate a presently preferred method of fabrication of a transistor with a low resistance ultra shallow tip region. The preferred method of fabrication will be described with respect to the fabrication of a PMOS transistor. It is to be appreciated that the preferred method is equally applicable to the fabrication of NMOS devices wherein the conductivity types are simply reversed. As shown in FIG. 3a, a PMOS transistor of the present invention is preferably fabricated on an n-type substrate or well 300 doped to a concentration level between 1×1017/cm3 to 1×1019/cm3. It is to be appreciated that substrate 300 may additionally include a top layer or layers of deposited semiconductor material. According to the present invention, a substrate is defined as the starting material on which the transistor is fabricated.
According to the present invention, first a gate dielectric layer 302 is formed on top surface 304 of substrate 300. Gate dielectric layer 302 is preferably a nitrided-oxide layer formed to a thickness of between 20 Å-50 Å. It is to be appreciated that other well-known gate dielectric layers, such as oxides, nitrides, and combinations thereof, may be utilized, if desired. Next, a gate electrode 306 is formed over gate dielectric layer 302. Gate electrode 306 is preferably formed from a 1000-3500 Å blanket deposited polysilicon layer patterned into gate electrode 306 with well-known photolithographic techniques. It is to be appreciated that other well-known patterning techniques may be utilized to pattern gate electrode 306, including submicron photolithography techniques and subphotolithographic patterning techniques such as described in copending patent application entitled “Inverted Spacer Transistor”, Ser. No. 08/288,332 filed Aug. 10, 1994, and assigned to the present assignee. Additionally, although gate electrode 306 is preferably a polysilicon gate electrode, gate electrode 306 can be a metal gate, a single crystalline silicon gate, or any combination thereof, if desired.
Next, as also shown in FIG. 3a, a first sidewall spacer layer 308 is blanket deposited over substrate 300 and the top and sides of gate electrode 306. Spacer layer 308 is preferably a silicon dioxide layer deposited by any well-known process, to a thickness of between approximately 50 Å-500 Å with 200 Å being preferred. It is to be appreciated that other insulators, such as silicon-nitride and nitride-oxides, etc., may be utilized as spacer layer 308, if desired. It is to be appreciated that spacer layer 308 must be formed thick enough to electrically isolate a subsequently deposited semiconductor material from gate electrode 306. Additionally, as will be appreciated later, the thickness of sidewall spacer layer 308 defines the resulting spacer thickness and the minimum length of the ultra shallow tip portion of the fabricated transistor.
Next, as shown in FIG. 3b, first sidewall spacer layer 308 is anisotropically dry etched with any well-known technique to form a first pair of sidewall spacers 310 which run along the width of gate electrode 306.
Next, as shown in FIG. 3b, substrate 300 is anisotropically etched with any well-known technique, such as reactive ion etching (RIE) with a chemistry comprising C2F6 and He at a ratio of 2:1, respectively, to form a pair of recesses 312 in silicon substrate 300 in alignment with the outside edges of first sidewall spacers 310. It is to be noted that polysilicon gate electrode 306 is partially etching during the silicon substrate recess etch. Gate electrode 306 and first sidewall spacer 310 act as a mask preventing silicon substrate surface 304, located underneath, from being etched. In this way the recess etch of the present invention is self-aligned to the outside edges of first sidewall spacers 310. According to the preferred embodiment of the present invention, substrate 300 is etched to form recess regions 312 with depths of between approximately 20 Å-1000 Å, with a depth of 200 Å below substrate surface 304 being preferred. It is to be appreciated that the depth of recess region 312 defines a minimum depth at which the fabricated transistors' ultra shallow tips will extend into substrate 300. The deeper the recess regions, the deeper the transistor tip regions will extend into substrate 300.
Next, according to the preferred embodiment of the present invention, as shown in FIG. 3c, semiconductor material 314 is selectively deposited into recesses 312 and onto the top surface of gate electrode 306. Semiconductor material 314 is selectively deposited so that it forms only on exposed silicon such as substrate 300 and polysilicon gate electrode 306. No semiconductor material is formed on sidewall spacer 310. Sidewall spacers 310 electrically isolate semiconductor material 314, formed in recesses 312, from gate electrode 306. Semiconductor material 314 is formed to a thicknesses of between 200 Å-2000 Å, with approximately 600 Å being preferred. In this way semiconductor material 314 is formed both above and below surface 304 of semiconductor substrate 300. Additionally, semiconductor material 314 is preferably in-situ doped with p-type impurities, such as boron, to a concentration level between 1×1018/cm3 to 5×1020/cm3, with a concentration of approximately 1×1020/cm3 being preferred. Additionally, it is to be appreciated that semiconductor material need not be in-situ doped, but rather may be doped to the desired conductivity level after deposition by ion implantation or diffusion. For example, in the fabrication of CMOS or BiCMOS parts it may be necessary to dope semiconductor material 314 after deposition so that standard photoresist masking techniques can be used to form both p-type conductivity semiconductor material and n-type conductivity semiconductor material for the PMOS and NMOS devices, respectively, of a CMOS circuit.
It is to be noted that the thickness and doping concentration level of semiconductor material 314 determines the resistivity of the raised tip portion of the fabricated transistor. A thicker and higher doped semiconductor material 314 results in a transistor with a lower parasitic resistance. An adverse capacitance (i.e., Miller capacitance), however, can be developed when opposite voltages are placed on gate electrode 306 and semiconductor material 314. The higher the doping and the thicker semiconductor material 314 is, the greater is the Miller capacitance. Thus, a trade off must be made between the transistors' parasitic resistance and its Miller capacitance.
According to the present invention, semiconductor material 314 is preferably a silicon/germanium semiconductor alloy with germanium comprising approximately 10-50% of the alloy. A silicon/germanium semiconductor alloy can be formed by decomposition of SiH2Cl2 and GeH4 in H2 ambient, at a temperature of between 500-800° C., with 600° C. being preferred. Such a semiconductor material is preferred because it exhibits good selectivity to silicon during deposition, making the present invention very manufacturable. Additionally, such a silicon/germanium semiconductor alloy exhibits many “faults” or “dislocations” which aid in the solid state diffusion of dopants through the semiconductor material. It is to be appreciated any semiconductor material which can be selectively deposited can be used to form semiconductor material 314. For example, semiconductor material 314 can be selectively deposited polycrystalline silicon formed from SiH2Cl2 and HCl in a H2 ambient, at temperature of between 600-900° C., or can be selectively deposited single crystalline silicon formed by any well-known technique.
Next, according to the present invention, as shown in FIG. 3d, p-type impurities or dopants are diffused out from semiconductor material 314 and into semiconductor substrate 300 to form diffused semiconductor regions 316. The out diffusion of impurities forms diffused semiconductor regions 316 with a concentration level approximately equal to the deposited semiconductor material 314. Impurities are diffused laterally (horizontally) beneath first thin sidewall spacers 310 until impurities reach at least the outside edges of gate electrode 306 and preferably extend approximately 100 Å beneath gate electrode 306. The portion of diffused semiconductor regions 316 which laterally extend beneath first sidewall spacer 310 and gate electrode 306 is the ultra shallow tip portion of the fabricated transistor. It is to be appreciated that the out diffusion of impurities also diffuses impurities deeper (or vertically) into substrate 300. For each 200 Å of lateral diffusion, dopants diffuse about 200 Å vertically into substrate 300. Thus, according to the preferred embodiment of the present invention, ultra shallow tips 317 are approximately 300 Å in length and approximately 500 Å (or 0.05 μm) deep for a 0.10 μm effective gate length.
According to the preferred embodiment of the present invention, solid-state diffusion step occurs directly after the formation of semiconductor material 314 with a rapid thermal process (RTP) at a temperature between 800° C. to 1000° C. for 5 to 60 seconds in a nitrogen (N2) ambient. It is to be appreciated that the solid-state diffusion step of the present invention need not necessarily occur directly after the formation of semiconductor material 314, but rather can occur during later thermal cycles used in subsequent process steps.
It is to be appreciated that a key feature of the present invention is the fact that the semiconductor material 314 is formed beneath semiconductor substrate surface 304. That is, in the present invention, a source of dopants 315 is placed into substrate 300 directly adjacent to the location where the ultra shallow tip 317 is to be formed. In this way during the solid-state diffusion step, dopants are able to easily diffuse in a single direction (laterally) below the first sidewall spacer 310 and underneath the outside edge of polysilicon gate electrode 306. This results in an ultra shallow tip 317, which is characterized by a very sharp and abrupt junction with substrate 300. Such an abrupt junction improves the punchthrough characteristics of the fabricated transistor. Additionally, it is to be appreciated that by forming ultra shallow tips 317 by solid-state diffusion, higher conductivity tips can be fabricated than possible with present standard ion implantation techniques. A higher concentration tip region improves the device's performance and lowers the devices parasitic resistance.
Next, as shown in FIG. 3e, a second pair of sidewall spacers 318 are formed on deposited semiconductor material 314 and adjacent to the outside edges of first sidewall spacer 310. Second sidewall spacer 318 are preferably formed by anisotropically dry etching a conformal layer of silicon nitride formed by a hot wall process. Like sidewall spacers 310, second sidewall spacer 318 can be formed by any one of a variety of well-known techniques, if desired. Second sidewall spacers 318 are substantially thicker than first sidewall spacers 310 and are formed to a thickness of between 500-2500 Å, with 1800 Å being preferred.
Next, as shown in FIG. 3f, fabrication of transistor 340 is completed with the formation of source/drain contact regions 319. After formation of second sidewall spacer 318, shown in FIG. 3e, the substrate is subjected to a standard and well-known ion implantation and anneal which implants p-type conductivity impurities, such as boron, into deposited semiconductor material 314, diffused silicon region 316, and semiconductor substrate 300. The ion implantation step preferably forms a source/drain contact region 322 with a p-type conductivity level of between 1×1019/cm3 to 5×1020/cm3, and a source/drain contact region 319 having a total thickness of between 0.15-0.25 μm. Additionally, the ion implantation step can also be used to dope polysilicon gate electrode 306, if not previously doped during polysilicon gate electrode 306 formation. It is to be appreciated that the second sidewall spacers 318 must be formed thick and wide enough to provide a sufficient mask to prevent the deep, high dose, ion implantation of the source/drain contact regions 319 from overwhelming the fabricated tip region 321.
Next, according to the preferred method of the present invention, silicide 320 is formed by a self-aligned silicide process (salicide) onto deposited semiconductor material 314 on source/drain contact regions 319 and onto deposited semiconductor material 314 formed on gate electrode 306 to significantly reduce the devices contact resistance. In the preferred salicide process a titanium layer is first blanket deposited over the entire device. The device is then temperature cycled to cause a reaction between the deposited titanium layer and any exposed silicon surfaces (i.e., semiconductor material 314 on gate electrode 306 and semiconductor material 314 on source/drain contact region 319) to form titanium suicide 320 (i.e., TiSix). It is to be appreciated that titanium does not react with second sidewall spacer 318. Next, a selective etch is used to remove the unreacted titanium from second sidewall spacers 318 and leave titanium silicide 320. It is to be appreciated that other refractory metals, such as tungsten, can be used to form silicide 320. Additionally, it is to be noted that second sidewall spacers 318 must be formed thick enough to prevent silicide encroachment from electrically shorting the gate electrode to the source/drain contact regions. After completion of the silicide process, the preferred method of fabrication of a novel transistor 340 with a low resistance ultra shallow tip region is complete.
FIG. 4 is a cross-sectional view of a preferred alternative embodiment of the present invention. FIG. 4 is a MOS transistor 400 with a low resistance ultra shallow tip 410 and a pair of partially raised shallow junction source/drain contact regions 412. Transistor 400 is fabricated in the same manner as transistor 340 as illustrated and described in FIGS. 3a-3 e and accompanying specification, respectively. After the formation of sidewall spacers 318, a second selective deposition of semiconductor material is used to form second semiconductor material 420 onto the top surface of first deposited semiconductor material 314 adjacent to the outside edges of second sidewall spacers 318 and on semiconductor material 314 formed on gate electrode 306. Second semiconductor material 420 is formed thick enough, between 100 Å to 1500 Å, and to a concentration level sufficient, between 1×1019/cm3 to 5×1020/cm3, to provide an adequate source/drain contact region 412 for the fabricated device. It is to be appreciated that the resulting source/drain contact region 412 must be thick enough to provide adequate insurance against metal contact spiking. Second semiconductor material 420 is preferably formed of a silicon/germanium alloy doped with a p-type impurity, such as boron, to the desired conductivity level. It is to be appreciated that second sidewall spacer 318 needs to be formed thick enough to prevent excessive Miller capacitance from developing between second semiconductor material 420 and gate electrode 306 and thereby adversely effecting device performance.
A chemical-mechanical polishing process is preferably used at this time to remove second semiconductor material 420 from the top surface of gate electrode 306 in order to improve the topography of the fabricated transistor. Finally, a self-aligned-silicide (salicide) process is used to form silicide 320, onto second deposited semiconductor material 420 and on top of semiconductor material 314 on top of gate electrode 306.
FIG. 5 is a cross-sectional view of a preferred alternative embodiment of the present invention. FIG. 5 illustrates a buried channel MOS transistor 500 with a low resistance ultra shallow tip region 510. Transistor 500 can be fabricated in the same manner as transistor 340 except that semiconductor substrate 300 also includes a top deposited semiconductor material 524 with a thickness between 200 Å-1000 Å doped to an p-type conductivity with a concentration between 1×1017/cm3 to 1×1019/cm3. It is to be appreciated that the preferred dimensions of the present invention are relative to the top surface 526 of deposited semiconductor material 524 which in this embodiment is to be considered as the top surface of semiconductor substrate 300. It is to be appreciated that deposited semiconductor material 524 need not necessarily be a single homogenous semiconductor material, but may be comprised of a plurality of differently doped and different semiconductor materials. Buried channel transistor 500 exhibits increased channel carrier mobility which improves the devices' drive current and switching speed.
FIG. 6 is a cross-sectional view of a preferred alternative embodiment of the present invention. FIG. 6 shows an MOS transistor 600 with a low resistance ultra shallow tip region 610. Transistor 600 differs from the other disclosed embodiments of the present invention, in that recesses 312 are not formed in semiconductor substrate 300 prior to selective semiconductor material 319 deposition. Instead, semiconductor material 314 is deposited directly onto the top surface 304 of semiconductor substrate 300. All of the remaining fabrication steps, as disclosed in FIGS. 3b-3 f and accompanying specification, are utilized to complete fabrication of transistor 600. It is to be appreciated that with transistor 600 no semiconductor material is recessed into substrate 300 so that the solid-state diffusion step must first drive p-type dopants down (vertically) into substrate 300 and then drive them laterally (horizontally) beneath first sidewall spacer 310 to outside edges of gate electrode 306 to form ultra shallow low resistance tip region 610 of transistor 600. Although such a diffusion process has been shown to produce high performance devices, the junction of the ultra shallow low resistance tip region 610 is not as abrupt as when dopants are diffused in a single direction from a semiconductor material partially recessed into substrate 300. Although transistor 600 does not have as an abrupt of an ultra shallow tip region as other embodiments, the removal of the recess step does decrease process complexity and costs.
Many alternative embodiments and specifics of the present invention have been described, however, one skilled in the art will appreciate that many of the features in one embodiment are equally applicable to other embodiments. Additionally, although many specific dimensions, materials, and concentrations have been described, it is to be appreciated that these specific dimensions, materials, and concentrations are not to be taken as limiting. Additionally, one skilled in the art will appreciate the ability to scale the transistor of the present invention to form both larger and smaller devices. The scope of the present invention is not intended to be limited to the detailed description of the present invention and rather is to be determined by the claims which follow.
Thus, novel transistors with low resistance ultra shallow tip regions and their methods of fabrication have been described.

Claims (33)

We claim:
1. A method of forming a transistor comprising the steps of:
forming a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate;
forming a pair of sidewall spacers adjacent to opposite sides of said gate electrode;
forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; and
depositing epitaxial semiconductor material into said pair of recesses to form a pair of source/drain regions.
2. The method of forming a transistor of claim 1 further comprising the step of:
forming a second pair of sidewall spacers on said deposited semiconductor material and adjacent to the outside edges of said first pair of sidewall spacers.
3. The method of claim 2 further comprising the step of forming silicide on said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
4. The method of forming the transistor of claim 2 further comprising the step of implanting ions into said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
5. The method of claim 1 wherein said semiconductor material is a silicon germanium alloy.
6. The method of claim 1 wherein said pair of recesses are formed to a depth between 20-1,000Å beneath said first surface of said semiconductor substrate.
7. A method of forming a transistor comprising the steps of:
forming a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate;
forming a pair of sidewall spacers adjacent to opposite sides of said gate electrode;
forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode;
depositing a doped semiconductor material into said pair of recesses; and
diffusing dopants from said doped semiconductor material into said semiconductor substrate beneath said gate electrode.
8. The method of forming a transistor of claim 7 further comprising the step of:
forming a second pair of sidewall spacers on said deposited semiconductor material and adjacent to the outside edges of said first pair of sidewall spacers.
9. The method of claim 10 further comprising the step of forming silicide on said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
10. The method of forming the transistor of claim 8 further comprising the step of implanting ions into said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
11. The method of claim 7 wherein said semiconductor material is a silicon germanium alloy.
12. The method of claim 7 wherein said pair of recesses are formed to a depth between 20-1,000Å beneath said first surface of said semiconductor substrate.
13. The method of forming a transistor of claim 7 wherein said dopants are diffused utilizing a Rapid Thermal Process (RTP) at a temperature of between 800-1,000° C.
14. A method of forming a transistor comprising the steps of:
forming a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate;
forming a pair of sidewall spacers adjacent to opposite sides of said gate electrode;
forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; and
selectively depositing semiconductor material into said pair of recesses wherein said semiconductor material is deposited in said recesses above said first surface of said semiconductor substrate to form a pair of raised source/drain regions.
15. The method of forming a transistor of claim 14 further comprising the step of:
forming a second pair of sidewall spacers on said deposited semiconductor material and adjacent to the outside edges of said first pair of sidewall spacers.
16. The method of claim 15 further comprising the step of forming silicide on said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
17. The method of forming the transistor of claim 15 further comprising the step of implanting ions into said semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
18. The method of claim 14 wherein said semiconductor material is a silicon germanium alloy.
19. The method of claim 14 wherein said recesses are formed to a depth between 20-1,000Å beneath said first surface of said semiconductor substrate.
20. The method of claim 14 further comprising the step of diffusing dopants from said semiconductor material into said semiconductor substrate beneath said gate electrode.
21. The method of claim 20 wherein said dopants are diffused utilizing a rapid thermal process at a temperature between 20-1,000Å.
22. A transistor comprising:
a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate;
a pair of sidewall spacers adjacent to opposite sides of said gate electrode;
a pair of source/drain regions comprising deposited silicon germanium alloy film on opposite sides of said gate electrode and beneath said first surface of said semiconductor substrate.
23. The transistor of claim 22 wherein said deposited silicon germanium alloy film extends above said first surface of said semiconductor substrate.
24. The transistor of claim 22 wherein said deposited semiconductor material is a epitaxial silicon germanium alloy.
25. The transistor of claim 22 further comprising a second pair of sidewall spacers on said deposited silicon germanium alloy film and adjacent to the outside edges of said first pair of sidewall spacers.
26. The transistor of claim 25 further comprising silicide formed on said silicon germanium alloy films adjacent to the outside edges of said second pair of sidewall spacers.
27. The transistor of claim 22 further comprising silicide on said silicon germanium alloy film.
28. A transistor comprising:
a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate;
a pair of sidewall spacers adjacent to opposite sides of said gate electrode; and
a pair of source/drain regions comprising deposited epitaxial semiconductor material on opposite sides of said gate electrode and beneath said first surface of said semiconductor substrate;
29. The transistor of claim 28 wherein said deposited epitaxial semiconductor material extends above said first surface of said semiconductor substrate.
30. The transistor of claim 28 wherein said deposited epitaxial semiconductor material is a silicon germanium alloy.
31. The transistor of claim 28 further comprising a second pair of sidewall spacers on said deposited epitaxial semiconductor material and adjacent to the outside edges of said first pair of sidewall spacers.
32. The transistor of claim 31 further comprising silicide formed on said deposited epitaxial semiconductor material adjacent to the outside edges of said second pair of sidewall spacers.
33. The transistor of claim 28 further comprising silicide on said deposited epitaxial semiconductor material.
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Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020197786A1 (en) * 2000-01-24 2002-12-26 Chih-Chen Cho Applying epitaxial silicon in disposable spacer flow
US20030030091A1 (en) * 2001-08-13 2003-02-13 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US20030049919A1 (en) * 2001-09-13 2003-03-13 Nec Corporation Semiconductor device having smooth refractory metal silicide layers and process for fabrication thereof
US20030052375A1 (en) * 2001-09-20 2003-03-20 Hiroki Koga Semiconductor device and method of manufacturing the same
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US6537885B1 (en) * 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6563179B2 (en) * 1999-09-09 2003-05-13 Infineon Technologies MOS transistor and method for producing the transistor
US6703648B1 (en) * 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6727136B1 (en) * 2002-10-18 2004-04-27 Advanced Micro Devices, Inc. Formation of ultra-shallow depth source/drain extensions for MOS transistors
US6753606B2 (en) * 2000-03-06 2004-06-22 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
US20040164318A1 (en) * 2001-08-06 2004-08-26 Massachusetts Institute Of Technology Structures with planar strained layers
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
US20040192017A1 (en) * 2003-03-24 2004-09-30 Taiwan Semiconductor Manufacturing Co., Ltd Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
EP1478029A1 (en) 2003-05-14 2004-11-17 Samsung Electronics Co., Ltd. Mos transistor and method of fabricating the same
US6881635B1 (en) 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US20050093075A1 (en) * 2003-10-31 2005-05-05 Bentum Ralf V. Advanced technique for forming a transistor having raised drain and source regions
US20050106863A1 (en) * 2003-11-13 2005-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer manufacturing methods employing cleaning delay period
US20050116219A1 (en) * 2001-09-24 2005-06-02 Amberwave Systems Corporation RF circuits including transistors having strained material layers
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US20050195012A1 (en) * 2004-03-02 2005-09-08 Atsushi Sueoka Semiconductor device
US20050282344A1 (en) * 2003-01-07 2005-12-22 Samsung Electronics Co., Ltd. MOSFET and method of fabricating the same
WO2006074438A1 (en) * 2005-01-06 2006-07-13 Intel Corporation Device with stepped source/drain region profile
US20060199343A1 (en) * 2005-02-01 2006-09-07 Sug-Woo Jung Method of forming MOS transistor having fully silicided metal gate electrode
US20060246641A1 (en) * 2005-04-29 2006-11-02 Thorsten Kammler Technique for forming a contact insulation layer with enhanced stress transfer efficiency
US20070023847A1 (en) * 2005-07-26 2007-02-01 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20070096149A1 (en) * 2005-10-31 2007-05-03 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US20070132057A1 (en) * 2005-12-08 2007-06-14 Giuseppe Curello Active region spacer for semiconductor devices and method to form the same
US20080003746A1 (en) * 2006-06-30 2008-01-03 Giuseppe Curello Selective spacer formation on transistors of different classes on the same device
US20080121883A1 (en) * 2005-07-07 2008-05-29 Fujitsu Limited Semiconductor device and manufacturing method thereof
KR100834741B1 (en) 2006-07-26 2008-06-05 삼성전자주식회사 Semiconductor device and fabrication method thereof
US20080135873A1 (en) * 2006-12-08 2008-06-12 Amberwave Systems Corporation Inducement of Strain in a Semiconductor Layer
US20080142840A1 (en) * 2004-09-29 2008-06-19 Nick Lindert Metal gate transistors with epitaxial source and drain regions
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US20090146181A1 (en) * 2007-12-07 2009-06-11 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing diffused source/drain extensions
US7566606B2 (en) 2002-06-07 2009-07-28 Amberwave Systems Corporation Methods of fabricating semiconductor devices having strained dual channel layers
KR100911986B1 (en) 2002-12-23 2009-08-13 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device
US7776697B2 (en) 2001-09-21 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US8183627B2 (en) 2004-12-01 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid fin field-effect transistor structures and related methods
US8748292B2 (en) 2002-06-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
US20160155818A1 (en) * 2014-11-27 2016-06-02 United Microelectronics Corp. Method for fabricating semiconductor device
US9490364B2 (en) 2001-11-01 2016-11-08 Intel Corporation Semiconductor transistor having a stressed channel
US9502418B2 (en) 2014-10-02 2016-11-22 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US9761693B2 (en) 2014-11-27 2017-09-12 United Microelectronics Corp. Method for fabricating semiconductor device

Families Citing this family (226)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3256084B2 (en) * 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 Semiconductor integrated circuit and manufacturing method thereof
JP3761918B2 (en) * 1994-09-13 2006-03-29 株式会社東芝 Manufacturing method of semiconductor device
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
JP4027447B2 (en) 1996-04-24 2007-12-26 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US5811350A (en) * 1996-08-22 1998-09-22 Micron Technology, Inc. Method of forming contact openings and an electronic component formed from the same and other methods
US5827769A (en) * 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5869879A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
US5869866A (en) 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
JPH10173177A (en) * 1996-12-10 1998-06-26 Mitsubishi Electric Corp Manufacture of mis transistor
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP2925008B2 (en) * 1997-01-30 1999-07-26 日本電気株式会社 Method for manufacturing semiconductor device
US6197645B1 (en) * 1997-04-21 2001-03-06 Advanced Micro Devices, Inc. Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
US6518155B1 (en) * 1997-06-30 2003-02-11 Intel Corporation Device structure and method for reducing silicide encroachment
US6777759B1 (en) 1997-06-30 2004-08-17 Intel Corporation Device structure and method for reducing silicide encroachment
US6010954A (en) * 1997-07-11 2000-01-04 Chartered Semiconductor Manufacturing, Ltd. Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices
KR100302187B1 (en) * 1997-10-08 2001-11-22 윤종용 Method for fabricating semiconductor device
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
JP2967477B2 (en) * 1997-11-26 1999-10-25 日本電気株式会社 Method for manufacturing semiconductor device
US7105411B1 (en) 1997-12-18 2006-09-12 Micron Technology, Inc. Methods of forming a transistor gate
JP2002509361A (en) 1997-12-18 2002-03-26 マイクロン テクノロジー， インク． Semiconductor manufacturing method and field effect transistor
US6121100A (en) * 1997-12-31 2000-09-19 Intel Corporation Method of fabricating a MOS transistor with a raised source/drain extension
KR100257075B1 (en) * 1998-01-13 2000-05-15 김영환 Semiconductor device and method for manufacturing the same
US6153456A (en) * 1998-01-14 2000-11-28 Vlsi Technology, Inc. Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask
US6177323B1 (en) * 1998-03-02 2001-01-23 Texas Instruments - Acer Incorporated Method to form MOSFET with an elevated source/drain for PMOSFET
US5989967A (en) * 1998-04-30 1999-11-23 Advanced Micro Devices, Inc. Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
KR100475034B1 (en) * 1998-06-08 2005-05-27 삼성전자주식회사 Most transistors with elevated source / drain regions and methods of manufacturing the same
US6124610A (en) 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
KR100343135B1 (en) 1998-07-24 2002-09-18 삼성전자 주식회사 Method for fabricating of MOS transistor to prevent short channel effect
US6198142B1 (en) 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication
US6261948B1 (en) 1998-07-31 2001-07-17 Micron Technology, Inc. Method of forming contact openings
US6380023B2 (en) * 1998-09-02 2002-04-30 Micron Technology, Inc. Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
US5923986A (en) * 1998-09-17 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a wide upper top spacer to prevent salicide bridge
JP2000156502A (en) * 1998-09-21 2000-06-06 Texas Instr Inc <Ti> Integrated circuit and method
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
JP2003526198A (en) * 1998-12-16 2003-09-02 インテル・コーポレーション Amorphization of substrate to prevent intrusion of silicide into channel region of field effect transistor
JP4068746B2 (en) * 1998-12-25 2008-03-26 株式会社ルネサステクノロジ Semiconductor integrated circuit device
KR20000050568A (en) * 1999-01-12 2000-08-05 윤종용 MOS transistor having raised source/drain structure and the fabrication method thereof
KR100308133B1 (en) * 1999-01-12 2001-09-26 김영환 Method for fablicating a MOS transistor having dual gate
JP4521542B2 (en) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor substrate
KR20000065719A (en) * 1999-04-08 2000-11-15 김영환 Semiconductor device and fabricating method thereof
KR100332106B1 (en) * 1999-06-29 2002-04-10 박종섭 Method of manufacturing a transistor in a semiconductor device
US6737710B2 (en) * 1999-06-30 2004-05-18 Intel Corporation Transistor structure having silicide source/drain extensions
WO2001003200A1 (en) * 1999-06-30 2001-01-11 Infineon Technologies Ag Insulation of gate electrodes and production method
KR100341182B1 (en) * 1999-11-30 2002-06-20 윤종용 Method of forming mos transistor in semiconductor device
US6541343B1 (en) * 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
EP1183727A1 (en) * 2000-02-17 2002-03-06 Koninklijke Philips Electronics N.V. SEMICONDUCTOR DEVICE WITH AN INTEGRATED CMOS CIRCUIT WITH MOS TRANSISTORS HAVING SILICON-GERMANIUM (Si 1-x?Ge x?) GATE ELECTRODES, AND METHOD OF MANUFACTURING SAME
US6274420B1 (en) * 2000-02-23 2001-08-14 Advanced Micro Devices, Inc. Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides
US6420250B1 (en) 2000-03-03 2002-07-16 Micron Technology, Inc. Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
KR100628253B1 (en) * 2000-08-09 2006-09-27 매그나칩 반도체 유한회사 Method for Forming Self-Aligned Silcide of Semiconductor Device
JP2002124665A (en) * 2000-10-12 2002-04-26 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6426247B1 (en) * 2001-01-17 2002-07-30 International Business Machines Corporation Low bitline capacitance structure and method of making same
US6323073B1 (en) * 2001-01-19 2001-11-27 United Microelectronics Corp. Method for forming doped regions on an SOI device
US6767777B2 (en) * 2001-02-06 2004-07-27 Texas Instruments Incorporated Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers
US6380043B1 (en) * 2001-02-12 2002-04-30 Advanced Micro Devices, Inc. Low temperature process to form elevated drain and source of a field effect transistor having high-K gate dielectric
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6670263B2 (en) * 2001-03-10 2003-12-30 International Business Machines Corporation Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
US6506650B1 (en) * 2001-04-27 2003-01-14 Advanced Micro Devices, Inc. Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile
US6541317B2 (en) * 2001-05-03 2003-04-01 International Business Machines Corporation Polysilicon doped transistor
US20020171107A1 (en) * 2001-05-21 2002-11-21 Baohong Cheng Method for forming a semiconductor device having elevated source and drain regions
US6413829B1 (en) * 2001-06-01 2002-07-02 Advanced Micro Devices, Inc. Field effect transistor in SOI technology with schottky-contact extensions
US6465847B1 (en) * 2001-06-11 2002-10-15 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US6614079B2 (en) 2001-07-19 2003-09-02 International Business Machines Corporation All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
US6649460B2 (en) 2001-10-25 2003-11-18 International Business Machines Corporation Fabricating a substantially self-aligned MOSFET
KR100406537B1 (en) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 Method for fabricating semiconductor device
JP2003188274A (en) * 2001-12-19 2003-07-04 Toshiba Corp Semiconductor device and its manufacturing method
US6891266B2 (en) * 2002-02-14 2005-05-10 Mia-Com RF transition for an area array package
US20030166323A1 (en) * 2002-03-01 2003-09-04 Infineon Technologies North America Corp. Raised extension structure for high performance cmos
US6716710B1 (en) * 2002-04-19 2004-04-06 Advanced Micro Devices, Inc. Using a first liner layer as a spacer in a semiconductor device
WO2003105206A1 (en) * 2002-06-10 2003-12-18 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US20040033677A1 (en) * 2002-08-14 2004-02-19 Reza Arghavani Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
DE10246718A1 (en) * 2002-10-07 2004-04-22 Infineon Technologies Ag Field effect transistor comprises a semiconductor substrate, a source recess and a drain recess formed in the substrate, a recessed insulating layer, an electrically conducting filler layer, a gate dielectric, and a gate layer
FR2846789B1 (en) * 2002-11-05 2005-06-24 St Microelectronics Sa MOS TRANSISTOR SEMICONDUCTOR DEVICE WITH ENGRAVED STOP LAYER HAVING IMPROVED RESIDUAL STRESS AND METHOD OF MANUFACTURING SUCH SEMICONDUCTOR DEVICE
KR100641494B1 (en) * 2002-12-30 2006-10-31 동부일렉트로닉스 주식회사 Method for manufacturing semiconductor device
JP2004241755A (en) * 2003-01-15 2004-08-26 Renesas Technology Corp Semiconductor device
US6878583B2 (en) * 2003-02-05 2005-04-12 Taiwan Semiconductor Manufacturing Company Integration method to enhance p+ gate activation
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US20040188765A1 (en) * 2003-03-28 2004-09-30 International Business Machines Corporation Cmos device integration for low external resistance
FR2854276A1 (en) * 2003-04-24 2004-10-29 Koninkl Philips Electronics Nv Semiconductor device useful as a transistor comprises source and drain tip regions with a lower melting point than the semiconductor substrate
JP4305192B2 (en) * 2003-04-25 2009-07-29 セイコーエプソン株式会社 Thin film semiconductor device manufacturing method, electro-optical device manufacturing method
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7012024B2 (en) * 2003-08-15 2006-03-14 Micron Technology, Inc. Methods of forming a transistor with an integrated metal silicide gate electrode
KR100546369B1 (en) * 2003-08-22 2006-01-26 삼성전자주식회사 High integrated semiconductor device with silicide layer securing contact margin and method for manufacturing the same
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
DE10351008B4 (en) * 2003-10-31 2008-07-10 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating transistors having elevated drain and source regions of different height and a semiconductor device
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
US7012014B2 (en) * 2003-12-04 2006-03-14 Taiwan Semiconductor Manufacturing Co., Ltd Recessed gate structure with reduced current leakage and overlap capacitance
US7244654B2 (en) * 2003-12-31 2007-07-17 Texas Instruments Incorporated Drive current improvement from recessed SiGe incorporation close to gate
US20050145956A1 (en) * 2004-01-05 2005-07-07 Taiwan Semiconductor Manufacturing Co. Devices with high-k gate dielectric
US20050179111A1 (en) * 2004-02-12 2005-08-18 Iwen Chao Semiconductor device with low resistive path barrier
US7402207B1 (en) 2004-05-05 2008-07-22 Advanced Micro Devices, Inc. Method and apparatus for controlling the thickness of a selective epitaxial growth layer
US20050274951A1 (en) * 2004-06-14 2005-12-15 Howard Gregory E MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication
JP4837902B2 (en) 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 Semiconductor device
US7135724B2 (en) * 2004-09-29 2006-11-14 International Business Machines Corporation Structure and method for making strained channel field effect transistor using sacrificial spacer
US7241700B1 (en) 2004-10-20 2007-07-10 Advanced Micro Devices, Inc. Methods for post offset spacer clean for improved selective epitaxy silicon growth
US7456062B1 (en) 2004-10-20 2008-11-25 Advanced Micro Devices, Inc. Method of forming a semiconductor device
US7402485B1 (en) 2004-10-20 2008-07-22 Advanced Micro Devices, Inc. Method of forming a semiconductor device
US7064025B1 (en) * 2004-12-02 2006-06-20 International Business Machines Corporation Method for forming self-aligned dual salicide in CMOS technologies
US7026232B1 (en) * 2004-12-23 2006-04-11 Texas Instruments Incorporated Systems and methods for low leakage strained-channel transistor
JP4369359B2 (en) 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
JP4361880B2 (en) * 2005-01-11 2009-11-11 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
CN1808268B (en) * 2005-01-18 2010-10-06 中芯国际集成电路制造(上海)有限公司 Metal hard mask method and structure for strained silicon MOS transistor
US7553718B2 (en) * 2005-01-28 2009-06-30 Texas Instruments Incorporated Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps
JP4369379B2 (en) 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7211481B2 (en) * 2005-02-18 2007-05-01 Texas Instruments Incorporated Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer
JP2006229040A (en) * 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd Method and apparatus for heat treatment
JP4867176B2 (en) * 2005-02-25 2012-02-01 ソニー株式会社 Manufacturing method of semiconductor device
JP4515305B2 (en) * 2005-03-29 2010-07-28 富士通セミコンダクター株式会社 P-channel MOS transistor and method for manufacturing the same, and method for manufacturing a semiconductor integrated circuit device
WO2006111888A1 (en) * 2005-04-20 2006-10-26 Koninklijke Philips Electronics N.V. A strained integrated circuit and a method of manufacturing the same
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
JP4630728B2 (en) * 2005-05-26 2011-02-09 株式会社東芝 Semiconductor device and manufacturing method thereof
US7553732B1 (en) 2005-06-13 2009-06-30 Advanced Micro Devices, Inc. Integration scheme for constrained SEG growth on poly during raised S/D processing
US20060281271A1 (en) * 2005-06-13 2006-12-14 Advanced Micro Devices, Inc. Method of forming a semiconductor device having an epitaxial layer and device thereof
US7732289B2 (en) * 2005-07-05 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a MOS device with an additional layer
CN100463143C (en) * 2005-07-07 2009-02-18 中芯国际集成电路制造(上海)有限公司 Strain source-drain CMOS integrating method with oxide separation layer
US7902008B2 (en) * 2005-08-03 2011-03-08 Globalfoundries Inc. Methods for fabricating a stressed MOS device
KR100618908B1 (en) * 2005-08-12 2006-09-05 삼성전자주식회사 Semiconductor device for improving resistance of gate and method of manufacturing the same
US7470943B2 (en) * 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US7572705B1 (en) 2005-09-21 2009-08-11 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing a semiconductor device
US7326601B2 (en) * 2005-09-26 2008-02-05 Advanced Micro Devices, Inc. Methods for fabrication of a stressed MOS device
KR100654360B1 (en) * 2005-10-27 2006-12-08 삼성전자주식회사 Semiconductor integrated circuit device and fabrication method for the same
US7566609B2 (en) * 2005-11-29 2009-07-28 International Business Machines Corporation Method of manufacturing a semiconductor structure
US7618856B2 (en) * 2005-12-06 2009-11-17 United Microelectronics Corp. Method for fabricating strained-silicon CMOS transistors
KR100741908B1 (en) * 2005-12-30 2007-07-24 동부일렉트로닉스 주식회사 Method of fabricating semiconductor device
EP1833094B1 (en) * 2006-03-06 2011-02-02 STMicroelectronics (Crolles 2) SAS Formation of shallow SiGe conduction channel
DE102006015087B4 (en) * 2006-03-31 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale Process for the production of transistors
DE102006015090B4 (en) * 2006-03-31 2008-03-13 Advanced Micro Devices, Inc., Sunnyvale Method for producing different embedded deformation layers in transistors
US7410875B2 (en) * 2006-04-06 2008-08-12 United Microelectronics Corp. Semiconductor structure and fabrication thereof
US8207523B2 (en) * 2006-04-26 2012-06-26 United Microelectronics Corp. Metal oxide semiconductor field effect transistor with strained source/drain extension layer
US7935590B2 (en) * 2006-05-11 2011-05-03 United Microelectronics Corp. Method of manufacturing metal oxide semiconductor and complementary metal oxide semiconductor
DE102006030264B4 (en) * 2006-06-30 2008-08-28 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating transistors having a biaxially-deformed channel caused by silicon germanium in the gate electrode
US20080076236A1 (en) * 2006-09-21 2008-03-27 Jih-Shun Chiang Method for forming silicon-germanium epitaxial layer
US7494862B2 (en) * 2006-09-29 2009-02-24 Intel Corporation Methods for uniform doping of non-planar transistor structures
US7800182B2 (en) * 2006-11-20 2010-09-21 Infineon Technologies Ag Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
DE102007004862B4 (en) * 2007-01-31 2014-01-30 Globalfoundries Inc. A method of fabricating Si-Ge containing drain / source regions in lower Si / Ge loss transistors
US20080272437A1 (en) * 2007-05-01 2008-11-06 Doris Bruce B Threshold Adjustment for High-K Gate Dielectric CMOS
US8574979B2 (en) * 2007-05-18 2013-11-05 Texas Instruments Incorporated Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US7892930B2 (en) * 2007-10-08 2011-02-22 Texas Instruments Incorporated Method to improve transistor tox using SI recessing with no additional masking steps
US20090186475A1 (en) * 2008-01-21 2009-07-23 Shyh-Fann Ting Method of manufacturing a MOS transistor
KR101082096B1 (en) * 2008-01-21 2011-11-10 주식회사 하이닉스반도체 The method for manufacturing semiconductor device using salicide process
US8293631B2 (en) 2008-03-13 2012-10-23 International Business Machines Corporation Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
KR101448172B1 (en) * 2008-07-02 2014-10-08 삼성전자주식회사 semiconductor device and manufacturing method with the same
DE102009006800B4 (en) * 2009-01-30 2013-01-31 Advanced Micro Devices, Inc. Process for the production of transistors and corresponding semiconductor component
DE102009006884B4 (en) * 2009-01-30 2011-06-30 Advanced Micro Devices, Inc., Calif. A method of fabricating a transistor device having in situ generated drain and source regions with a strain-inducing alloy and a gradually varying dopant profile and corresponding transistor device
US8274110B2 (en) * 2009-05-20 2012-09-25 Micron Technology, Inc. Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
JP5446558B2 (en) * 2009-08-04 2014-03-19 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8487354B2 (en) * 2009-08-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving selectivity of epi process
JP5434365B2 (en) * 2009-08-24 2014-03-05 ソニー株式会社 Semiconductor device and manufacturing method thereof
US8067282B2 (en) * 2009-10-08 2011-11-29 United Microelectronics Corp. Method for selective formation of trench
US8421164B2 (en) 2010-01-05 2013-04-16 Micron Technology, Inc. Memory cell array with semiconductor selection device for multiple memory cells
CN101807605B (en) * 2010-02-05 2015-05-06 上海华虹宏力半导体制造有限公司 Semiconductor device and manufacture method thereof
JP5236676B2 (en) * 2010-03-18 2013-07-17 ルネサスエレクトロニクス株式会社 Static random access memory
US8278166B2 (en) * 2010-07-16 2012-10-02 United Microelectronics Corp. Method of manufacturing complementary metal oxide semiconductor device
CN102468164B (en) 2010-10-29 2014-10-08 中国科学院微电子研究所 Transistor and manufacture method thereof
US8426265B2 (en) 2010-11-03 2013-04-23 International Business Machines Corporation Method for growing strain-inducing materials in CMOS circuits in a gate first flow
US8778767B2 (en) 2010-11-18 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and fabrication methods thereof
KR101195269B1 (en) * 2011-02-15 2012-11-14 에스케이하이닉스 주식회사 Method of fabricating semiconductor device having low contact resistance
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
JP5360119B2 (en) * 2011-04-18 2013-12-04 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8969154B2 (en) 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8574995B2 (en) * 2011-11-10 2013-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain doping method in 3D devices
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
CN103325684B (en) * 2012-03-23 2016-03-02 中国科学院微电子研究所 A kind of semiconductor structure and manufacture method thereof
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
WO2013180244A1 (en) * 2012-05-31 2013-12-05 富士電機株式会社 Method for manufacturing semiconductor device
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
CN103515239A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing ultra-thin SOI semiconductor device and ultra-thin SOI semiconductor device
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
JP5488675B2 (en) * 2012-11-14 2014-05-14 ソニー株式会社 Manufacturing method of semiconductor device
US8900958B2 (en) 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US8853039B2 (en) 2013-01-17 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction for formation of epitaxial layer in source and drain regions
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US9142673B2 (en) * 2013-07-31 2015-09-22 Globalfoundries Inc. Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US10157995B2 (en) * 2013-08-09 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating junction formation of transistors with contact formation
KR102135303B1 (en) 2013-12-27 2020-07-17 인텔 코포레이션 Diffused tip extension transistor
KR102157839B1 (en) * 2014-01-21 2020-09-18 삼성전자주식회사 Methods of selectively growing source and drain regions of fin field effect transistor
US9214551B2 (en) 2014-02-19 2015-12-15 United Microelectronics Corp. Method for fabricating semiconductor device, and semiconductor device made thereby
JP2015228418A (en) * 2014-05-30 2015-12-17 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device and manufacturing method of the same
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9716160B2 (en) * 2014-08-01 2017-07-25 International Business Machines Corporation Extended contact area using undercut silicide extensions
DE102014111140B4 (en) * 2014-08-05 2019-08-14 Infineon Technologies Austria Ag Semiconductor device with field effect structures with different gate materials and method for the production thereof
US11049939B2 (en) 2015-08-03 2021-06-29 Semiwise Limited Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation
TWI680502B (en) * 2016-02-03 2019-12-21 聯華電子股份有限公司 Semiconductor device and method of manufacturing the same
CN106206316A (en) * 2016-07-27 2016-12-07 上海集成电路研发中心有限公司 A kind of manufacture method of mos field effect transistor
US10879354B2 (en) * 2016-11-28 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
CN113629144B (en) * 2020-05-08 2023-07-07 长鑫存储技术有限公司 Semiconductor device and method for manufacturing the same
US11373696B1 (en) 2021-02-19 2022-06-28 Nif/T, Llc FFT-dram

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6313379A (en) 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
EP0401174A1 (en) 1989-05-02 1990-12-05 STMicroelectronics S.r.l. Surface field effect transistor with depressed source and/or drain areas for ulsi integrated devices
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
WO1991004577A1 (en) 1989-09-22 1991-04-04 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron misfet device
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5285088A (en) * 1991-09-17 1994-02-08 Nec Corporation High electron mobility transistor
US5336903A (en) * 1992-07-27 1994-08-09 North Carolina State University At Raleigh Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures
US5405795A (en) * 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4133704A (en) * 1977-01-17 1979-01-09 General Motors Corporation Method of forming diodes by amorphous implantations and concurrent annealing, monocrystalline reconversion and oxide passivation in <100> N-type silicon
JPS6151959A (en) * 1984-08-22 1986-03-14 Toshiba Corp Manufacture of semiconductor device
CA1216962A (en) * 1985-06-28 1987-01-20 Hussein M. Naguib Mos device processing
US4885617A (en) * 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
US5006476A (en) * 1988-09-07 1991-04-09 North American Philips Corp., Signetics Division Transistor manufacturing process using three-step base doping
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
JP2921889B2 (en) * 1989-11-27 1999-07-19 株式会社東芝 Method for manufacturing semiconductor device
US5231042A (en) * 1990-04-02 1993-07-27 National Semiconductor Corporation Formation of silicide contacts using a sidewall oxide process
JPH04350942A (en) * 1991-05-29 1992-12-04 Nec Corp Manufacture of semiconductor device
US5341014A (en) * 1992-01-07 1994-08-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and a method of fabricating the same
US5393685A (en) * 1992-08-10 1995-02-28 Taiwan Semiconductor Manufacturing Company Peeling free metal silicide films using rapid thermal anneal
US5352631A (en) * 1992-12-16 1994-10-04 Motorola, Inc. Method for forming a transistor having silicided regions
JPH0786579A (en) * 1993-09-14 1995-03-31 Toshiba Corp Semiconductor device
US5409847A (en) * 1993-10-27 1995-04-25 Matsushita Electric Industrial Co., Ltd. Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature
US5478776A (en) * 1993-12-27 1995-12-26 At&T Corp. Process for fabricating integrated circuit containing shallow junction using dopant source containing organic polymer or ammonium silicate
KR0135147B1 (en) * 1994-07-21 1998-04-22 문정환 Manufacturing method of transistor
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5538909A (en) * 1995-01-19 1996-07-23 United Microelectronics Corporation Method of making a shallow trench large-angle-tilt implanted drain device
US5569624A (en) * 1995-06-05 1996-10-29 Regents Of The University Of California Method for shallow junction formation
WO1997047159A1 (en) * 1996-06-03 1997-12-11 Kanagawa Prefectural Government Process for producing infrared emitting device and infrared emitting device produced by the process
TW346652B (en) * 1996-11-09 1998-12-01 Winbond Electronics Corp Semiconductor production process

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6313379A (en) 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
EP0401174A1 (en) 1989-05-02 1990-12-05 STMicroelectronics S.r.l. Surface field effect transistor with depressed source and/or drain areas for ulsi integrated devices
WO1991004577A1 (en) 1989-09-22 1991-04-04 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron misfet device
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5397909A (en) * 1990-10-12 1995-03-14 Texas Instruments Incorporated High-performance insulated-gate field-effect transistor
US5285088A (en) * 1991-09-17 1994-02-08 Nec Corporation High electron mobility transistor
US5336903A (en) * 1992-07-27 1994-08-09 North Carolina State University At Raleigh Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures
US5405795A (en) * 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Disclosed Anonymously; "Method for Making Devices having Reduced Field Gradients at Junction Edges"; Jul., 1989, No. 303, New York, US; 2244 Research Disclosure; pp. 496.
Mark Rodder, Member, IEEE, and D. Yeakley; "Raised Source/Drain MOSFET with Dual Sidewall Spacers"; 8179 IEEE Electron Device Letters 12(1992) Mar., No. 3, New York, US; pp. 89-91.
Momose, et al.; "Tunneling Gate Oxide Appraoch to Ultra-High Current Drive in Small-Geometry MOSFETS"; International Electron Devices Meeting 1994 IEEE; Dec. 11-14, 1994; pp. 25.1.1-25.1.4.

Cited By (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563179B2 (en) * 1999-09-09 2003-05-13 Infineon Technologies MOS transistor and method for producing the transistor
US7342273B2 (en) 2000-01-24 2008-03-11 Micron Technology, Inc. Applying epitaxial silicon in disposable spacer flow
US7037775B2 (en) 2000-01-24 2006-05-02 Micron Technology, Inc. Applying epitaxial silicon in disposable spacer flow
US7884427B2 (en) 2000-01-24 2011-02-08 Round Rock Research, Llc Applying epitaxial silicon in disposable spacer flow
US20060091479A1 (en) * 2000-01-24 2006-05-04 Chih-Chen Cho Applying epitaxial silicon in disposable spacer flow
US20040219756A1 (en) * 2000-01-24 2004-11-04 Chih-Chen Cho Applying epitaxial silicon in disposable spacer flow
US20020197786A1 (en) * 2000-01-24 2002-12-26 Chih-Chen Cho Applying epitaxial silicon in disposable spacer flow
US20110124171A1 (en) * 2000-01-24 2011-05-26 Round Rock Research, Llc Applying epitaxial silicon in disposable spacer flow
US6756264B2 (en) * 2000-01-24 2004-06-29 Micron Technology, Inc. Applying epitaxial silicon in disposable spacer flow
US8232167B2 (en) 2000-01-24 2012-07-31 Round Rock Research, Llc Applying epitaxial silicon in disposable spacer flow
US7102234B2 (en) 2000-03-06 2006-09-05 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
US6753606B2 (en) * 2000-03-06 2004-06-22 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US8436336B2 (en) 2001-06-18 2013-05-07 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US20040164318A1 (en) * 2001-08-06 2004-08-26 Massachusetts Institute Of Technology Structures with planar strained layers
US7141820B2 (en) 2001-08-06 2006-11-28 Amberwave Systems Corporation Structures with planar strained layers
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US20080265299A1 (en) * 2001-08-13 2008-10-30 Mayank Bulsara Strained channel dynamic random access memory devices
US7410861B2 (en) 2001-08-13 2008-08-12 Amberwave Systems Corporation Methods of forming dynamic random access memory trench capacitors
US20050067647A1 (en) * 2001-08-13 2005-03-31 Amberwave Systems Corporation Methods of forming dynamic random access memory trench capacitors
US20030030091A1 (en) * 2001-08-13 2003-02-13 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US20050035389A1 (en) * 2001-08-13 2005-02-17 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US8253181B2 (en) 2001-08-13 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel dynamic random access memory devices
US7408214B2 (en) 2001-08-13 2008-08-05 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US6710407B2 (en) * 2001-09-13 2004-03-23 Nec Electronics Corporation Semiconductor device having smooth refractory metal silicide layers and process for fabrication thereof
US20030049919A1 (en) * 2001-09-13 2003-03-13 Nec Corporation Semiconductor device having smooth refractory metal silicide layers and process for fabrication thereof
US6914309B2 (en) * 2001-09-20 2005-07-05 Nec Corporation Semiconductor device with double sidewall spacer and layered contact
US20050196944A1 (en) * 2001-09-20 2005-09-08 Hiroki Koga Semiconductor device and method of manufacturing the same
US7709366B2 (en) 2001-09-20 2010-05-04 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
US20100200925A1 (en) * 2001-09-20 2010-08-12 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
US20030052375A1 (en) * 2001-09-20 2003-03-20 Hiroki Koga Semiconductor device and method of manufacturing the same
US7884353B2 (en) 2001-09-21 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7846802B2 (en) 2001-09-21 2010-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7776697B2 (en) 2001-09-21 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7906776B2 (en) 2001-09-24 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US20050116219A1 (en) * 2001-09-24 2005-06-02 Amberwave Systems Corporation RF circuits including transistors having strained material layers
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US9735270B2 (en) 2001-11-01 2017-08-15 Intel Corporation Semiconductor transistor having a stressed channel
US9490364B2 (en) 2001-11-01 2016-11-08 Intel Corporation Semiconductor transistor having a stressed channel
US6537885B1 (en) * 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US7566606B2 (en) 2002-06-07 2009-07-28 Amberwave Systems Corporation Methods of fabricating semiconductor devices having strained dual channel layers
US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
US8748292B2 (en) 2002-06-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US6727136B1 (en) * 2002-10-18 2004-04-27 Advanced Micro Devices, Inc. Formation of ultra-shallow depth source/drain extensions for MOS transistors
US7071065B1 (en) 2002-10-29 2006-07-04 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6703648B1 (en) * 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
KR100911986B1 (en) 2002-12-23 2009-08-13 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device
US20050282344A1 (en) * 2003-01-07 2005-12-22 Samsung Electronics Co., Ltd. MOSFET and method of fabricating the same
US7696051B2 (en) * 2003-01-07 2010-04-13 Samsung Electronics Co., Ltd. Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate
US6960781B2 (en) 2003-03-07 2005-11-01 Amberwave Systems Corporation Shallow trench isolation process
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
US20040192017A1 (en) * 2003-03-24 2004-09-30 Taiwan Semiconductor Manufacturing Co., Ltd Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
US6830996B2 (en) 2003-03-24 2004-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
EP1478029A1 (en) 2003-05-14 2004-11-17 Samsung Electronics Co., Ltd. Mos transistor and method of fabricating the same
US20040227164A1 (en) * 2003-05-14 2004-11-18 Samsung Electronics Co., Ltd. MOS transistor with elevated source/drain structure and method of fabricating the same
KR100621546B1 (en) * 2003-05-14 2006-09-13 삼성전자주식회사 Method and Apparatus For Making MOS Transistors With Elevated Source/Drain
EP2565931A1 (en) 2003-05-14 2013-03-06 Samsung Electronics Co., Ltd. MOS Transistor
US20060163558A1 (en) * 2003-05-14 2006-07-27 Samsung Electronics, Co., Ltd. MOS transistor with elevated source/drain structure
US7368792B2 (en) 2003-05-14 2008-05-06 Samsung Electronics Co., Ltd. MOS transistor with elevated source/drain structure
US7033895B2 (en) * 2003-05-14 2006-04-25 Samsung Electronics Co., Ltd. Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process
US20050093075A1 (en) * 2003-10-31 2005-05-05 Bentum Ralf V. Advanced technique for forming a transistor having raised drain and source regions
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
US6933157B2 (en) 2003-11-13 2005-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer manufacturing methods employing cleaning delay period
US20050106863A1 (en) * 2003-11-13 2005-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer manufacturing methods employing cleaning delay period
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US20050195012A1 (en) * 2004-03-02 2005-09-08 Atsushi Sueoka Semiconductor device
US6881635B1 (en) 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US20080142840A1 (en) * 2004-09-29 2008-06-19 Nick Lindert Metal gate transistors with epitaxial source and drain regions
US8344452B2 (en) * 2004-09-29 2013-01-01 Intel Corporation Metal gate transistors with raised source and drain regions formed on heavily doped substrate
US8183627B2 (en) 2004-12-01 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid fin field-effect transistor structures and related methods
WO2006074438A1 (en) * 2005-01-06 2006-07-13 Intel Corporation Device with stepped source/drain region profile
US7335959B2 (en) 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
US20060199343A1 (en) * 2005-02-01 2006-09-07 Sug-Woo Jung Method of forming MOS transistor having fully silicided metal gate electrode
US7354838B2 (en) * 2005-04-29 2008-04-08 Advanced Micro Devices, Inc. Technique for forming a contact insulation layer with enhanced stress transfer efficiency
US20060246641A1 (en) * 2005-04-29 2006-11-02 Thorsten Kammler Technique for forming a contact insulation layer with enhanced stress transfer efficiency
US20080121883A1 (en) * 2005-07-07 2008-05-29 Fujitsu Limited Semiconductor device and manufacturing method thereof
US7728393B2 (en) 2005-07-26 2010-06-01 Samsung Electronics Co., Ltd. Semiconductor device
US20070023847A1 (en) * 2005-07-26 2007-02-01 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US8790980B2 (en) 2005-10-31 2014-07-29 International Business Machines Corporation (Ibm) Implant damage control by in-situ C doping during sige epitaxy for device applications
US20110223737A1 (en) * 2005-10-31 2011-09-15 Globalfoundries Singapore Pte. Ltd. Implant damage control by in-situ c doping during sige epitaxy for device applications
US8652892B2 (en) 2005-10-31 2014-02-18 International Business Machines Corporation (Ibm) Implant damage control by in-situ C doping during sige epitaxy for device applications
US20070096149A1 (en) * 2005-10-31 2007-05-03 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7560780B2 (en) * 2005-12-08 2009-07-14 Intel Corporation Active region spacer for semiconductor devices and method to form the same
US20070132057A1 (en) * 2005-12-08 2007-06-14 Giuseppe Curello Active region spacer for semiconductor devices and method to form the same
US20080003746A1 (en) * 2006-06-30 2008-01-03 Giuseppe Curello Selective spacer formation on transistors of different classes on the same device
US8174060B2 (en) 2006-06-30 2012-05-08 Intel Corporation Selective spacer formation on transistors of different classes on the same device
US8154067B2 (en) 2006-06-30 2012-04-10 Intel Corporation Selective spacer formation on transistors of different classes on the same device
US20110157854A1 (en) * 2006-06-30 2011-06-30 Giuseppe Curello Selective spacer formation on transistors of different classes on the same device
US7541239B2 (en) 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
US20090189193A1 (en) * 2006-06-30 2009-07-30 Intel Corporation Selective spacer formation on transistors of different classes on the same device
KR100834741B1 (en) 2006-07-26 2008-06-05 삼성전자주식회사 Semiconductor device and fabrication method thereof
US7897493B2 (en) 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
US20080135873A1 (en) * 2006-12-08 2008-06-12 Amberwave Systems Corporation Inducement of Strain in a Semiconductor Layer
US20090146181A1 (en) * 2007-12-07 2009-06-11 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing diffused source/drain extensions
US9502418B2 (en) 2014-10-02 2016-11-22 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US9576961B2 (en) 2014-10-02 2017-02-21 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US9887198B2 (en) 2014-10-02 2018-02-06 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US9905479B2 (en) 2014-10-02 2018-02-27 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US10580704B2 (en) 2014-10-02 2020-03-03 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US10622259B2 (en) 2014-10-02 2020-04-14 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US20160155818A1 (en) * 2014-11-27 2016-06-02 United Microelectronics Corp. Method for fabricating semiconductor device
US9761693B2 (en) 2014-11-27 2017-09-12 United Microelectronics Corp. Method for fabricating semiconductor device

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US5710450A (en) 1998-01-20
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EP0803131A4 (en) 1998-06-17
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EP1253632A2 (en) 2002-10-30
JP5198823B2 (en) 2013-05-15

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