US5349307A - Constant current generation circuit of current mirror type having equal input and output currents - Google Patents

Constant current generation circuit of current mirror type having equal input and output currents Download PDF

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US5349307A
US5349307A US08/021,750 US2175093A US5349307A US 5349307 A US5349307 A US 5349307A US 2175093 A US2175093 A US 2175093A US 5349307 A US5349307 A US 5349307A
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transistor
input
constant current
output
current path
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Kiyoshi Inagaki
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NEC Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology

Definitions

  • the present invention relates to a constant current generation circuit, and more specifically to a constant current generation circuit composed of a current mirror circuit.
  • the constant current generation circuit shown in FIG. 1 of this Japanese patent laid-open publication includes a constant current source 1 connected in series to an input current path of a MOS transistor current mirror circuit 2, and a bipolar transistor current mirror circuit 3 having an input current path connected in series through a load resistor R 3 to an output current path of the MOS transistor current mirror circuit 2, an output current path of the bipolar transistor current mirror circuit 3 constituting an output of the constant current generation circuit.
  • the constant current source 1 includes a resistor R 2 and three series-connected diodes D 1 , D 2 and D 3 , which are connected in series between a ground and a low potential power supply line V EE .
  • a constant voltage obtained across the three series-connected diodes D 1 , D 2 and D 3 is applied to a base of an NPN bipolar transistor Q 4 , so that a constant current I 0 passes through the NPN bipolar transistor Q 4 .
  • the value of this constant current I 0 can be adjusted by a resistor R 1 connected between an emitter of the NPN bipolar transistor Q 4 and the low potential power supply line V EE .
  • a current mirror circuit includes an input transistor and an output transistor, which have their gates or bases connected to each other. One end of a main current path of the input transistor and one end of a main current path of the output transistor are connected in common to the same power supply line. The gate or base and the other end of the main current path of the input transistor are connected to each other.
  • FIG. 1 of Japanese Patent Laid-open Publication No. Hei 1-321706 current I 0 passing through an input PMOS transistor T 2 of the MOS transistor current mirror circuit 2 is transferred or copied to an output PMOS transistor T 1 of the MOS transistor current mirror circuit 2, which supplies a constant current T 1 to an input NPN bipolar transistor Q 1 of the bipolar transistor current mirror circuit 3.
  • the load resistor R 3 functions to compensate for a drain voltage of the output PMOS transistor T 1 .
  • the current I' 1 passing through the input NPN bipolar transistor Q 1 is transferred or copied to an output NPN bipolar transistor Q 2 , so that a constant current I' 2 is generated at a collector of the output NPN bipolar transistor Q 2 .
  • Another object of the present invention is to provide a constant current generation circuit of the current mirror type which can make an input current and an output current equal to each other regardless of variation of a power supply voltage.
  • a constant current generation circuit comprising:
  • a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through the constant current source between the first end and the second end;
  • a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of the first input transistor and one end of a main current path of the first output transistor being connected in common to a second voltage supply line, the other end of the main current path of the first input transistor being connected to the control electrode of the first input transistor and the second end of the constant current source so that the first constant current flows through the first input transistor;
  • a bipolar transistor having an emitter connected to the other end of the main current path of the first output transistor, a collector of the bipolar transistor supplying a constant output current, and a base of the bipolar transistor being biased with an appropriate voltage so that a voltage of the output terminal of the current mirror circuit is made substantially equal to the voltage of the input terminal of the current mirror circuit, thereby minimizing a current transmission error between the input terminal and the output terminal of the current mirror circuit.
  • FIG. 1 is a circuit diagram of a first embodiment of the constant current generation circuit in accordance with the present invention
  • FIG. 2 is a circuit diagram of a second embodiment of the constant current generation circuit in accordance with the present invention.
  • FIGS. 3A and 3B are circuit diagram of third and fourth embodiments of the constant current generation circuit in accordance with the present invention.
  • FIG. 1 there is shown a circuit diagram of a first embodiment of the constant current generation circuit in accordance with the present invention.
  • the shown embodiment generally comprises a constant current source 1, a first current mirror circuit 2, a second current mirror circuit 3 and a bias circuit 4, connected as shown.
  • the constant current source 1 includes a constant voltage generating circuit composed of three forward direction series-connected diodes D 1 , D 2 and D 3 and a resistor R 2 , which are connected in series between a ground and a power supply terminal 5 of a low potential V EE .
  • a cathode of the diode D 3 is connected to the power supply terminal 5 of the low potential V EE
  • the resistor R2 is connected at its one end of the ground and at its other end to an anode of the diode D 1 .
  • the constant current source 1 also includes an NPN transistor Q 4 having its base connected to a connection node between the resistor R 2 and the diode D 1 .
  • An emitter of the NPN transistor Q 4 is connected through a resistor R 1 to the power supply terminal 5 for V EE .
  • the first current mirror circuit 2 includes an input P-channel MOS transistor T 2 and an output P-channel MOS transistor T 1 , which have their gate interconnected to each other and their source connected in common to the ground.
  • a drain of the input transistor T 2 is connected to the gate of the input transistor T 2 itself. Namely, the input transistor T 2 is connected in the form of a diode.
  • the input transistor T 2 is also connected to a collector of the transistor Q 4 of the constant current source 1.
  • the second current mirror circuit 3 includes an input N-channel MOS transistor T 4 and an output N-channel MOS transistor T 5 , which have their gate interconnected to each other and their source connected in common to the power supply line 5 for the low potential V EE .
  • a drain of the input transistor T 4 is connected to the gate of the input transistor T 4 itself. Namely, the input transistor T 4 is connected in the form of a diode.
  • the input transistor T 4 is also connected through the bias circuit 4 to a drain of the output N-channel MOS transistor T 1 .
  • a drain of the input transistor T 5 is connected so as to supply a constant output current I 2 .
  • the bias circuit 4 includes an NPN transistor Q 5 having its base connected to the connection node between the resistor R 2 and the diode D 1 , similarly to the NPN transistor Q 4 , and an emitter of the NPN transistor Q 5 is connected through a resistor R 2 to the power supply terminal 5 for V EE .
  • the bias circuit 4 also includes a P-channel MOS transistor T 3 having its source connected to the ground and its drain connected to a gate of the P-channel MOS transistor T 3 itself so as to function as a diode, and a PNP transistor Q 6 having its emitter connected to the drain of the P-channel MOS transistor T 3 and its collector connected to a base of the PNP transistor Q 6 itself so as to function as a diode.
  • the collector of the PNP transistor Q 6 is connected to a collector of the NPN transistor Q 5 , and also to a base of another PNP transistor Q 7 which has its emitter connected to the drain of the P-channel MOS transistor T 1 and its collector connected to the drain of the N-channel MOS transistor T 4 .
  • a bias voltage defined by the three series-connected diodes D 1 , D 2 and D 3 is applied to the base of the NPN transistors Q 4 and Q 5 , so that these NPN transistors are biased in a forward direction, and a constant current I 0 flows through each of these NPN transistors.
  • This constant current I 0 is determined or adjusted by the emitter bias resistors R 1 and R 4 .
  • a drain voltage V 2 of the PMOS transistor T 2 connected in the form of diode is set to a value near to a threshold voltage of the PMOS transistor T 2 .
  • the gate of the PMOS transistor T 1 is applied with the gate voltage of the PMOS transistor T 2 .
  • a drain voltage V 1 of the PMOS transistor T 1 is set by an emitter voltage of the PNP transistor Q 7 .
  • a base voltage of the PNP transistor Q 7 is set to V 2 +V BE , where V BE is a base-emitter voltage of the PNP transistor Q 7 .
  • the P-channel MOS transistor T 3 has the same characteristics as that of the P-channel MOS transistor T 2 and the PNP transistor Q 6 has the same characteristics as that of the PNP transistor Q 7
  • the P-channel MOS transistor T 3 connected in the form of a diode gives a voltage drop equal to the drain voltage V 2 voltage V BE of the PNP transistor Q 7 .
  • the bias voltage V 2 +V BE is applied to the base of the PNP transistor Q 7 by cooperation of the P-channel MOS transistor T 3 and the PNP transistor Q 6 .
  • the drain voltage V 1 of the PMOS transistor T 1 becomes equal to the drain voltage V 2 of the PMOS transistor T 2 , and therefore, a current I 1 flowing through the PMOS transistor T 1 becomes equal to the current I 0 flowing through the PMOS transistor T 2 .
  • a current transmission error ⁇ (I 1 -I 0 )/I 0 ⁇ 100% was not greater than 2%.
  • FIG. 2 there is shown a circuit diagram of a second embodiment of the constant current generation circuit in accordance with the present invention.
  • elements similar or corresponding to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted.
  • the second embodiment is different from the first embodiment only in that the current mirror circuit 3 is composed of only bipolar transistors, in place of the MOS transistors T 4 and T 5 .
  • the second current mirror circuit 3 includes an input NPN transistor Q 1 and an output NPN transistor Q 2 , which have their base interconnected to each other and their emitter connected in common to the power supply line 5 for the low potential V EE .
  • a collector of the input NPN transistor Q 1 is connected to the collector of the PNP transistor Q 7 and a base of another NPN transistor Q 3 , which has its collector connected to the ground and its emitter connected to the base of the input NPN transistor Q 1 .
  • a collector of the output NPN transistor Q 2 is connected so as to supply a constant output current I 2 .
  • FIG. 3A there is shown a circuit diagram of a third embodiment of the constant current generation circuit in accordance with the present invention.
  • the third embodiment is a modification of the first embodiment, and therefore, in FIG. 3, elements similar or corresponding to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted.
  • the details of the constant current source 1 and the current mirror circuit 3 are omitted.
  • This third embodiment is different from the first embodiment in that the bias circuit 4 is modified so as to supply a fixed bias voltage to the base of the PNP transistor Q 7 . Namely, by making a base bias voltage V B of the PNP transistor Q 7 equal to ⁇ V 2 +V BE ⁇ , an advantage similar to the first embodiment can be obtained.
  • FIG. 3B there is shown a circuit diagram of a fourth embodiment of the constant current generation circuit in accordance with the present invention.
  • the fourth embodiment is a modification of the third embodiment, and therefore, in FIG. 4, elements similar or corresponding to those shown in FIG. 3 are given the same Reference Numerals, and explanation thereof will be omitted.
  • This fourth embodiment is different from the third embodiment in that the first current mirror circuit 2 includes an input PNP transistor Q 8 and an output PNP transistor Q 9 , which have their base interconnected to each other and their emitter connected in common to the ground.
  • a collector of the input PNP transistor Q 8 is connected to a base of the PNP transistor Q 8 itself and to the constant current source 1.
  • a collector of the output PNP transistor Q 9 is connected to the emitter of the PNP transistor Q 7 .
  • the output constant current I 2 is supplied by the second current mirror circuit 3.
  • the output current I 1 of the first current mirror circuit 2 is similarly a constant current, and therefore, it is a matter of course that the second current mirror circuit 3 can be omitted, and the output current I 1 of the first current mirror circuit 2 can be used as the constant output current of the constant current generation circuit in accordance with the present invention.
  • the constant current generation circuit in accordance with the present invention is characterized in that the output of the current mirror circuit is drawn through the bipolar transistor, so that the drain voltages of a pair of MOS transistors of the current mirror circuit can be made equal to each other regardless of variation in the power supply voltage, and therefore, the input current and the output current can be also made equal to each other.

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Abstract

A constant current generation circuit includes a current mirror circuit having an input PMOS transistor connected in the form of a diode connected in series to a constant current source. With a constant current I0 of the constant current source, a drain voltage V2 of the input PMOS transistor is set to a value near to the threshold voltage of the input PMOS transistor. A gate of the input PMOS transistor is connected to a gate of output PMOS transistor having its drain connected to an emitter of a PNP transistor, which has its base biased with an appropriate voltage. With this arrangement, a drain voltage V1 of the output PMOS transistor can be made equal to the drain voltage V2 of the input PMOS transistor, and therefore, the input current I0 flowing through the input PMOS transistor can be made equal to an output current I1 flowing through the output PMOS transistor.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a constant current generation circuit, and more specifically to a constant current generation circuit composed of a current mirror circuit.
2. Description of Relates Art
A typical example of the constant current generation circuit of this type is disclosed in Japanese Patent Laid-open Publication No. Hei 1-321706. For example, the constant current generation circuit shown in FIG. 1 of this Japanese patent laid-open publication includes a constant current source 1 connected in series to an input current path of a MOS transistor current mirror circuit 2, and a bipolar transistor current mirror circuit 3 having an input current path connected in series through a load resistor R3 to an output current path of the MOS transistor current mirror circuit 2, an output current path of the bipolar transistor current mirror circuit 3 constituting an output of the constant current generation circuit.
The constant current source 1 includes a resistor R2 and three series-connected diodes D1, D2 and D3, which are connected in series between a ground and a low potential power supply line VEE. A constant voltage obtained across the three series-connected diodes D1, D2 and D3 is applied to a base of an NPN bipolar transistor Q4, so that a constant current I0 passes through the NPN bipolar transistor Q4. The value of this constant current I0 can be adjusted by a resistor R1 connected between an emitter of the NPN bipolar transistor Q4 and the low potential power supply line VEE.
In general, a current mirror circuit includes an input transistor and an output transistor, which have their gates or bases connected to each other. One end of a main current path of the input transistor and one end of a main current path of the output transistor are connected in common to the same power supply line. The gate or base and the other end of the main current path of the input transistor are connected to each other. With this arrangement, if a predetermined current is caused to pass through the input transistor, the output transistor is controlled to pass the predetermined current therethrough.
In FIG. 1 of Japanese Patent Laid-open Publication No. Hei 1-321706, current I0 passing through an input PMOS transistor T2 of the MOS transistor current mirror circuit 2 is transferred or copied to an output PMOS transistor T1 of the MOS transistor current mirror circuit 2, which supplies a constant current T1 to an input NPN bipolar transistor Q1 of the bipolar transistor current mirror circuit 3. In this case, the load resistor R3 functions to compensate for a drain voltage of the output PMOS transistor T1. In the bipolar transistor current mirror circuit 3, the current I'1 passing through the input NPN bipolar transistor Q1 is transferred or copied to an output NPN bipolar transistor Q2, so that a constant current I'2 is generated at a collector of the output NPN bipolar transistor Q2.
In the above mentioned constant current generation circuit, in the case that the two PMOS transistors T1 and T2 of the current mirror circuit 2 have an inclined current-voltage characteristics in a saturated region, if a drain voltage of the PMOS transistor T2 becomes different from a drain voltage of the PMOS transistor T1, the currents flowing through the respective PMOS transistors T1 and T2 becomes unequal.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a constant current generation circuit which has overcomes the above mentioned defect of the conventional one.
Another object of the present invention is to provide a constant current generation circuit of the current mirror type which can make an input current and an output current equal to each other regardless of variation of a power supply voltage.
The above and other objects of the present invention are achieved in accordance with the present invention by a constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through the constant current source between the first end and the second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of the first input transistor and one end of a main current path of the first output transistor being connected in common to a second voltage supply line, the other end of the main current path of the first input transistor being connected to the control electrode of the first input transistor and the second end of the constant current source so that the first constant current flows through the first input transistor;
a bipolar transistor having an emitter connected to the other end of the main current path of the first output transistor, a collector of the bipolar transistor supplying a constant output current, and a base of the bipolar transistor being biased with an appropriate voltage so that a voltage of the output terminal of the current mirror circuit is made substantially equal to the voltage of the input terminal of the current mirror circuit, thereby minimizing a current transmission error between the input terminal and the output terminal of the current mirror circuit.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a first embodiment of the constant current generation circuit in accordance with the present invention;
FIG. 2 is a circuit diagram of a second embodiment of the constant current generation circuit in accordance with the present invention; and
FIGS. 3A and 3B are circuit diagram of third and fourth embodiments of the constant current generation circuit in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, there is shown a circuit diagram of a first embodiment of the constant current generation circuit in accordance with the present invention.
The shown embodiment generally comprises a constant current source 1, a first current mirror circuit 2, a second current mirror circuit 3 and a bias circuit 4, connected as shown. The constant current source 1 includes a constant voltage generating circuit composed of three forward direction series-connected diodes D1, D2 and D3 and a resistor R2, which are connected in series between a ground and a power supply terminal 5 of a low potential VEE. A cathode of the diode D3 is connected to the power supply terminal 5 of the low potential VEE, and the resistor R2 is connected at its one end of the ground and at its other end to an anode of the diode D1. The constant current source 1 also includes an NPN transistor Q4 having its base connected to a connection node between the resistor R2 and the diode D1. An emitter of the NPN transistor Q4 is connected through a resistor R1 to the power supply terminal 5 for VEE.
The first current mirror circuit 2 includes an input P-channel MOS transistor T2 and an output P-channel MOS transistor T1, which have their gate interconnected to each other and their source connected in common to the ground. A drain of the input transistor T2 is connected to the gate of the input transistor T2 itself. Namely, the input transistor T2 is connected in the form of a diode. The input transistor T2 is also connected to a collector of the transistor Q4 of the constant current source 1.
The second current mirror circuit 3 includes an input N-channel MOS transistor T4 and an output N-channel MOS transistor T5, which have their gate interconnected to each other and their source connected in common to the power supply line 5 for the low potential VEE. A drain of the input transistor T4 is connected to the gate of the input transistor T4 itself. Namely, the input transistor T4 is connected in the form of a diode. The input transistor T4 is also connected through the bias circuit 4 to a drain of the output N-channel MOS transistor T1. On the other hand, a drain of the input transistor T5 is connected so as to supply a constant output current I2.
The bias circuit 4 includes an NPN transistor Q5 having its base connected to the connection node between the resistor R2 and the diode D1, similarly to the NPN transistor Q4, and an emitter of the NPN transistor Q5 is connected through a resistor R2 to the power supply terminal 5 for VEE. The bias circuit 4 also includes a P-channel MOS transistor T3 having its source connected to the ground and its drain connected to a gate of the P-channel MOS transistor T3 itself so as to function as a diode, and a PNP transistor Q6 having its emitter connected to the drain of the P-channel MOS transistor T3 and its collector connected to a base of the PNP transistor Q6 itself so as to function as a diode. In addition, the collector of the PNP transistor Q6 is connected to a collector of the NPN transistor Q5, and also to a base of another PNP transistor Q7 which has its emitter connected to the drain of the P-channel MOS transistor T1 and its collector connected to the drain of the N-channel MOS transistor T4.
Now, operation of the first embodiment will be described. A bias voltage defined by the three series-connected diodes D1, D2 and D3 is applied to the base of the NPN transistors Q4 and Q5, so that these NPN transistors are biased in a forward direction, and a constant current I0 flows through each of these NPN transistors. This constant current I0 is determined or adjusted by the emitter bias resistors R1 and R4. With this constant current I0, a drain voltage V2 of the PMOS transistor T2 connected in the form of diode is set to a value near to a threshold voltage of the PMOS transistor T2.
The gate of the PMOS transistor T1 is applied with the gate voltage of the PMOS transistor T2. A drain voltage V1 of the PMOS transistor T1 is set by an emitter voltage of the PNP transistor Q7. At this time, a base voltage of the PNP transistor Q7 is set to V2 +VBE, where VBE is a base-emitter voltage of the PNP transistor Q7. If the P-channel MOS transistor T3 has the same characteristics as that of the P-channel MOS transistor T2 and the PNP transistor Q6 has the same characteristics as that of the PNP transistor Q7, the P-channel MOS transistor T3 connected in the form of a diode gives a voltage drop equal to the drain voltage V2 voltage VBE of the PNP transistor Q7. Thus, the bias voltage V2 +VBE, is applied to the base of the PNP transistor Q7 by cooperation of the P-channel MOS transistor T3 and the PNP transistor Q6.
With this arrangement, the drain voltage V1 of the PMOS transistor T1 becomes equal to the drain voltage V2 of the PMOS transistor T2, and therefore, a current I1 flowing through the PMOS transistor T1 becomes equal to the current I0 flowing through the PMOS transistor T2. In this embodiment, for example, even if the power supply voltage VEE (=-4.5 V) varies in the range of ±10%, a current transmission error {(I1 -I0)/I0 }×100% was not greater than 2%.
Referring to FIG. 2, there is shown a circuit diagram of a second embodiment of the constant current generation circuit in accordance with the present invention. In FIG. 2, elements similar or corresponding to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted. The second embodiment is different from the first embodiment only in that the current mirror circuit 3 is composed of only bipolar transistors, in place of the MOS transistors T4 and T5.
Namely, the second current mirror circuit 3 includes an input NPN transistor Q1 and an output NPN transistor Q2, which have their base interconnected to each other and their emitter connected in common to the power supply line 5 for the low potential VEE. A collector of the input NPN transistor Q1 is connected to the collector of the PNP transistor Q7 and a base of another NPN transistor Q3, which has its collector connected to the ground and its emitter connected to the base of the input NPN transistor Q1. On the other hand, a collector of the output NPN transistor Q2 is connected so as to supply a constant output current I2. In this second embodiment, an advantage similar to the first embodiment can be obtained, since the drain voltage V1 of the PMOS transistor T1 becomes equal to the drain voltage V2 of the PMOS transistor T2.
Referring to FIG. 3A, there is shown a circuit diagram of a third embodiment of the constant current generation circuit in accordance with the present invention. The third embodiment is a modification of the first embodiment, and therefore, in FIG. 3, elements similar or corresponding to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted. In addition, the details of the constant current source 1 and the current mirror circuit 3 are omitted.
This third embodiment is different from the first embodiment in that the bias circuit 4 is modified so as to supply a fixed bias voltage to the base of the PNP transistor Q7. Namely, by making a base bias voltage VB of the PNP transistor Q7 equal to {V2 +VBE }, an advantage similar to the first embodiment can be obtained.
Referring to FIG. 3B, there is shown a circuit diagram of a fourth embodiment of the constant current generation circuit in accordance with the present invention. The fourth embodiment is a modification of the third embodiment, and therefore, in FIG. 4, elements similar or corresponding to those shown in FIG. 3 are given the same Reference Numerals, and explanation thereof will be omitted.
This fourth embodiment is different from the third embodiment in that the first current mirror circuit 2 includes an input PNP transistor Q8 and an output PNP transistor Q9, which have their base interconnected to each other and their emitter connected in common to the ground. A collector of the input PNP transistor Q8 is connected to a base of the PNP transistor Q8 itself and to the constant current source 1. On the other hand, a collector of the output PNP transistor Q9 is connected to the emitter of the PNP transistor Q7. In third fourth embodiment, an advantage similar to the third embodiment can be obtained.
In the above mentioned embodiments, the output constant current I2 is supplied by the second current mirror circuit 3. However, the output current I1 of the first current mirror circuit 2 is similarly a constant current, and therefore, it is a matter of course that the second current mirror circuit 3 can be omitted, and the output current I1 of the first current mirror circuit 2 can be used as the constant output current of the constant current generation circuit in accordance with the present invention.
It would be understood to average persons in the art that the above mentioned embodiments can be modified by changing the P-channel MOS transistors, the N-channel transistors, the NPN transistors and the PNP transistors to N-channel MOS transistors, P-channel transistors, PNP transistors and NPN transistors, respectively and by inverting the potential relation between the ground and the power supply terminal 5.
As will be apparent from the above description of the embodiments with reference to the drawings, the constant current generation circuit in accordance with the present invention is characterized in that the output of the current mirror circuit is drawn through the bipolar transistor, so that the drain voltages of a pair of MOS transistors of the current mirror circuit can be made equal to each other regardless of variation in the power supply voltage, and therefore, the input current and the output current can be also made equal to each other.
The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims (14)

I claim:
1. A constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through said constant current source between said first end and said second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of said first input transistor and one end of a main current path of said first output transistor being connected in common to a second voltage supply line, the other end of said main current path of said first input transistor being connected to said control electrode of said first input transistor and said second end of said constant current source so that said first constant current flows through said first input transistor;
a PNP transistor having an emitter connected to the other end of said main current path of said first output transistor, a base of said PNP transistor being biased with an appropriate voltage, and a collector of said PNP transistor supplying a constant output current;
wherein said constant current source includes a first constant current transistor having its control electrode biased with a fixed bias voltage, one end of a main current path of said first constant current transistor being connected to the other end of said main current path of said first input transistor, and the other end of said main current path of said first constant current transistor being connected through a first resistor to said first voltage supply line, and further including a bias circuit which comprises:
a second constant current transistor having its control electrode biased with said fixed bias voltage, one end of a main current path of said second constant current transistor being connected to said base of said PNP transistor, and the other end of said main current path of said second constant current transistor being connected through a second resistor to said first voltage supply line, and
an active load having its one end connected to said base of said PNP transistor and its other end connected to said second voltage supply line, said active load giving a voltage drop which substantially equals to a volume drop across said main current path of said first input transistor plus a base-emitter voltage of said PNP transistor.
2. A constant current generation circuit claimed in claim 1 wherein said active load includes a P-channel MOS transistor having its source connected to said second voltage supply line and its drain connected to a gate of said P-channel MOS transistor itself, and a PNP transistor having its emitter connected to said drain of said P-channel MOS transistor and its base and its collector connected in common to said base of said PNP transistor.
3. A constant current generation circuit claimed in claim 1 wherein said first current mirror circuit includes an input P-channel MOS transistor and an output P-channel MOS transistor which have their gate interconnected to each other and their source connected in common to said second voltage supply line, a drain of said input P-channel MOS transistor being connected to said gate of said input P-channel MOS transistor itself and also connected to said one end of said main current path of said first constant current transistor, and a drain of said output P-channel MOS transistor being connected to said collector of said PNP transistor.
4. A constant current generation circuit claimed in claim 1 wherein said first current mirror circuit includes an input PNP transistor and an output PNP transistor which have their base interconnected to each other and their emitter connected in common to said second voltage supply line, a collector of said input PNP transistor being connected to a base of said input PNP transistor itself and also connected to said one end of said main current path of said first constant current transistor, and an emitter of the output PNP transistor being connected to said collector of said PNP transistor.
5. A constant current generation circuit claimed in claim 1 further including a second current mirror circuit composed of a second input transistor and a second output transistor having their control electrode interconnected to each other, one end of a main current path of said second input transistor and one end of a main current path of said second output transistor being connected in common to said first voltage supply line, the other end of said main current path of said second input transistor being connected to said control electrode of said second input transistor band said collector of said PNP transistor, and the other end of said main current path of said second output transistor supplying a constant output current.
6. A constant current generation circuit claimed in claim 5 wherein said second current mirror circuit includes an input N-channel MOS transistor and an output N-channel MOS transistor which have their gate interconnected to each other and their source connected in common to the first voltage supply line, a drain of the input N-channel MOS transistor being connected to said gate of the input N-channel MOS transistor itself and also connected to said collector of said PNP transistor, and a drain of said output N-channel MOS transistor supplying a constant output current.
7. A constant current generation circuit claimed in claim 5 wherein said second current mirror circuit includes an input NPN transistor and an output NPN transistor which have their base interconnected to each other and their emitter connected in common to the first power supply line, a collector of said input NPN transistor being connected to said collector of said PNP transistor and a base of a third NPN transistor, which has its collector connected to said second voltage supply line and its emitter connected to said base of said input NPN transistor, and a collector of said output NPN transistor supplying a constant output current.
8. A constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through said constant current source between said first end and said second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of said first input transistor and one end of a main current path of said first output transistor being connected in common to a second voltage supply line, the other end of said main current path of said first input transistor being connected to said control electrode of said first input transistor and said second end of said constant current source so that said first constant current flows through said first input transistor;
a bipolar transistor having an emitter connected to the other end of said main current path of said first output transistor, a base of said bipolar transistor being biased with an appropriate voltage, and a collector of said bipolar transistor supplying a constant output current;
wherein said constant current source includes a first constant current transistor having its control electrode biased with a fixed bias voltage, one end of a main current path of said first constant current transistor being connected to the other end of said main current path of said first input transistor, and the other end of said main current path of said first constant current transistor being connected through a first resistor to said first voltage supply line, and further including a bias circuit which comprises:
a second constant current transistor having its control electrode biased with said fixed bias voltage, one end of a main current path of said second constant current transistor being connected to said base of said bipolar transistor, and the other end of said main current path of said second constant current transistor being connected through a second resistor to said first voltage supply line, and
an active load having its one end connected to said base of said bipolar transistor and its other end connected to said second voltage supply line, said active load giving a voltage drop which substantially equals to a voltage drop across said main current path of said first input transistor plus a base-emitter voltage of said bipolar transistor.
9. A constant current generation circuit claimed in claim 8 wherein said base of said bipolar transistor is biased with a fixed voltage substantially equal to a voltage drop across said main current path of said first input transistor plus a base-emitter voltage of said bipolar transistor.
10. A constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through said constant current source between said first end and said second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of said first input transistor and one end of a main current path of said first output transistor being connected in common to a second voltage supply line, the other end of said main current path of said first input transistor being connected to said control electrode of said first input transistor and said second end of said constant current source so that said first constant current flows through said first input transistor;
a PNP transistor having an emitter connected to the other end of said main current path of said first output transistor, a base of said PNP transistor being biased with an appropriate voltage, and a collector of said PNP transistor supplying a constant output current;
wherein said base of said PNP transistor is biased with a fixed voltage substantially equal to a voltage drop across said main current path of said first input transistor plus a base-emitter voltage of said PNP transistor; and
wherein said first current mirror circuit includes an input P-channel MOS transistor and an output P-channel MOS transistor which have their gate interconnected to each other and their source connected in common to said second voltage supply line, a drain of said input P-channel MOS transistor being connected to said gate of said input P-channel MOS transistor itself and also connected to said second end of said constant current source, and a drain of said output P-channel MOS transistor being connected to said collector of said PNP transistor.
11. A constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through said constant current source between said first end and said second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of said first input transistor and one end of a main current path of said first output transistor being connected in common to a second voltage supply line, the other end of said main current path of said first input transistor being connected to said control electrode of said first input transistor and said second end of said constant current source so that said first constant current flows through said first input transistor;
a PNP transistor having an emitter connected to the other end of said main current path of said first output transistor, a base of said PNP transistor being biased with an appropriate voltage, and a collector of said PNP transistor supplying a constant output current;
wherein said base of said PNP transistor is biased with a fixed voltage substantially equal to a voltage drop across said main current path of said first input transistor plus a base-emitter voltage of said PNP transistor; and
wherein said first current mirror circuit includes an input PNP transistor and an output PNP transistor which have their base interconnected to each other and their emitter connected in common to said second voltage supply line, a collector of said input PNP transistor being connected to a base of said input PNP transistor itself and also connected to said second end of said constant current source, and an emitter of the output PNP transistor being connected to said collector of said PNP transistor.
12. A constant current generation circuit comprising:
a constant current source having a first end connected to a first voltage supply line, and a second end, and so configured to allow a first constant current to flow through said constant current source between said first end and said second end;
a first current mirror circuit composed of a first input transistor and a first output transistors having their control electrode interconnected to each other, one end of a main current path of said first input transistor and one end of a main current path of said first output transistor being connected in common to a second voltage supply line, the other end of said main current path of said first input transistor being connected to said control electrode of said first input transistor and said second end of said constant current source so that said first constant current flows through said first input transistor;
a PNP transistor having an emitter connected to the other end of said main current path of said first output transistor, a base of said PNP transistor being biased with an appropriate voltage, and a collector of said PNP transistor supplying a constant output current;
wherein said base of said PNP transistor is biased with a fixed voltage substantially equal to a voltage drop across said main current path of said first input transistor plus a base-emitter voltage of said PNP transistor; and
further including a second current mirror circuit composed of a second input transistor and a second output transistor having their control electrode interconnected to each other, one end of a main current path of said second input transistor and one end of a main current path of said second output transistor being connected in common to said first voltage supply line, the other end of said main current path of said second input transistor being connected to said control electrode of said second input transistor and said collector of said PNP transistor, and the other end of said main current path of said second output transistor supplying a constant output current.
13. A constant current generation circuit claimed in claim 12 wherein said second current mirror circuit includes an input N-channel MOS transistor and an output N-channel MOS transistor which have their gate interconnected to each other and their source connected in common to the first voltage supply line, a drain of the input N-channel MOS transistor being connected to said gate of the input N-channel MOS transistor itself and also connected to said collector of said PNP transistor, and a drain of said output N-channel MOS transistor supplying a constant output current.
14. A constant current generation circuit claimed in claim 12 wherein said second current mirror circuit includes an input NPN transistor and an output NPN transistor which have their base interconnected to each other and their emitter connected in common to the first power supply line, a collector of said input NPN transistor being connected to said collector of said PNP transistor and a base of a third NPN transistor, which has its collector connected to said second voltage supply line and its emitter connected to said base of said input NPN transistor, and a collector of said output NPN transistor supplying a constant output current.
US08/021,750 1992-02-19 1993-02-19 Constant current generation circuit of current mirror type having equal input and output currents Expired - Fee Related US5349307A (en)

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