US4728754A - Inter-bus system - Google Patents

Inter-bus system Download PDF

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Publication number
US4728754A
US4728754A US06/902,246 US90224686A US4728754A US 4728754 A US4728754 A US 4728754A US 90224686 A US90224686 A US 90224686A US 4728754 A US4728754 A US 4728754A
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Prior art keywords
bus
inter
grant
converter
active
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US06/902,246
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Glenville C. E. Fowler
David J. Tozer
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Sprint International Communications Corp
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Plessey Overseas Ltd
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Assigned to PLESSEY OVERSEAS LIMITED reassignment PLESSEY OVERSEAS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FOWLER, GLENVILLE C. E., TOZER, DAVID J.
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Publication of US4728754A publication Critical patent/US4728754A/en
Assigned to TELENET COMMUNICATIONS CORPORATION, A DE. CORP. reassignment TELENET COMMUNICATIONS CORPORATION, A DE. CORP. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: PLESSEY OVERSEAS LIMITED
Assigned to SPRINT INTERNATIONAL COMMUNICATIONS CORPORATION, A CORP. OF DE reassignment SPRINT INTERNATIONAL COMMUNICATIONS CORPORATION, A CORP. OF DE CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). EFFECTIVE DATE: JAN. 2, 1990 - DE Assignors: TELENET COMMUNICATIONS CORPORATION
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing

Definitions

  • the present invention relates to a inter-bus system providing a high speed communication interface between a number of communication systems.
  • the inter-bus system may be used as a high bandwidth communication link between a series of packet switching exchanges.
  • LAN local area network
  • the problem with a LAN is that it is a serial bus controlled by a complex protocol. This results in a bandwidth below 1M bytes/sec.
  • An aim of the present invention is to provide an inter-bus system capable of working at a bandwidth of 10M bytes/sec.
  • a further aim of the present invention is to provide a multi-drop inter-bus system capable of tranferring data over a distance up to 15 metres with the same bandwidth as normal microprocessor buses.
  • An advantage of the present invention is that it is cheaper than most high speed long distance buses.
  • a further advantage of the present invention is that a simple protocol is used, maintaining maximum bus throughput.
  • an inter-bus system for interconnecting a plurality of communication systems by way of an interfacing means, each communication system is provided with a bus converter for interfacing the inter-bus system with the bus of each communication system, the inter-bus system includes a grant return path, and the bus converters are chained by a grant link arrangement, used to carry a grant pulse which is passed on around the chained bus converters to identify the master converter for an inter-bus system transfer; wherein, when the grant pulse is received by a bus converter wanting to transmit, that bus converter breaks the chain and performs the transmission required, when the transmission is complete the completing bus converter surrenders its master state by generating the grant pulse.
  • FIG. 1 shows a block diagram of an inter-bus system
  • FIG. 2 shows a frame format
  • the inter-bus system is a 16 bit parallel bus with parity protection which operates over long distances using a multi-drop RS-485 standard interface.
  • the bus operates at 5 MHz.
  • the bus can operate over distances of up to 15 meters using transceivers supporting a multi-drop interface in which up to thirty two communication system cabinets CAB1-CAB32 can be placed.
  • the inter-connection is a twisted pair ribbon cable which uses standard push fit connectors.
  • the bus has a maximum operating speed of 10M bytes/sec when used in burst transfer mode and is parity protected.
  • the 16 data lines are used for the address as well as the data.
  • the bus uses a daisy chain arbitration acheme which is simple and cost effective.
  • the grant signal This is passed from one card to another and is not part of the twisted ribbon cable. This is simply a twisted pair wire which plugs into the cards via a separate connector.
  • Each cabinet has a bus converter which converts from the cabinet bus, a multi-master system bus for example, to the inter-bus system.
  • One of these converters is always set up as the master card.
  • the master card generates the clock signal (e.g. 5 MHz) and starts and ends each arbitration cycle.
  • a cabinet can only transmit on the inter-bus system if it has control of the bus, otherwise it is in receive mode.
  • the frame format will now be desribed.
  • Data sent on the bus has to be transmitted in a frame.
  • the ADDRESS FIELD is the first word to be transmitted. All of the bus converters have an address trap circuit which will trigger should the address being transmitted correspond to its system.
  • the BYTE COUNT is the second word to be sent and is an inclination of the number of words being sent after it. This also includes the CRC if used.
  • the DATA FIELD contains the data being transferred. The amount of data that can be transferred is limited by the byte count. In the packet switching system this would vary from 1 to 4096 bytes.
  • the CRC FIELD Cyclic Redundancy Check
  • This is generated by the transmitting system.
  • the cycle begins with the master system using the bus if it requires it. If it does not, it transmits a grant pulse from its grant out pin which is connected to the grant in pin on the next card. This grant pulse is sent to the next card and so on until a system wants to transmit data to another system on the bus. If this is the case, the grant pulse is held back from going to the next system.
  • the TRANS ACTIVE line is driven by the transmitter for the whole length of the transmission.
  • the address word is sent first and is qualified by the ADDRESS STROBE line. This signal lasts the length of the clock cycle in which the address is being transmitted (200 ns).
  • the data is then transmitted on the same line as the address.
  • a word is transmitted on each falling edge of the CLOCK SIGNAL.
  • the transmission is finished when the TRANS ACTIVE line goes inactive.
  • the grant signal is then passed on to the next card.
  • the transmission can also be terminated when the ABORT signal is driven by either the transmitter or the receiver.
  • the grant is not passed on until a clock cycle has elapsed from when the TRANS ACTIVE line goes inactive.
  • a receiving system monitors the TRANS ACTIVE line and if active checks to see if the ADDRESS STROBE is active. If both of these conditions are met, the first word, the address, is interrogated to see if the value corresponds to its own system. If there is no address match then the system will idle and wait for the next address strobe.
  • a receiving system does have a correct address it will continue to accept more data.
  • the next word is the byte count which the system uses to monitor the number of bytes sent. The system will continue to accept data until the byte count equals the number of bytes received. If the TRANS ACTIVE line is still active and data is still being sent then the receiver will drive the ABORT line. Also if the TRANS ACTIVE line is disabled before the correct number of bytes have been accepted that frame is also aborted. An abort signal is also generated by the receiver if the receiving parity is incorrect on any received byte.
  • the bus uses RS-485 transceivers. These components are readily available and are designed to work in multi-drop situations. Termination for the bus are via simple resistive loads. Up to thirty two transceivers can operate on the bus at one time, one transmit and thirty two in receive mode.
  • the RS-485 uses a balanced voltage technique. Further information is available from the EIA specification for RS-485 (EIA standards proposal No. 1488, Electrical Characteristics of Generators and Receivers for use in Balanced Digital Multipoint Systems).
  • the GRANT line is implemented using an RS-422 interface, since multi-drop is not required.
  • the systems are linked using fifty-way twisted pair ribbon cable.
  • the mechanical connections are accomplished using DIN 41612 push fit connectors.
  • the GRANT signal is transmitted via a separate twisted pair cable using a simple two-way connector.
  • the invention is not limited to fast communication links between large systems in the communication field. It could be used in the computer industry for connecting large mainframes to high speed peripherals for example.

Abstract

The inter-bus system provides the communication interconnection between communication systems to form a large telegraph packet switching exchange for example. The fast inter-bus system uses an RS-485 interface, however, the specific protocol used has particular speed advantages. The inter-bus system consists of a bus converter for each communication system interconnected by a bus involving 16 data bits, a pair of parity bits, clock, abort, transmit active, address strobe and grant return paths. The bus converters are chained by a grant link arrangement. The grant link is used to carry a grant pulse which is passed on around the chained bus converters to identify the master converter for an inter-bus system transfer. When the grant pulse is received by a bus converter wanting to transmit, that bus converter breaks the chain and performs the transmission required. When the transmission is complete the completing bus converter surrenders its master state by generating the grant pulse.

Description

FIELD OF THE INVENTION
The present invention relates to a inter-bus system providing a high speed communication interface between a number of communication systems.
The inter-bus system may be used as a high bandwidth communication link between a series of packet switching exchanges.
DESCRIPTION OF PRIOR ART
At present, a high bandwidth communication link is provided by a local area network (LAN), operating at 10 MHz. The problem with a LAN is that it is a serial bus controlled by a complex protocol. This results in a bandwidth below 1M bytes/sec.
STATEMENT OF THE OBJECTS OF INVENTION
An aim of the present invention is to provide an inter-bus system capable of working at a bandwidth of 10M bytes/sec.
A further aim of the present invention is to provide a multi-drop inter-bus system capable of tranferring data over a distance up to 15 metres with the same bandwidth as normal microprocessor buses.
An advantage of the present invention is that it is cheaper than most high speed long distance buses.
A further advantage of the present invention is that a simple protocol is used, maintaining maximum bus throughput.
According to the present invention, there is provided an inter-bus system for interconnecting a plurality of communication systems by way of an interfacing means, each communication system is provided with a bus converter for interfacing the inter-bus system with the bus of each communication system, the inter-bus system includes a grant return path, and the bus converters are chained by a grant link arrangement, used to carry a grant pulse which is passed on around the chained bus converters to identify the master converter for an inter-bus system transfer; wherein, when the grant pulse is received by a bus converter wanting to transmit, that bus converter breaks the chain and performs the transmission required, when the transmission is complete the completing bus converter surrenders its master state by generating the grant pulse.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the present invention will now be described with reference to the accompanying drawings wherein:
FIG. 1 shows a block diagram of an inter-bus system, and
FIG. 2 shows a frame format.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, the inter-bus system is a 16 bit parallel bus with parity protection which operates over long distances using a multi-drop RS-485 standard interface. The bus operates at 5 MHz.
The bus can operate over distances of up to 15 meters using transceivers supporting a multi-drop interface in which up to thirty two communication system cabinets CAB1-CAB32 can be placed. The inter-connection is a twisted pair ribbon cable which uses standard push fit connectors.
The bus has a maximum operating speed of 10M bytes/sec when used in burst transfer mode and is parity protected. The 16 data lines are used for the address as well as the data. The bus uses a daisy chain arbitration acheme which is simple and cost effective.
There are a total of twenty four signals which make up the bus, of which twenty three are on the ribbon cable as follows:
______________________________________                                    
SIGNAL    NO OF LINES    COMMENTS                                         
______________________________________                                    
Data 0 to 15                                                              
          16             These are the 16                                 
                         address or data lines.                           
Parity low                                                                
          1              Parity line for the                              
                         lower data byte.                                 
Parity high                                                               
          1              Parity line for the                              
                         upper data byte.                                 
Clock     1              Bus clock with 20%                               
                         duty cycle. Maximum                              
                         speed 5 MHz.                                     
Abort     1              This signal when                                 
                         active, aborts the                               
                         present bus cycle.                               
Trans Active                                                              
          1              This signal is active                            
                         during a transfer. It                            
                         is generated by the                              
                         transmitting card.                               
Address Strobe                                                            
          1              This signal is active                            
                         during the address                               
                         which is usually the                             
                         first word of a frame.                           
Grant Return                                                              
          1              This is the grant                                
                         return signal from the                           
                         the last card to the                             
                         master arbitration                               
                         card.                                            
______________________________________
There is also another signal called the grant signal. This is passed from one card to another and is not part of the twisted ribbon cable. This is simply a twisted pair wire which plugs into the cards via a separate connector.
Each cabinet has a bus converter which converts from the cabinet bus, a multi-master system bus for example, to the inter-bus system. One of these converters is always set up as the master card. The master card generates the clock signal (e.g. 5 MHz) and starts and ends each arbitration cycle. A cabinet can only transmit on the inter-bus system if it has control of the bus, otherwise it is in receive mode.
Referring to FIG. 2, the frame format will now be desribed. Data sent on the bus has to be transmitted in a frame. The ADDRESS FIELD is the first word to be transmitted. All of the bus converters have an address trap circuit which will trigger should the address being transmitted correspond to its system. The BYTE COUNT is the second word to be sent and is an inclination of the number of words being sent after it. This also includes the CRC if used. The DATA FIELD contains the data being transferred. The amount of data that can be transferred is limited by the byte count. In the packet switching system this would vary from 1 to 4096 bytes.
The CRC FIELD (Cyclic Redundancy Check) is added to provide an extra level of detection of data corruption. This is generated by the transmitting system.
The Transmitting System
The cycle begins with the master system using the bus if it requires it. If it does not, it transmits a grant pulse from its grant out pin which is connected to the grant in pin on the next card. This grant pulse is sent to the next card and so on until a system wants to transmit data to another system on the bus. If this is the case, the grant pulse is held back from going to the next system.
Once a system has been granted the bus it will begin its transmission cycle. The TRANS ACTIVE line is driven by the transmitter for the whole length of the transmission. The address word is sent first and is qualified by the ADDRESS STROBE line. This signal lasts the length of the clock cycle in which the address is being transmitted (200 ns). The data is then transmitted on the same line as the address. A word is transmitted on each falling edge of the CLOCK SIGNAL.
The transmission is finished when the TRANS ACTIVE line goes inactive. The grant signal is then passed on to the next card. The transmission can also be terminated when the ABORT signal is driven by either the transmitter or the receiver. The grant is not passed on until a clock cycle has elapsed from when the TRANS ACTIVE line goes inactive.
Receiving System
If a system has not been granted use of the inter-bus system then it is in the receiving mode. A receiving system monitors the TRANS ACTIVE line and if active checks to see if the ADDRESS STROBE is active. If both of these conditions are met, the first word, the address, is interrogated to see if the value corresponds to its own system. If there is no address match then the system will idle and wait for the next address strobe.
If a receiving system does have a correct address it will continue to accept more data. The next word is the byte count which the system uses to monitor the number of bytes sent. The system will continue to accept data until the byte count equals the number of bytes received. If the TRANS ACTIVE line is still active and data is still being sent then the receiver will drive the ABORT line. Also if the TRANS ACTIVE line is disabled before the correct number of bytes have been accepted that frame is also aborted. An abort signal is also generated by the receiver if the receiving parity is incorrect on any received byte.
Electrical Interface
The bus uses RS-485 transceivers. These components are readily available and are designed to work in multi-drop situations. Termination for the bus are via simple resistive loads. Up to thirty two transceivers can operate on the bus at one time, one transmit and thirty two in receive mode. The RS-485 uses a balanced voltage technique. Further information is available from the EIA specification for RS-485 (EIA standards proposal No. 1488, Electrical Characteristics of Generators and Receivers for use in Balanced Digital Multipoint Systems).
The GRANT line is implemented using an RS-422 interface, since multi-drop is not required.
Mechanical Interface
The systems are linked using fifty-way twisted pair ribbon cable. The mechanical connections are accomplished using DIN 41612 push fit connectors.
The GRANT signal is transmitted via a separate twisted pair cable using a simple two-way connector.
The invention is not limited to fast communication links between large systems in the communication field. It could be used in the computer industry for connecting large mainframes to high speed peripherals for example.

Claims (3)

We claim:
1. An inter-bus system for interconnecting a plurality of communication systems by way of an interfacing means, each communication system is provided with a bus converter for interfacing the inter-bus system with the bus of each communication system, the inter-bus system includes a grant return path, and the bus converters are chained by a grant link arrangement, used to carry a grant pulse which is passed on around the chained bus converters to identify the master converter for an inter-bus system transfer; wherein, when the grant pulse is received by a bus converter wanting to transmit, that bus converter breaks the chain and performs the transmission required, when the transmission is complete the completing bus converter surrenders its master state by generating the grant pulse, said plurality of communication systems are inter-connected by a first line which is made active by a transmitter in the system, the converter of which disignated as the master, and remains active throughout the duration of a transmission, after which it is made inactive by the transmitter to allow the grant pulse to be passed on, and, wherein a system in a receiving mode monitors the first line to detect if it is active, and if an active line is detected, a second line which interconnects said plurality of communication systems is monitored to detect if it is in an active state, and if detected, address data being transmitted by another system is interrogated to ascertain if it corresponds to the address of the system in receiving mode, wherein the system in receiving mode continues to receive data if the address corresponds, the data next received indicates the number of bytes being transmitted by the other system, and the system in the receiving mode continues to accept data until a byte count equals the number of bytes received, and if data continues to be sent after the byte count equals the number of bytes received, while the first line is active, an abort signal is generated by the system in receiving mode.
2. An inter-bus system as claimed in claim 1, wherein if the first line, in an active state, is disabled before the correct number of bytes has been received, an abort signal is generated by the system in receiving mode.
3. An inter-bus system as claimed in claim 2 wherein the system in transmitting mode sends a cyclic redundancy check code to provide data corruption detection.
US06/902,246 1985-09-03 1986-08-29 Inter-bus system Expired - Lifetime US4728754A (en)

Applications Claiming Priority (2)

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GB8521806A GB2180126B (en) 1985-09-03 1985-09-03 Inter-bus system
GB8521806 1985-09-03

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US4728754A true US4728754A (en) 1988-03-01

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US (1) US4728754A (en)
EP (1) EP0213804B1 (en)
JP (1) JPS6260050A (en)
AU (1) AU592108B2 (en)
DE (1) DE3688160T2 (en)
GB (1) GB2180126B (en)
IN (1) IN168592B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400360A (en) * 1993-03-23 1995-03-21 Limitorque Corporation Repeater for a digital control system
US5841992A (en) * 1996-03-25 1998-11-24 Snap-On Tools Company Network-to-serial device intelligent converter
US11347667B2 (en) * 2018-01-10 2022-05-31 Qualcomm Incorporated Bus controller and related methods

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Publication number Priority date Publication date Assignee Title
WO1992013395A1 (en) * 1991-01-28 1992-08-06 Motorola, Inc. Receiver controller method and apparatus
FI95757C (en) * 1992-10-09 1996-03-11 Nokia Mobile Phones Ltd Method and IC bus structure for serial data transmission

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US3597549A (en) * 1969-07-17 1971-08-03 Bell Telephone Labor Inc High speed data communication system
US4292623A (en) * 1979-06-29 1981-09-29 International Business Machines Corporation Port logic for a communication bus system
US4570257A (en) * 1984-02-14 1986-02-11 Rosemount Inc. Communication system with slot time error detection

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US3508206A (en) * 1967-05-01 1970-04-21 Control Data Corp Dimensioned interrupt
JPS5147499B2 (en) * 1971-12-29 1976-12-15
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US4433391A (en) * 1981-08-17 1984-02-21 Burroughs Corporation Buffered handshake bus with transmission and response counters for avoiding receiver overflow
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
US4641266A (en) * 1983-11-28 1987-02-03 At&T Bell Laboratories Access-arbitration scheme

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Publication number Priority date Publication date Assignee Title
US3597549A (en) * 1969-07-17 1971-08-03 Bell Telephone Labor Inc High speed data communication system
US3597549B1 (en) * 1969-07-17 1983-12-06
US4292623A (en) * 1979-06-29 1981-09-29 International Business Machines Corporation Port logic for a communication bus system
US4570257A (en) * 1984-02-14 1986-02-11 Rosemount Inc. Communication system with slot time error detection

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400360A (en) * 1993-03-23 1995-03-21 Limitorque Corporation Repeater for a digital control system
US5841992A (en) * 1996-03-25 1998-11-24 Snap-On Tools Company Network-to-serial device intelligent converter
US11347667B2 (en) * 2018-01-10 2022-05-31 Qualcomm Incorporated Bus controller and related methods

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Publication number Publication date
JPS6260050A (en) 1987-03-16
DE3688160D1 (en) 1993-05-06
AU592108B2 (en) 1990-01-04
EP0213804B1 (en) 1993-03-31
EP0213804A2 (en) 1987-03-11
IN168592B (en) 1991-05-04
AU6119786A (en) 1987-03-05
DE3688160T2 (en) 1993-09-02
GB2180126B (en) 1989-08-31
EP0213804A3 (en) 1989-03-15
GB8521806D0 (en) 1985-10-09
GB2180126A (en) 1987-03-18

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