US4633107A - CMOS power-up reset circuit for gate arrays and standard cells - Google Patents
CMOS power-up reset circuit for gate arrays and standard cells Download PDFInfo
- Publication number
- US4633107A US4633107A US06/673,386 US67338684A US4633107A US 4633107 A US4633107 A US 4633107A US 67338684 A US67338684 A US 67338684A US 4633107 A US4633107 A US 4633107A
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- voltage potential
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Definitions
- This invention relates to power-up reset circuits for logic circuits, and more particularly, to power-up reset circuits for use with power supplies of any given ramp rate.
- CMOS complementary metal-oxide-semiconductor
- CMOS complementary metal-oxide-semiconductor
- a reset signal is typically provided during power-up of the circuit to set these elements to a certain desired condition. Normally, it is desirable to have this reset occur automatically during power-up, that is, during the period of time when the voltage from the power supply is transitioning from zero volts to the nominal voltage used to power the circuit.
- CMOS Gate Array/Standard Cell implementations which are manufactured using basic CMOS processing techniques, the passive components cannot be integrated with the standard geometry devices and must be provided externally.
- Another object of the invention is to provide a power-up reset circuit whose functionality is independent of the typical range of process variations and temperature range applications.
- a power-up reset circuit of this invention generates a reset signal during a power-up cycle of a power supply having a source voltage potential and a source voltage reference.
- a first means senses the source voltage potential and generates the reset signal at an output when the source voltage potential rises above a threshold level.
- the power-up reset circuit further has means for coupling an input of the first sensing means to the source voltage potential to permit a voltage at the first sensing means' input to follow the source voltage potential during an initial rise of the source voltage potential.
- a second sensing means senses the source voltage potential and generates a time delayed signal at an output when the source voltage potential rises above a predetermined level.
- a terminating means has an input coupled to the output of the second sensing means and generates a termination signal at an output coupled to the input of the first sensing means to terminate the reset signal in response to the time delayed signal.
- a feedback switch has an input coupled to the output of the first sensing means and couples the terminating means to one of the source voltage potential and the source voltage reference in response to the reset signal and decouples the terminating means from the one of the source voltage potential and source voltage reference in response to the termination of the reset signal.
- FIG. 1 is a circuit schematic of the invention
- FIG. 2 is a schematic of P-Channel MOSFETs connected to form a capacitor
- FIG. 3 is a schematic of N-Channel MOSFETs connected to form a capacitor
- FIG. 4 is a timing diagram illustrating the operation of the invention with a power supply having a step-function ramp rate
- FIG. 5 is a timing diagram illustrating the operation of the invention with a power supply having a linear ramp rate.
- a power-up reset circuit 10 is shown connected to power supply 12 which has a source voltage potential terminal 14 and a source voltage reference terminal 16.
- power supply 12 provides a source voltage potential at source voltage potential terminal 14 and the source voltage reference terminal 16 is connected to ground.
- the source voltage potential provided at source voltage potential terminal 14 of power supply 12 will hereinafter be referred to as VDD.
- a source voltage potential sensing and delay circuit has P-Channel MOSFETS 18, 26, 28 and a capacitator 30.
- P-Channel MOSFET 18 has its source 20 connected to VDD and its gate 22 connected to its drain 24.
- a MOSFET connected in the manner just described is typically referred to as a diode-connected MOSFET.
- MOSFETs 26 and 28 are also P-Channel diode-connected MOSFETs.
- the source of MOSFET 26 is coupled to the drain of MOSFET 18 and the drain of MOSFET 26 is coupled to the source of MOSFET 28.
- the drain of MOSFET 28 is connected to one side of capacitor 30 and to an input 32 of a CMOS inverter 34.
- CMOS inverter 34 comprises a threshold detection and terminating circuit and consists of a P-Channel MOSFET 36 and an N-Channel MOSFET 38.
- the source of P-Channel MOSFET 36 provides a source voltage potential terminal 40 for inverter 34 which is coupled to VDD by a feedback switch, feedback MOSFET 68.
- the source of N-Channel MOSFET 38 provides a source voltage reference terminal 42 for inverter 34. Terminals 40, 42 comprise power supply terminals for threshold detection inverter 34.
- the gate of MOSFETs 36, 38 are connected together and form the input 32 of CMOS inverter 34.
- the drains for MOSFETs 36, 38 are also connected together and provide an output 44 of CMOS inverter 34.
- Output 44 of CMOS inverter 34 is coupled by a capacitor 46 to VDD. Output 44 is also connected to an input, illustratively input 48 of CMOS inverter 50, of a wave shaping circuit which includes CMOS inverters 50, 60, and 72.
- CMOS inverter 50 is formed from a P-Channel MOSFET 52 and an N-Channel MOSFET 54.
- the source of MOSFET 52 is connected to VDD and the source of MOSFET 54 is connected to ground.
- the gates of MOSFETs 52, 54 are connected together and form input 48 and the drains of MOSFETs 52, 54 are connected together to provide an output 56 for inverter 50.
- Inverter 60 is formed from a P-Channel MOSFET 62 which has its source connected to VDD and a N-Channel MOSFET 64 which has its source connected to ground.
- the gates of MOSFETs 62, 64 are connected together to form input 58 and the drains of MOSFETs 62, 64 are connected together to provide an output 66 for inverter 60.
- a reset signal R is generated at output 66 of inverter 60 as will be described in greater detail later.
- Output 56 of inverter 50 is also connected to an input of the feedback switch, the gate of feedback P-Channel MOSFET 68.
- the source of MOSFET 68 is connected to VDD and the drain of MOSFET 68 is connected to the source voltage potential terminal 40 of inverter 34.
- MOSFET 68 forms the feedback switch which is coupled in series with the power supply terminals 40, 42 of inverter 34 between the source voltage potential VDD and the source voltage reference, ground.
- Output 66 of inverter 60 is connected to an input 70 of a CMOS inverter 72.
- Inverter 72 is formed from a P-Channel MOSFET 74 which has its source connected to VDD and a N-Channel MOSFET 76 which has its source connected to ground.
- the gates of MOSFETs 74, 76 are connected together to form input 70 and the drains of MOSFETs 74, 76 are connected together to provide an output 80 for inverter 72.
- an inverse reset signal R of the reset signal R generated at output 66 of inverter 60 is generated at output 80 of inverter 72.
- MOSFET 54 In operation, when the power supply 12 is turned on, the voltage at input 48 of inverter 50 will be brought to VDD through capacitor 46 as VDD rises. Therefore, as soon as VDD is higher than the threshold voltage for MOSFET 54 (illustratively 0.7 volts), MOSFET 54 will be turned on thereby pulling output 56 of inverter 50 to ground. Since input 48, the gate of MOSFET 52, of inverter 50 will be at VDD, as will the source of P-Channel MOSFET 52, MOSFET 52 will be biased off.
- the low signal at output 56 which is connected to the gate of feedback P-Channel MOSFET 68, will cause feedback MOSFET 68 to turn on thereby connecting inverter 34 to VDD.
- Input 32 of inverter 34 will be low at this point thereby forcing output 44 of inverter 34 high to ensure that input 48 of inverter 50 remains at VDD until inverter 34 changes states.
- the low signal at output 56 will also cause inverter 60 to generate a high signal at output 66 which in turn causes a low signal to be generated at output 80 of inverter 72. Therefore, reset signal R will be high and its inverse R at output 80 will be low. It should be understood that output 44 of inverter 34 could also provide the reset signal although wave-shaping inverters 50, 60, and 72 will generate a reset pulse having a more optimum wave shape.
- VDD voltage at input 32 of inverter 34 will begin to rise. This will occur when VDD reaches approximately 3 VDC.
- inverter 34 When the voltage at input 32 reaches approximately 1.8 VDC, inverter 34 will change states wherein MOSFET 38 will be turned on and MOSFET 36 will be biased off. MOSFET 38 will pull output 44 of inverter 34 to ground as soon as it is turned on. This will cause capacitor 46 to begin to discharge and input 48 of inverter 50 to be pulled low. This in turn causes inverters 50, 60, and 72 to change states. Output 56 of inverter 50 will go high, output 66 of inverter 60 will go low terminating reset signal R, and output 80 of inverter 72 will go high terminating the inverse reset signal R. As soon as output 56 of inverter 50 goes high, feedback MOSFET 68 will be biased off thereby disconnecting inverter 34 from VDD.
- inverter 34 By disconnecting inverter 34 from VDD as soon as the reset signal R is terminated, the current which would normally flow from VDD through MOSFETs 36, 38 will be eliminated thereby ensuring minimal power dissipation. This eliminates the problem which occurs if the feedback switch is not utilized wherein MOSFET 36 of inverter 34 would not be fully turned off even though the voltage level at input 32 had reached a sufficiently high level to turn MOSFET 38 on, which pulls output 44 of inverter 34 low.
- MOSFET 36 would not be fully turned off until the voltage level at input 32 reaches VDD. Therefore, during the time period that capacitor 30 continues to charge towards VDD after the voltage level at input 32 has reached the threshold level to cause inverter 34 to switch, current will not be flowing from VDD to ground through inverter 34. It should be understood that MOSFETs 18, 26, 28 effectively form an equivalent resistance which coacts with capacitor 30 so that the time it takes for the voltage level at input 32 to reach its various levels is determined by the RC time constant of capacitor 30 and the equivalant resistance of MOSFETs 18, 26, 38.
- the reset circuit becomes functionally independent of the power supply's ramp rate as shown by the simulation results discussed later. Further, using three MOSFETs (18, 26, 28) makes the circuit insensitive to temperature variations over at least the MIL-SPEC range, -55° C. to +125° C.
- a capacitor formed from P-Channel MOSFETs is shown.
- the capacitor is formed from three P-Channel MOSFETs 82, 84, 86.
- the source of MOSFET 82 is left floating while the drain of MOSFET 82 is connected to the source of MOSFET 84.
- the drain of MOSFET 84 is connected to the source of MOSFET 86 while the drain of MOSFET 86 is left floating.
- the gates of MOSFETs 82, 84, 86 are connected together and form one side of the capacitor.
- the substrates of MOSFETs 82, 84, 86 are also connected together and form the other side of the capacitor.
- a capacitor formed from P-Channel MOSFETs could be utilized for capacitor 46 wherein the interconnected gates would be coupled to input 48 of inverter 50 and the interconnected substrates would be connected to VDD.
- a capacitor formed from N-Channel MOSFET's is shown.
- the capacitor is formed from three N-Channel MOSFETs 88, 90, 92.
- the drain of MOSFET 88 is left floating while the source of MOSFET 88 is connected to the drain of MOSFET 90.
- the source of MOSFET 90 is connected to the drain of MOSFET 92 while the source of MOSFET 92 is left floating.
- the gates of MOSFETs 88, 90, 92 are connected together to form one side of the capacitor while the substrates of MOSFET 88, 90, 92 are connected together to form the other side of the capacitor.
- the capactor formed from N-Channel MOSFETs could be utilized as capacitor 30 with the interconnected gates connected to input 32 of inverter 34 and the connected together substrates connected to ground.
- capacitors 30 and 46 are approximately 1 pF.
- FIG. 4 a timing diagram for the circuit of FIG. 1 having the values as just described for a power supply having a step-function ramp rate is shown.
- VDD jumps to 5 volts.
- Input 48 of inverter 50 will follow VDD to 5 volts virtually simultaneously. This will force output 56 low, output 66 high, and output 80 low, thereby generating a high reset signal R at output 66 and its inverse R at output 80.
- the gate to MOSFET 66 will also be brought low, thereby biasing MOSFET 68 on which connects VDD to inverter 34.
- the voltage level at input 32 of inverter 54 will have risen to approximately 1.8 volts at which time it forces inverter 34 to change states.
- Output 44 is brought low forcing output 56 high, output 66 low, and output 80 high, thereby terminating the reset signal R.
- the gate of MOSFET 68 will also be brought high biasing MOSFET 68 off, thereby disconnecting inverter 34 from VDD.
- the voltage at input 32 will continue to rise to VDD.
- FIG. 5 a timing diagram for a power supply having a linear ramp rate is shown.
- the voltage at input 48 of inverter 50 will follow VDD high.
- the output 56 of inverter 54 will be brought low turning MOSFET 68 on and also forcing output 66 of inverter 60 high and output 80 of inverter 70 low.
- reset signal R at output 66 and its inverse R at output 80 will be generated.
- the voltage level at input 32 will have reached approximately 1.8 VDC at which time inverter 34 will change states.
- Output 44 is brought low forcing output 56 of inverter 56 high turning MOSFET 68 off and also forcing output 66 low and output 80 high. This terminates the reset signal R and also disconnects inverter 34 from VDD so that no current can flow through inverter 34 while the voltage at input 34 continues to rise to VDD. Therefore, stand-by current flow through these devices is virtually eliminated as soon as the reset signal is terminated.
Abstract
Description
Claims (22)
Priority Applications (1)
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US06/673,386 US4633107A (en) | 1984-11-20 | 1984-11-20 | CMOS power-up reset circuit for gate arrays and standard cells |
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US06/673,386 US4633107A (en) | 1984-11-20 | 1984-11-20 | CMOS power-up reset circuit for gate arrays and standard cells |
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US06/673,386 Expired - Lifetime US4633107A (en) | 1984-11-20 | 1984-11-20 | CMOS power-up reset circuit for gate arrays and standard cells |
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Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812679A (en) * | 1987-11-09 | 1989-03-14 | Motorola, Inc. | Power-on reset circuit |
US4825106A (en) * | 1987-04-08 | 1989-04-25 | Ncr Corporation | MOS no-leak circuit |
EP0343872A2 (en) * | 1988-05-27 | 1989-11-29 | Advanced Micro Devices, Inc. | CMOS power-on reset circuit |
US4948995A (en) * | 1987-11-06 | 1990-08-14 | Nec Corporation | Disenabling circuit for power-on event |
US4983857A (en) * | 1989-07-31 | 1991-01-08 | Sgs-Thomson Microelectronics, Inc. | Power-up reset circuit |
US4996451A (en) * | 1988-10-06 | 1991-02-26 | Sgs-Thomson Microelectronics Srl | Programmable static selection circuit for programmable devices |
US5030845A (en) * | 1989-10-02 | 1991-07-09 | Texas Instruments Incorporated | Power-up pulse generator circuit |
US5148051A (en) * | 1990-12-14 | 1992-09-15 | Dallas Semiconductor Corporation | Power up circuit |
EP0503803A1 (en) * | 1991-03-12 | 1992-09-16 | Harris Corporation | Switching circuit |
US5172012A (en) * | 1990-06-20 | 1992-12-15 | Seiko Instruments Inc. | Power-on clearing circuit in semiconductor IC |
US5223834A (en) * | 1991-11-29 | 1993-06-29 | Industrial Technology Research Institute | Timing control for precharged circuit |
US5300840A (en) * | 1991-11-25 | 1994-04-05 | Sgs-Thomson Microelectronics, S.A. | Redundancy fuse reading circuit for integrated memory |
US5323067A (en) * | 1993-04-14 | 1994-06-21 | National Semiconductor Corporation | Self-disabling power-up detection circuit |
US5414307A (en) * | 1992-09-30 | 1995-05-09 | At&T Corp. | Power reset circuit |
US5442312A (en) * | 1992-09-30 | 1995-08-15 | Siemens Ag | Integrated circuit for generating a reset signal |
US5467039A (en) * | 1993-07-08 | 1995-11-14 | Samsung Electronics Co., Ltd. | Chip initialization signal generating circuit |
US5485111A (en) * | 1993-04-08 | 1996-01-16 | Nec Corporation | Power on reset circuit with accurate detection at low voltages |
US5508649A (en) * | 1994-07-21 | 1996-04-16 | National Semiconductor Corporation | Voltage level triggered ESD protection circuit |
US5537360A (en) * | 1994-09-16 | 1996-07-16 | Dallas Semiconductor Corporation | Programmable power supply systems and methods providing a write protected memory having multiple interface capability |
US5552725A (en) * | 1994-08-05 | 1996-09-03 | Advanced Micro Devices, Inc. | Low power, slew rate insensitive power-on reset circuit |
US5564010A (en) * | 1993-05-24 | 1996-10-08 | Thomson Consumer Electronics, Inc. | Reset signal generator, for generating resets of multiple duration |
US5567993A (en) * | 1994-06-23 | 1996-10-22 | Dallas Semiconductor Corporation | Programmable power supply system and methods |
US5587676A (en) * | 1993-10-01 | 1996-12-24 | S Gs - Microelectronics Limited | Driver circuit |
US5696461A (en) * | 1994-08-31 | 1997-12-09 | Sgs-Thomson Microelectronics S.R.L. | Power-on reset circuit |
US5714898A (en) * | 1995-10-19 | 1998-02-03 | Lg Semicon Co., Ltd. | Power supply control circuit |
US5886550A (en) * | 1996-11-27 | 1999-03-23 | Electronics And Telecommunications Research Institute | Integrated circuit built-in type supply power delay circuit |
US5959926A (en) * | 1996-06-07 | 1999-09-28 | Dallas Semiconductor Corp. | Programmable power supply systems and methods providing a write protected memory having multiple interface capability |
US6104220A (en) * | 1998-01-20 | 2000-08-15 | Vlsi Technology, Inc. | Low power undervoltage detector with power down mode |
US6173436B1 (en) * | 1997-10-24 | 2001-01-09 | Vlsi Technology, Inc. | Standard cell power-on-reset circuit |
US6658597B1 (en) | 1999-10-22 | 2003-12-02 | Industrial Technology Research Institute | Method and apparatus for automatic recovery of microprocessors/microcontrollers during electromagnetic compatibility (EMC) testing |
US20050140404A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit in semiconductor memory device |
US20060232320A1 (en) * | 2005-04-14 | 2006-10-19 | Seiko Epson Corporation | Semiconductor integrated circuit |
US8493109B2 (en) | 2010-03-31 | 2013-07-23 | Qualcomm Incorporated | System and method to control a power on reset signal |
TWI470929B (en) * | 2009-01-29 | 2015-01-21 | Seiko Instr Inc | Power-on reset circuit |
CN104579263A (en) * | 2013-10-14 | 2015-04-29 | 北京同方微电子有限公司 | Reset circuit with high response speed and low temperature coefficient |
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US3895239A (en) * | 1973-12-26 | 1975-07-15 | Motorola Inc | MOS power-on reset circuit |
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US4140930A (en) * | 1976-07-30 | 1979-02-20 | Sharp Kabushiki Kaisha | Voltage detection circuit composed of at least two MOS transistors |
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1984
- 1984-11-20 US US06/673,386 patent/US4633107A/en not_active Expired - Lifetime
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US3895239A (en) * | 1973-12-26 | 1975-07-15 | Motorola Inc | MOS power-on reset circuit |
US4001609A (en) * | 1974-07-11 | 1977-01-04 | U.S. Philips Corporation | Cmos power-on reset circuit |
US4140930A (en) * | 1976-07-30 | 1979-02-20 | Sharp Kabushiki Kaisha | Voltage detection circuit composed of at least two MOS transistors |
US4045688A (en) * | 1976-10-26 | 1977-08-30 | Rca Corporation | Power-on reset circuit |
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Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4825106A (en) * | 1987-04-08 | 1989-04-25 | Ncr Corporation | MOS no-leak circuit |
US4948995A (en) * | 1987-11-06 | 1990-08-14 | Nec Corporation | Disenabling circuit for power-on event |
US4812679A (en) * | 1987-11-09 | 1989-03-14 | Motorola, Inc. | Power-on reset circuit |
EP0343872A2 (en) * | 1988-05-27 | 1989-11-29 | Advanced Micro Devices, Inc. | CMOS power-on reset circuit |
EP0343872A3 (en) * | 1988-05-27 | 1991-01-09 | Advanced Micro Devices, Inc. | Cmos power-on reset circuit |
US4996451A (en) * | 1988-10-06 | 1991-02-26 | Sgs-Thomson Microelectronics Srl | Programmable static selection circuit for programmable devices |
US4983857A (en) * | 1989-07-31 | 1991-01-08 | Sgs-Thomson Microelectronics, Inc. | Power-up reset circuit |
US5030845A (en) * | 1989-10-02 | 1991-07-09 | Texas Instruments Incorporated | Power-up pulse generator circuit |
US5172012A (en) * | 1990-06-20 | 1992-12-15 | Seiko Instruments Inc. | Power-on clearing circuit in semiconductor IC |
US5148051A (en) * | 1990-12-14 | 1992-09-15 | Dallas Semiconductor Corporation | Power up circuit |
EP0503803A1 (en) * | 1991-03-12 | 1992-09-16 | Harris Corporation | Switching circuit |
US5300840A (en) * | 1991-11-25 | 1994-04-05 | Sgs-Thomson Microelectronics, S.A. | Redundancy fuse reading circuit for integrated memory |
US5223834A (en) * | 1991-11-29 | 1993-06-29 | Industrial Technology Research Institute | Timing control for precharged circuit |
US5414307A (en) * | 1992-09-30 | 1995-05-09 | At&T Corp. | Power reset circuit |
US5442312A (en) * | 1992-09-30 | 1995-08-15 | Siemens Ag | Integrated circuit for generating a reset signal |
US5485111A (en) * | 1993-04-08 | 1996-01-16 | Nec Corporation | Power on reset circuit with accurate detection at low voltages |
US5323067A (en) * | 1993-04-14 | 1994-06-21 | National Semiconductor Corporation | Self-disabling power-up detection circuit |
US5564010A (en) * | 1993-05-24 | 1996-10-08 | Thomson Consumer Electronics, Inc. | Reset signal generator, for generating resets of multiple duration |
US5467039A (en) * | 1993-07-08 | 1995-11-14 | Samsung Electronics Co., Ltd. | Chip initialization signal generating circuit |
US5587676A (en) * | 1993-10-01 | 1996-12-24 | S Gs - Microelectronics Limited | Driver circuit |
US5567993A (en) * | 1994-06-23 | 1996-10-22 | Dallas Semiconductor Corporation | Programmable power supply system and methods |
US5508649A (en) * | 1994-07-21 | 1996-04-16 | National Semiconductor Corporation | Voltage level triggered ESD protection circuit |
US5552725A (en) * | 1994-08-05 | 1996-09-03 | Advanced Micro Devices, Inc. | Low power, slew rate insensitive power-on reset circuit |
US5696461A (en) * | 1994-08-31 | 1997-12-09 | Sgs-Thomson Microelectronics S.R.L. | Power-on reset circuit |
US5537360A (en) * | 1994-09-16 | 1996-07-16 | Dallas Semiconductor Corporation | Programmable power supply systems and methods providing a write protected memory having multiple interface capability |
US5714898A (en) * | 1995-10-19 | 1998-02-03 | Lg Semicon Co., Ltd. | Power supply control circuit |
US5959926A (en) * | 1996-06-07 | 1999-09-28 | Dallas Semiconductor Corp. | Programmable power supply systems and methods providing a write protected memory having multiple interface capability |
US5886550A (en) * | 1996-11-27 | 1999-03-23 | Electronics And Telecommunications Research Institute | Integrated circuit built-in type supply power delay circuit |
US6173436B1 (en) * | 1997-10-24 | 2001-01-09 | Vlsi Technology, Inc. | Standard cell power-on-reset circuit |
US6104220A (en) * | 1998-01-20 | 2000-08-15 | Vlsi Technology, Inc. | Low power undervoltage detector with power down mode |
US6658597B1 (en) | 1999-10-22 | 2003-12-02 | Industrial Technology Research Institute | Method and apparatus for automatic recovery of microprocessors/microcontrollers during electromagnetic compatibility (EMC) testing |
US20050140404A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit in semiconductor memory device |
US7123062B2 (en) * | 2003-12-30 | 2006-10-17 | Hynix Semiconductor Inc. | Power-up circuit in semiconductor memory device |
US20060232320A1 (en) * | 2005-04-14 | 2006-10-19 | Seiko Epson Corporation | Semiconductor integrated circuit |
US7656210B2 (en) * | 2005-04-14 | 2010-02-02 | Seiko Epson Corporation | Semiconductor integrated circuit |
TWI470929B (en) * | 2009-01-29 | 2015-01-21 | Seiko Instr Inc | Power-on reset circuit |
US8493109B2 (en) | 2010-03-31 | 2013-07-23 | Qualcomm Incorporated | System and method to control a power on reset signal |
CN104579263A (en) * | 2013-10-14 | 2015-04-29 | 北京同方微电子有限公司 | Reset circuit with high response speed and low temperature coefficient |
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