US3925703A

US3925703A - Spatial discharge transfer gaseous discharge display/memory panel

Info

Publication number: US3925703A
Application number: US372730A
Authority: US
Inventors: Jerry D Schermerhorn
Original assignee: Owens Illinois Inc
Current assignee: Techneglas LLC
Priority date: 1973-06-22
Filing date: 1973-06-22
Publication date: 1975-12-09
Anticipated expiration: 1992-12-09
Also published as: JPS5049979A; GB1479732A; DE2429663A1; NL7408359A; FR2241869A1; FR2241869B1

Abstract

A gaseous discharge display/memory panel having electrodes positioned to define discharge sites within the range of influence of other sites such that the transfer of one site to the ''''on state'''' of discharge will in the presence of appropriate potentials applied to the electrodes cause an adjacent site to be placed in the on state by spatial discharge transfer. Discharge sites are grouped as sub sites so that spatial discharge transfer is controlled in the coupling or interaction by the spatial relationships of the sub sites. Panel conductors for the discharge sites are arranged in various configurations from a single conductor having crosspoints defining discharge sub sites with two conductors to conductor arrays having a plurality of grouped conductors in each of two arrays forming a plurality of crosspoints for each conductor and patterned groups of discharge sub sites intercoupled for spatial discharge transfer. Logic can be performed internally of the panel by applying erase signals to all discharge sub sites of an on state group to be erased such that that group is in an ''''off state'''' of discharge. The truth table of groups of discharge sub sites is such that any on state sub site places the entire group in the ''''on state'''' as an OR function and only an off state for all sub sites of a group is effective to erase the group as an AND function. The negation of these functions as a NOR or a NAND can be accomplished by inverting the discharge of all groups in the panel, applying the basic function to the desired group, and reinverting the discharge states of all groups in the panel.

Description

[ Dec. 9, 1975 harge y transfer of one site to the on state of discharge will in the presence of appropriate potentials applied to the electrodes cause an adjacent site to be placed in the on state by spatial discharge transfer. Discharge sites are grouped as sub sites so that spatial disc transfer is controlled in the coupling or interaction the spatial relationships of the sub sites. Panel conductors for the discharge sitesare arranged in various configurations from a single conductor having crosspoints defining discharge sub sites with two conductors to conductor arrays having a plurality of grouped conductors in each of two arrays forming a plurality of crosspoints for each conductor and patterned groups 315/169 169 gflatrigSeClllfatfgeiub sites lntercoupled for spatial dis Logic can be performed internally of the panel by applying erase signals to all discharge sub sites of an on state group to be erased such that that group is in an off state of discharge. The truth table of groups Unite States Patent m 0 M 0 H .1 47 M m h 23 m 0 W m w o 4% R/ s m H Y l FA n O SL m T 1mm NP h n N E a c 1m. D m .m m E e .m .,m E h 7 m m a M RA 9 m mu D mnw mm C o 9 W mm m mwmn mm r. m m Warm N r TEEm n c e AS e m Am amp i I SGPI AFA Uh e h 1 1]] 1 S m m mmw mm [58] Field of [56] References Cited UNITED STATES PATENTS US. Patent Dec. 9, 1975 Sheet 1 of2 3,925,703

I Flt :1

INTERFACE,ADDRESSING & SUSTAINING VOLTAGE CIRCUITS FIG. I

FIG. 4

FIG. 3

SPATIAL DISCHARGE TRANSFER GASEOUS DISCHARGE DISPLAY/MEMORY PANEL CROSS REFERENCE TO RELATED APPLICA- TTONS This application is related to the United States Patent Applications of Jerry D. Schermerhom for Method of Introducing Logic Into Display/Memory Gaseous Discharge Panels by Spatial Discharge Transfer" Ser. No. 372,542, filed June 22, 1973, now U.S. Pat. No. 3,908,151 for Display/Memory Gaseous Discharge Panel Interconnections to Driving Circuits, Ser. No. 372,541, filed June 22, 1973, now U.S. Pat. No. 3,846,656, for Method of Driving and Addressing Gas Discharge Panels by Inversion Techniques, Ser. No. 372,553, filed June 22, 1973, now U.S. Pat. No. 3,851,210, and for Circuits for Driving and Addressing Gas Discharge Panels by Inversion Techniques, Ser. No. 372,549, filed June 22, 1973, now U.S. Pat. No. 3,840,779.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to gaseous discharge display/- memory devices and more particularly to panel conductor arrangements defining the discharge sites in such devices.

2. Description of the Prior Art Heretofore, multiple gas discharge display and/or memory panels have been proposed in the form of a pair of opposed dielectric charge storage members which are backed by electrodes, the electrodes being so formed and oriented with respect to an ionizable gaseous medium as to define a plurality of discrete gas discharge units or cells. The cells have been defined by surrounding or confining physical structure such as the walls of apertures in a perforated glass plate sandwiched between glass surfaces and they have been defined in an open space between glass or other dielectric backed by conductive electrode surfaces by appropriate choices of the gaseous medium, its pressure and the electrode geometry. In either structure, charges (electrons and ions) produced upon ionization of the gas volume of a selected discharge cell, when proper alternating operating voltages are applied between the opposed electrodes, are collected upon the surface of the dielectric at specifically defined locations and constitute anelectrical field opposing the electrical field which created them so as to reduce the voltage and terminate the discharge for the remainder of the cycle portion of the discharge producing polarity. These collected charges aid an applied voltage of the polarity opposite that which created them so they aid in the initiation of a discharge by imposing a total voltage sufficient to again initiate a discharge and collection of charges. This repetitive and alternating charge collection and ionization discharge constitutes an electrical memory.

An example of a panel structure containing nonphysically isolated or open discharge cells is disclosed One construction of a memory/display panel includes a continuous volume of ionizable gas confined between a pair of dielectric surfaces backed by conductor arrays, typically in parallel lines with the arrays of lines orthogonally related, to define in the region of registration of electrode areas through panel thickness 21 plurality of opposed pairs of charge storage areas on the surfaces of the dielectric bounding or confining the gas.

in U.S. Pat. 3,499,167 issued to Theodore C. Baker, et

a]. Physically isolated cells have been disclosed in the article by D. L. Bitzer and H. G. Slottow entitled The Plasma Display Panel A Digitally Addressable Display With Inherent Memory Proceeding of the Fall Joint Computer Conference, I E E E, San Francisco, Calif, Nov. 1966, pp 541-547 and in U.S. Pat. No. 3,559,190.

Many variations of the individual conductor form, the array form, their relationship to each other and to the dielectric and gas are available, hence the orthogonally related, parallel line arrays are discussed herein merely as illustrative.

Another construction as disclosed in U.S. Pat. application of Jerry D. Scherrnerhorn Ser. No. 239,015 filed Oct. 29, 1972, and entitled Monolithic Display Device comprises a dielectric sheet member hav ing generally parallel major faces separated by a given thickness supporting two conductor arrays. A first conductor array, which can be parallel spaced conductors, is mounted on one major surface of the dielectric member and a cooperating second conductor array is mounted on the opposite surface so that individual conductors in the opposite arrays define cooperating conductor pairs. Cavities are formed in the dielectric member adjacent each cooperating conductor pair and are filled with an ionizable gas to form a portion of the wall of a hermetically sealed discharge site associated with each pair. Advantageously, a thin dielectric overcoat is applied to those conductors otherewise exposed to the hermetically sealed volume so that the conductors are not in direct contact with the ionizable gas.

Generally the multicelled gas discharge display/me mory panels have been made of a pair of dielectric films separated by a thin layer or volume of gaseous discharge medium and covering conductor arrays on rigid nonconductive support members such as transparent glass panels. The conductors of the arrays are narrow strips of thin conductive material, typically about 8,000 angstroms thick, and may be of transparent, semi-transparent, or opaque material such as tin oxide, gold or aluminum. In typical orthogonal arrays, parallel lines of about 3 mils width spaced 17 mils center to center and having a resistance less than about 1000 ohms per linear inch of conductor line and usually less than 50 ohms per inch have been employed. Such constructions have been modified to enhance their light output from discharging cells by minimizing the shadow area of two crossing conductors by having at least one of the conductor arrays, usually that on the viewing side, formed of' conductors each made up of conductive bridges in the display area or at the element ends. This arrangement provides multiple element unitary conductors of the panel located so that the discharge is exposed between the elements without the present of an intervening opaque or semiopaque conductive layer over the center of the discharge site. Details of such a divided conductor discharge device construction are shown in U.S. Pat. No. 3,603,836 which issued Sept. 7, 1971 to John D. Grier and is entitled Conductor Configurations for Discharge Panels.

In prior art, a wide variety of gases and gas mixtures have been utilized as the ionizable gaseous medium it being desirable that the gas provide a copious supply of charges during discharge, be inert to the materials with which it came in contact, and where a visual display is desired, be one which produces visible light or radiation which stimulates a phosphor. Preferred embodiments of the display panel have utilized at least one rare gas, more preferably at least two, selected from helium, neon, argon, krypton or xenon.

In an open cell Baker et al. type panel, the gas pressure and the electric field are sufficient to laterally confine charges generated on discharge within elemental or discrete dielectric areas confined generally to a region in proximity to the registering projections of opposed electrodes through the dielectric layers and gas. The space between the dielectric surfaces occupied by the gas is such as to permit photons generated on discharge in a selected discrete or elemental volume of gas to pass freely through the gas space and strike surface areas of dielectric remote from the selected discrete volumes, such remote, photon struck dielectric surface areas thereby emitting charged particles so as to condition at least one elemental volume other than the elemental volume in which the photons originated.

With respect to the memory function of a given discharge panel, the allowable distance or spacing between the dielectric surfaces depends inter alia, on the frequency of the alternating potential imposed, the distance typically being greater for lower frequencies.

While the prior art does disclose gaseous discharge devices having externally positioned electrodes for initiating a gaseous discharge, sometimes called electrodeless discharge, such prior art devices utilized frequencies and spacing or discharge volumes and gas pressures such that although discharges are initiated in the gaseous medium, such discharges are ineffective or not utilized for charge generation and storage at higher frequencies. Although charge storage may be realized at lower frequencies, such charge storage has not been utilized in a display/memory device in the manner of the Bitzer-Slottow or Baker et al. devices.

In operation of the display/memory device an alternating voltage is applied, typically, by applying a first periodic voltage wave form to one array and applying a cooperating second wave form, frequently identical to and shifted on the time axis with respect to the first wave form, to the opposed array to impose a voltage across the cells formed by the opposed arrays of electrodes which is the algebraic sum of the first and second wave forms. The cells have a voltage at which a discharge is initiated. That voltage can be derived from externally applied voltage or a combustion of wall charge potential and externally applied voltage. Ordinarily, the entire cell array is excited by an alternating voltage which, by itself, is of insufficient magnitude to ignite gas discharges in any of the elements. When the walls are appropriately charged, as by means of a previous discharge, the voltage applied across the element will be augmented, and a new discharge will be ignited. Electrons and ions again flow to the dielectric walls extinguishing the discharge; however, on the following half cycle their resultant wall charges again augment the applied external voltage and cause a discharge in vthe opposite direction. The sequence of electrical discharges is sustained by an alternating voltage signal that, by itself, could not initiate that sequence. The half amplitude of this sustaining voltage has been designated V Any given cell has a range of sustaining voltages. A panel is operated near the center of this range to accommodate individual cell differences.

In addition to the sustaining voltage there are manipulating voltages or addressing voltages imposed on the opposed electrodes of a selected cell or cells to alter the state of those cells selectively. One such voltage termed a writing voltage transfers a cell or discharge site from the quiescent to the discharging state by virtue of a total applied voltage across the cell sufficient to make it probable that on subsequent sustaining voltage half cycles the cell will be in the on state. A cell in the on state can be manipulated by an addressing voltage termed an erase voltage which transfers it to the off state by imposing sufficient voltage to draw off the surface or wall charges on the cell walls and cause them to discharge without being collected on the opposite cell walls so that succeeding sustainer voltage transitions are not augmented sufficiently by wall charges to ignite discharges.

A common utilization of writing voltages is to superimpose them on a sustainer wave form in an aiding direction and cumulatively with the sustainer voltage achieve the cells tum on voltage. Erase voltages are superimposed on a sustainer wave form in opposition to the sustainer voltage to develop a voltage level sufficient to draw the charges from the dielectric surfaces and discharge them without collecting charges in a significant quantity on the dielectric wall opposite that from which they were drawn. The wall voltage of a discharged cell is termed a off state wall voltage and frequently is midway between the extreme magnitude limits of the sustainer voltage, 2 V

The stability characteristics and non-linear switching properties of these bistable cells are such that in the case of a cell which has not fired in the preceding half cycle of sustaining voltage the state of any cell in the cell array can be changed by selective application of an external voltage which exceeds the turn on or discharge igniting potential. In the case of a cell which has been fired in the preceding half cycle and has accumulated charges which can aid the sustaining voltage, the cell can be turned off by applying a voltage which discharges the cell. These manipulating signals are applied in a timed relationship with the alternating sustaining voltage, and through control of discharge intensity, accomplish selective state transitions by changing the wall voltage of only the cell being addressed.

Cells are transferred to the on state by applying a portion of the manipulating signal superimposed on the sustaining voltage termed a select signal on each of two opposed electrodes which constitute the cell. Conventionally, like sustaining signals are imposed on each electrode array so that half the sustaining voltage is imposed on each array and half the select signal is imposed on the addressed cell electrode in each electrode array at a time when the sum of the applied voltages is sufficient to ignite a discharge. Further, the partial select signals on each electrode are limited to a value which will not impose a firing potential across other cells defined by that electrode and not selected. A typical write signal for a cell is developed by applying half select voltages to the addressed electrodes of the cell to be placed in the on state at a time the sustaining voltages are developing a pedestal potential somewhat below the maximum sustaining voltage. Typically, a write signal is imposed on each opposed electrode of the cell during the terminal portion of a sustain voltage half cycle when any wall charging which may result from the prior sustainer transient is substantially completed. The manipulating signal thus ignites a single, and unique, cell at the intersection of the selected two opposed electrodes. This ignited discharge thus establishes the cell in the on state since a quantity of charge is stored in the cell such that on each succeeding half the charge stored :in the cell is discharged at a time when the sustaining voltage is imposing a voltage in opposition to the wall charge voltage. As for writing, the

erase manipulation is facilitated if the sustaining voltage is at a pedestal level below the level providing the maximum applied voltage so that the erase half select voltages are at a convenient level/Typically an erase signal is imposed on each opposed electrode of the cell during the terminal portion of a sustain voltage half cy-' cle, when the wall charging from the prior sustainer discharge is substantially completed, but proceeding the next half cycle alternation by enough time so that the wall discharge of the selected cell is substantially stabilized.

In the operation of a multiple gaseous discharge device, of the above described type, it is necessary to condition or prime the discrete elemental gas volume of each discharge cell by supplying at least one free electron thereto such that a gaseous discharge can be initiated when the cell is addressed with an appropriate voltage signal.

One such means of panel conditioning comprises periodically applying an electronic conditioning signal or write pulse to all of the panel discharge cells. However,

electronic conditioning is self-conditioning and is only effective after a discharge cell has been conditioned previously; that is electronic conditioning involves periodically discharging a cell. Accordingly, one cannot wait too long between the periodically applied conditioning pulses since there must be at least one free electron present in order to discharge and condition a cell.

External radiation can be employed to condition a panel, as by flooding part or all of the gaseous medium of the panel with untraviolet radiation. This is sometimes inconvenient since external radiation may not be available to the panel and at best, required auxiliary equipment.

A frequently employed conditioning termed internal conditioning comprises using internal radiation such as from a radioactive material.

Photon conditioning where .photons excite electrons as by impingement upon the dielectric surface of the cells is utilized by providing one or more pilot discharge cells maintained in the on state for the generation of photons. This is particularly effective in an open cell construction as disclosed by Baker et al. where the space between the dielectric surfaces occupied by the gas is such as to permit photons generated on discharge in a sele'cteddiscrete or elemental volume of gas to pass freely through the panel gas space so as to condition other elemental volumes of other discharge units. In addition to or in lieu of the pilot cells, other sourcesof photons internal to the panel may be used.

Internal photon conditioning may be unreliable when a given discharge unit to be addressed is remote in dis tance relative to the conditioning source. Accordingly, a multiplicity of pilot cells may be required for the conditioning of a panel having a large area. in one highly convenient arrangement, the panel matrix border is comprised of a plurality of such pilot cells.

Circuitry for sustaining voltages, and where employed jtheir pedestals, and for the manipulating voltquite extensive.

Transformer coupling of manipulating signals to the electrodes of multiple gas discharge display/memory devices has been disclosed in William E. Johnson et a1. U.S. Pat. No. 3,618,071 for Interfacing Circuitry and Method for Multiple Discharge Gaseous Display and/or Memory Panels which'issued Nov. 2, 1971. The coupling of individual electrodes in large arrays involving substantial numbers of electrodes is cumbersome and expensive. Accordingly, solid-state pulser circuits capable of feeding through the sustaining voltage were proposed as exemplified in William E. Johnson U.S. Pat. No. 3,611,296 of Oct. 5, 1971 for Driving Circuitry For Gas Discharge Panel. Multiplexing of the signals to the electrodes in an array has been utilized employing combinations of diode and resistor pulsors to manipulate cell potentials as shown in U.S. Pat. No. 3,684,918 issued Aug. 15, 1972 to Larry J. Schmersal for Gas Discharge Display/Memory Panels and Selection and Addressing Circuits Therefore.

Complex and massive addressing circuitry has been required where large panel arrays have been addressed on a per conductor basis. Attempts to reduce the mass of such addressing means have included coincidence gates and binary coding schemes whereby combinations of gating signals are fed to ANDS which have their outputs connected to the external terminals of the individual panel conductors. One such arrangement accommodating binary coded address signals is illustrated in U.S. Pat. No. 3,611,296 by William E. Johnson which issued Oct. 5, 1971 and is entitled Driving Circuitry for Gas Discharge Panel.

A first object of this invention is to improve gas discharge panels. A

A second object of the present invention is to simplify the external circuitry for gas discharge panels.

Another object is to accomplish logic functions internally of gas discharge panels.

A fourth object is to provide decoding means internally of gas discharge panels.

An additional object is to influence the discharge state of one cell or portion thereof in response to the discharge stateof a nearby cell or portion thereof.

SUMMARY OF THE INVENTTON Particular utility is realized by employing grouped sites or cells as individual display sites or image bits where the panel is made up of a plurality of suchcells which are not subject to intercell spatial discharge transfer and are each controllable through intra sub site spatial discharge transfer. In the following disclosure the grouped sites will be treated as subdivided into discharge sub sites defined by proximate portions of paired conductor regions of conductors of opposed arrays and all sites of a group will be treated as a single discharge site or cell.

Control of such cells to transfer from the off state of discharge to the on state of discharge is by imposing a in the erase mode for individual cell control. That is in I order to transfer a cell from the on state to the off state all sub sites of which it is composed must be erased or transferred to the off state for, if any one sub site remains in an on state, spatial discharge transfer will reignite discharge in the associated sub sites of its cell.

The method of control by inversion logic as disclosed in US. Pat. application Ser. No. 372,553 filed June 22, 1973, now US. Pat. No. 3,851,210 in the name ofJerry D. Scherrnerhorn entitled Method of Driving and Addressing Gas Discharge Panels by lnversion Techniques lends itself to AND or NAND logic operation of panels constructed according to this invention. According to that method cells are erased while the panel is inverted in its discharge state so that upon reinversion the erased cell is placed in a written state. Further the method utilizes grounded partial select signals to erase and electronically symmetrical sustainer voltage and cell addressing circuitry by employing asymmetrical sustainer voltage components referenced to ground or a slight offset from ground. Inversion is accomplished by interchanging the sustainer voltages imposed on the opposed conductor arrays of the panel such that the array subject to the smaller voltage, e.g. between ground and about A V has the larger voltage, e.g. between about V and the opposite polarity of about /2 V while that which was subject to the larger voltage is subject to the smaller voltage. Such an interchange, where voltage levels are appropriately chosen for the cell parameters of the device to which it is applied, results in the off state. wall voltage of the composite sustainer voltage wave form for normal sustainer conditions coinciding or nearly coinciding with the cell wall voltage for on state cells during inversion while the cell wall voltage for on state cells for normal sustainer conditions coincides or nearly coincides with the off state wall voltage for the inverting sustainer voltage condition.

In employing internal AND or NAND logic, large cell matrices can be controlled with relatively few external connections to the conductors of the conductor arrays. Such cell matrices can be expanded from a single cell having two discharge sub sites made up of one conductor in one array having portions proximate to portions of two conductors which are proximate to each other in the other array to a single cell made up of four discharge sub sites made up of two conductors in one array each having a portion proximate to each other and to each of two conductors in another array or to .cells with greater numbers of sub sites and component DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a gaseous discharge display/- memory panel according to this invention and made up of a matrix of cells each comprising four sub sites as 8 connected to diagrammatically illustrated sources of operating potentials;

FIG. 2 is an exaggerated cross-sectional view (enlarged but not to proportional scale since the thickness of the gas volume, dielectric members and conductor arrays have been enlarged for purposes of illustration) taken on the lines 22 of FIG. 1;

FIG. 3 is an enlarged plan view of the conductor cross points of one discharge cell made up of four discharge sub sites together with lines generally representing the discharge regions between individual cross points and the interconnecting discharge fringe regions which give rise to spatial discharge transfer between related sub sites;

FIG. 4 is a diagrammatic plan view of a single cell comprising two discharge sub sites to illustrate the most elemental form of display/memory device offering spatial discharge transfer;

FIG. 5 is a diagrammatic plan view of a matrix of cells of the type shown in FIG. 4 wherein each cell is made up of two discharge sub sites which afford spatial discharge transfer between sub sites of each cell and wherein the cells are spaced sufficiently to avoid spatial discharge between cells;

FIG. 6 is a diagrammatic plan view of a four cell matrix or matrix portion in which each cell has nine discharge sub sites subject to spatial discharge transfer;

FIG. 7 is an isometric view of a sectioned fragment of a monolithic structure offering spatial discharge transfer between discharge sub sites of discharge cells each having four sub sites;

FIG. 8 is a diagrammatic plan view of the monolithic structure of FIG. 7;

FIG. 9 is a diagrammatic plan view of another form of monolithic structure having a discrete cavity in the region of each cell; and

FIG. 10 is a cross-section of one cavity form which can be employed with the structure of FIG. 9, taken along line 10I0 of FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENT One form of multicelled gas discharge display/memory device according to this invention, as shown in FIGS. 1 and 2, utilizes a pair of

dielectric films

10 and 1 1 separated by a thin layer or volume of a gaseous discharge medium 12, the medium producing a copious supply of charges (ions and electrons). These charges are alternately collectable on the surfaces of the dielectric members at opposed or facing elemental or discrete areas defined by the conductor arrays on the nongas contacting sides of the dielectric films l0 and 11. For convenience the upper array will be termed the x array and the lower array the array. While the electrically operative structural members, such as the dielectric members 10 and l 1 and the x and y conductors, are all relatively thin (being exaggerated in thickness in the drawings), they are formed on and supported by rigid

non-conductive support members

13 and 14 respectively.

One or both of the

non-conductive support members

13 and 14 pass light produced by discharges in the elemental gas volumes unless only the memory function is utilized, in which case they can be opaque. Advantageously they are transparent glass.

Members

13 and 14 essentially define the over-all thickness and strength of the panel. They serve as heat sinks for heat generated by discharges and thus minimize the effect of temperature on operation of the device. For example, the gas layer 12 is usually under mils and typically about 4 to 6 mils in thickness as determined by spacer 15.

Dielectric layers

10 and 1 1 (over the conductors) are usually between 1 and 2 mils thick.

Support members

13 and 14 are typically about one-eighth to one-quarter inch thick.

Spacer 15 may be made of the same glass material as dielectric films 10 and 11 and may be an integral rib formed on one of the films l0 and 11 overlying

dielectric members

13 and 14 or directly on the

dielectric members

13 and 14 and fused to the other film or member to form a bakeable hermetic seal enclosing and confining ionizable gas volume 12.

Conductor arrays 16 and 17 may be formed in situ on

support members

13 and 14, for example as individual conductor strips about 8,000 angstroms thick, and may be transparent, semi-transparent, or opaque conductive material such as tin oxide, gold or aluminum. According to this invention, at least a pair of conductor strips is employed in at least one array as disclosed in FIGS. 4 and 5 and where AND logic is to be accomplished in both conductor coordinates a plurality of pairs of conductor strips are utilized in each array 16 and 17 as shown in FIGS. 1, 2, 3 and 6. Paired cross points 18 of x conductor strips 19 and y conductor strips 20 define discharge sub sites which are sufficiently close to each other as to have a discharge in one institute a discharge in the other. Thus, the combined sub sites are considered a cell 21. In order to designate cells 21 in the illustrated orthogonal matrix, they will be assigned reference characters of their coordinate and rank or column as x-1 through x-4 and y-l through y-4 in FIG. 1. Further, since a multiplicity of conductors can be present in a rank or column alphabetical suffixes will be applied. Thus the lower left-comer cell 21 of FIG. 1 is designated cell x-l, y-/ and is made up of conductor strips 19-1a and 19-1b, and 20-1a and 20- lb. Similarly, the cross points 18 are designated by their conductor strips so the lower left cross point of cell x1, y-l is l9-1a and 20-1a.

As described above the construction of the display device can assume many forms including equally spaced curved support surfaces for the conductor arrays. A preferred form is a flat display panel made up of parallel dielectric support panels which can be transparent glass for display of the cells as discrete lighted spots in a matrix forming a darker background or of darkened spots on a lighted background. Generally, the device construction can be conventional and according to the open celled construction of Baker et al. US. Pat. No. 3,499,167. Operation can also be according to Baker et al. The distinctions over prior devices residing in the spacing of the conductors in the arrays making up the panel and the utilization of the internal logic function attainable with such constructions.

In the illustrated construction of paired, orthogonally related conductors a typical cell 21 is comprised of straight strips 3 mils wide spaced on 6 mil centers so that a 3 mil open strip is between each pair. The cells in such an array are typically spaced on 16 mil centers in order to insure isolation of spatial discharge transfer to intracell discharge sub sites. It is to be appreciated that the interaction between sub sites is based on the fring ing of the discharge effects beyond the shadow area of the conductor cross points. Typically, a plane panel device having a neon-krypton or neonargon gas atmosphere with neon about 99.7% by weight at about at- 10 mospheric pressure and a thickness of 4.5 to 4.7 mils exhibits spatial discharge transfer between electrodes up to 3.5 to 5 mils apart without interaction between elements 7 to 10 mils apart, depending to a degree on the size of the conductors, the thickness of the dielectric overcoat, and the gas parameters.

The spacing in an array of the grouped conductors having portions which constitute effective electrode areas of sub sites of a cell can be within a range which depends to a degree upon the thickness of the dielectric overcoat 10 and 11 above the conductors and the gas volume geometry, composition and pressure. In general the discharge characteristics of the gas are a determining factor. Discharges occur in the region of the gas volume which is proximate to the sub site electrodes of the opposed arrays with some extension beyond the projection of the areas perpendicular to the conductor arrays. Thus'there is also a lower limit to the conductor spacing of grouped conductors of a cell in an array. When the conductor edges are too close, the field pattern of one can extend over the region of influence of others whereby an erase signal imposed on less than all sub sites of the cell draws enough charge from the walls of the sub site of the adjacent grouped conductors to place all sub sites of the cell in an off state. First and second paired conductors of one array such a 19-/a and 19-1b should be conductively isolated from each other, so spaced from each other and the sub site electrode areas of a conductor or conductors in the opposed array as to be adapted to initiate an on state of discharge in a discharge sub site including one of the first and second conductors which is in an off state of discharge in response to an on state of discharge in the discharge sub site of the other of the first and second conductors, and so spaced from each other and the sub site electrode areas of a conductor or conductors in the opposed array as to be adapted to maintain an on state of discharge in a discharge sub site including one of the first and second conductors in response to the transfer of the other sub site including the other of the first and second conductors from an on state of discharge to an off state of discharge in response to a manipulating signal superimposed on the sustainer voltage imposed on those conductors.

A sustainer voltage component which periodically shifts in level on a cyclic basis is applied to each of the x and y arrays to impose a composite sustainer voltage which alternates with a total excursion across the cells and each sub site of 2 V typically about 220 volts for the exemplary constructions. In order to manipulate the discharge state of the cells and sub sites, voltages are imposed on the sustainer level. By definition, for any given set of cell parameters the sustainer voltage 2 V, is such that a cell in the on state of discharge is sustained in the on state as the voltage alternates by causing the wall charge accumulated on the dielectric surfaces to transfer to opposed surfaces and provide a wall voltage augmenting the next half sustainer cycle to fire the cell while a cell in the off state of discharge remains in that state during the alternation. Transfer of an off state site to an on state of discharge is accomplished by raising the applied voltage to a level which institutes a discharge, usually as a signal superimposed on and augmenting the sustaining voltage. In the process of initiating a discharge in one sub site the positive ions 24 in the gas 12 accumulate on the dielectric surface overlying the negative conductor in its region of registry with its opposed conductor region and the negative particles,

electrons 25, accumulate on the dielectric overlying the positive conductor. These charged particles are excited in the gas volume between the electrodes subject to the firing voltage and while they are generally localized to that region some are in fringe areas beyond the zone in registry with the registering electrodes. Such fringing which may tend to follow the underlying conductors in the vicinity of the cell wall so that the region near the cell wall of the x array conductors is elongated in the x dimension represented by the dashed line 22, while that near the y conductor wall is elongated in the y dimension, represented by the dot-dashed line 23. Further, the fringing is sufficient so that sustainer voltage fields imposed on the adjacent sub sites of a cell having one sub site in an on state of discharge will attract sufficient charged particles into those sub sites to place them in an on state of discharge either in the same cycle of sustainer voltage in which the first sub site was turned on or the next succeeding cycle.

Since the spatial discharge transfer between sub sites is dependent upon the proximity of the sub sites, the sites themselves can be arranged in many desired forms as in the form of characters such as letters or numerals by parallel and closely spaced conductors in at least one array. Further, paired conductors in one array can cooperate with a single conductor in its opposed array as illustrated in FIGS. 4 and 5. The gating function of this form of device can be arranged with greater numbers of inputs by grouping a greater number of conductors in spatial discharge transfer proximity to each other as with three or more parallel conductors as will be discussed with respect to FIG. 6.

A convenient construction for devices of the type shown in FIGS. 1, 2 and 3 is to apply and secure conductors l9 and 20 to their

support members

13 and 14. Their dielectric layers 10 and l l are formed of an inorganic material, preferably in situ, as adherent films or coatings which are not chemically or physically affected by elevated temperatures. One such material is a solder glass such as Kimble SG-68 manufactured by and commercially available from the assignee of the present invention. This glass has a thermal expansion characteristic substantially matching the thermal expansion characteristics of certain soda-lime glasses suitable, when in plate form, for supporting

members

13 and 14. Dielectric layers 10 and 11 must be smooth and have a dielectric strength of about 1,000 volts per mil and be electrically homogenous on a microscopic scale (i.e. no cracks, bubbles, crystals, dirt, surface films or other irregularities). Also, the surfaces of dielectric layers 10 and l 1 should be good photo-emitters of electrons to enable priming or conditioning of the cells for transfer to an on state of discharge. Alternatively, dielectric layers 10 and 11 may be overcoated with materials designed to produce good electron emission, as in US. Pat. No. 3,634,719, issued to Roger E. Ernsthausen.

The ends of paired x array conductors 19-1a, 19-1b, 19-na, l9-nb and support members 13 extend beyond the spacer side wall enclosing gas volume 12 within the margin 26 and are exposed for the purpose of making electrical connection to external circuitry generically termed the interface, addressing and sustaining voltage circuits 27. Likewise, the ends of paired y array conductors -1a, 20-1b, 20-na, 20-nb on support member 14 extend beyond spacer side wall 15 and are exposed for the purpose of making electrical connections to the circuits 27.

A particular advantage of the conductor configurations of the illustrated devices is their capability to function as coincidence gates or logic ANDs by virtue of spatial discharge transfer. In some utilizations it is desirable that a cell change its discharge state only when a coincidence of input signals are imposed. Heretofore, such coincidences were utilized for control of a cell by circuitry external of the device. Since plurality individual inputs for manipulating signals are available for at least one array of a cell according to this invention and the discharge sub sites of that cell have coupled operation in their transfer into the on state of discharge, the transfer to the off state for the cell can be accomplished only if all of its discharge sub sites are in the off state of discharge simultaneously. The requisite coincident off state of all sub sites can be employed to either write or erase a cell. A cell in the on state" of discharge can be erased by employing coincident erase manipulative signals addressed to all conductors of the arrays which have cross-points defining discharge sub sites of that cell while the device is operating in its normal mode. A cell in the off state of discharge can be written by inverting the discharge state of the matrix including the cell so that the subject cell is in an on state of discharge, then erasing that cell by applying erasing signals to all sub sites of the cell to place them all in an off state of discharge, and then reinverting the matrix so that the subject cell is in the on state.

All cells of a display panel can be inverted in their discharge state by shifting voltage levels applied to the cells of the panel. For a given operating mode established by a given sustainer voltage applied as component voltages on the x and y arrays, all cells in the on state of discharge have a wall voltage on the dielectric film overlying the conductor portion defining the discrete discharge sub sites established at a level approaching the applied voltage. This wall charge voltage is opposite the polarity of the voltage applied to the underlying electrodes. Upon reversal of the polarity of the applied sustainer voltage, the wall charge voltage augments the sustainer voltage sufficiently to impose the firing voltage of the discharge sub sites across the ionizable gas in those sub sites. The discharges occur and the charge particles accumulate on the cell walls in an opposite orientation and corresponding wall voltage levels as for the preceding half cycle of the sustainer voltage so that upon the next reversal of the sustainer voltage the wall charge voltage again augments the voltage across the cell to achieve the firing voltage. Cells in the off state have an off state wall voltage, usually midway between the extremes of the excursions of the sustainer voltage.

Inversion of a cell matrix subject to a sustainer voltage is achieved by shifting the excursion limits of the sustainer while continuing to impose the sustainer voltage magnitude, 2 V across the conductor arrays forming the matrix. The shift is such that the off state wall voltage level for the shifted sustainer is at or near the on state wall voltage established prior to the shift and the on state wall voltage for the shifted sustainer is at or near the off state wall voltage established prior to the shift. The shift will therefore cause the prior off state wall voltage level to augment the next sustainer voltage transition to the cell firing level and place the formally off cells in an on state while the wall voltage of the formerly on state cells is at the new off state level and has no augmenting effect so that the former on state cells are off while the inversion levels of sustainer voltage are imposed; Reinversion of the cell matrix is by a shift of sustainer voltage levels to their original levels. One form of a suitable sustaining voltage circuit for cell matrix discharge state inversion is shown in the aforenoted Scherrnerhorn patent application entitled Circuits for Driving and Addressing Gas Discharge Panels by Inversion Techniques.

The erase signals, manipulative signals for individual discharge sites, are imposed in opposition to the currently applied sustainer voltage at a level sufficient to discharge the wall charge on the walls of the addressed cell which is in the on state of discharge without accumulating a sufficient wall charge on the opposite wall to augment the next sustainer voltage transition to the site firing level. In the circuits of the patent application entitled Circuits for Driving and Addressing Gas Discharge Panels by Inversion Techniques the erase signals for both the normal sustainer voltage operating mode and the inverting sustainer voltage operating mode are imposed by'grounding the conductors of the opposed array which, by their cross point, define the addressed discharge site. Where the circuit of that disclosure applies the sustaining voltage components for the x array to all conductors of the x array, the panel of FIGS. 1, 2, and 3 has its cells controlled by erase signals applied coincidentally to the grouped conductors of each array the cross points of which constitute the discharge sub sites of the cell to be addressed. Thus for cell x-1,-y-1 conductors x- 1a and x-2a would receive x erase signals and conductors y-1a and y-2a would receive y erase signals so that all of the discharge sub sites of cross points 19-1a, 20-1a and 19-1a, 20-1b and 19-1b, 20-la and 19-112, 20-1b are transferred to the off state.

While cells 21 each composed of four discharge sub sites 18 have been shown as made up of a cross point of an a conductor of an a conductor set and a b conductor of a b conductor set for each of the x array 16 and the y array 17, it is to be understood that only two such proximate cross points are required to achieve discharge interaction of spatial discharge transfer. As shown in FIG. 4, logic can be accomplished internally with a single x conductor 28 and paired

conductors

29 and 31 having their cross points 32 and 33 with 28 sufficiently proximate for spatial discharge transfer. With a sustainer voltage imposed between 28 for the x component and 29 and 31 for the y component write partial select signals on 28 and either of 29 or 31 will institute a discharge at both

discharge sub sites

32 and 33. Erase partial select signals, however, will not be effective to transfer the cell 34 comprising 32 and 33 to an off state unless applied to all

conductors

28, 29 and 31.

FIG. 5 shows a matrix 35 of cells 36 each of which comprises an x conductor 37-1 37-4 and one conductor of the a set of y conductors and one conductor of the b set of y conductors 38-1 38-4 to make up a plurality of cells of two sub sites each.

In FIG. 6 nine discharge sub site cells 41 are illustrated to illustrate a three by three coincidence gate arrangement for AND logic in a display memory panel. In this arrangement each conductor array is made up of three sets of conductors designated a, b and c which are grouped for each cell in groups of three, one form each set, as x conductors 42- 1a, 42-112 and 42- 10 all of which must be subject to an erase partial select signal to erase the cell.

The general arrangement for a display/memory device of at least a pair of conductors which are relatively closely spaced and are spaced in operative relationship to at least a second conductor so that independent manipulating electrical signals can be applied to the conductors while a sustainer voltage component is applied to the pair and another component is applied to the second conductor lends itself to various constructions which have bistable disc charge conditions. Such constructions having an enclosure for ionizable gas and having a thin dielectric film separating the conductors from the gas at least in the region between the conductors in which the discharge occurs can be in a geometry which lends itself to monolithic forms wherein the several conductors dielectric film overcoats and walls defining the discharge region are in a common base. FIGS. 7 through 10 illustrate typical monolithic geometries for a discharge device of this type.

A common support substrate 43 which can be a suitable dielectric such as a glass plate has a first conductor array of paired conductors 44 formed on its upper face as viewed in FIG. 7 to form a first or bottom conductor array 45. This conductor array can be formed in the manner of the arrays of FIGS. 1-3 by either a printing process or as small guage wires placed in the desired pattern and adhered to the plate 43.

A dielectric layer or coating 45 is applied over conductors 44 with a thickness of from about 0.5 mils to about 6 mils, typically about 1.2 mils thick as illustrated. A variety of dielectric materials, especially lead borosilicates, are useful for this purpose. A plurality of discharge cavities 47 are formed in the layer 45 either by masking the material as it is applied in a powder or thick slurry which is fired in situ or by firing the layer 45 and thereafter forming the cavities by well-known photoetching techniques and/or chemical etching through a mask or screen. Alternatively, the layer can be machined as by means of a laser beam, sonic source, or like-energy means. Cavities 47 are shown as troughs extending across a substantial portion of the face of the monolithic structure.

A top cooperating conductor array 48 made up of paired conductors 49 is applied to the upper surface of the dielectric coating or layer 34 and can be applied in the same manner as the bottom conductor array 45 (it will be appreciated that the terms top and bottom are relative and could just as well be called frow and column conductor arrays). Conductors 49 are at transverse angles to conductors 44 to thereby define a plurality of matrix cross points.

The cavities 47 are shown between the conductors 49 which are paired with a proximity which provides a gas volume to accommodate the interaction of spatial discharge transfer and thus are of suitable dimensions to permit the discharge pattern between cross points forming discharge sub sites as defined by the cavity walls to fringe into the range of influence of the associated sub sites of the cells. The cavities may comprise any suitable geometric shape such as a round or rectangular hole provided the open region affords a suitable discharge zone for the sub sites of the cells. Typically the grooves or trough cavities 47 can be about 4 mils at the top and about 3 mils at the bottom with a dielectric layer 51 applied over the upper conductor array and the cavity walls of a thickness of about 1 mil. This spaces the 3 mil wide conductive strips which are paired by about 4 mils (7 mils center to center). The proximate edges of conductors of adjacent cells should 15 be spaced at least 7 mils and preferrably about 9 mils so that the longitudinal centers of the paired conductors and cavities 47 are spaced about 16 mils. The greatest extension of the cavity bottoms is within about 0.1 to 0.2 mils from the upper faces of conductors 44.

The electrically operative structural elements as monolithically formed in an integral assembly 52 has its upper face and the cavities enclosed to define a hermetically sealed chamber for ionizable gas. A glass plate 53 is shown spaced from the assembly 52 to form a wall of this chamber where the assembly forms an opposite wall and suitable sealing spacer elements and exposed electrical terminal ends for

conductors

44 and 49 are provided at the edges of the panel like envelope all in the manner of the structures of FIGS. 1 through 6. Alternatively, the assembly 52 can be mounted within an envelope (not shown) with a suitable viewing panel provided for its upper face, or, in the case of transparent substrate 43 and

dielectric films

45 and 51, for its lower face.

FIGS. 9 and 10 show another monolithic structure in a matrix of nine cells 55 each made up of paired x array conductors 56, as 56-1a, 56-lb 56-3a and 56-3b, and paired array conductors 57. As in FIGS. 7 and 8, a substrate 58 provides a base upon which conductors 57 are mounted and then covered with a dielectric layer 59. The x array conductors 56 are formed on the layer 59 and coated with a dielectric 61. An upper plate 62 spaced from the free surface of dielectric 61 provides a major wall of the hermetically sealed enclosure for ionizable gas volume 63. In this embodiment the cavities 64 defining the principal discharge region of each cell 55 are individual to the cells and are located intermediate the cross points of

conductors

56 and 57 which are the effective electrode areas of each sub site of the cells. The discharge sub site wall upon which wall charge is developed in cell operation is the side wall of the cavity 64 proximate the effective electrode areas. As shown in FIG. 10 the cavities extend as right circular cylinders through

dielectric layers

61 and 59 and into substrate 58 so that they extend between and below lower electrodes 57. The dimensions of the elements and their spacings can be as for FIGS. 7 and 8. Further the cutaway regions forming the cavities need not be right circular cylinders and need not extend be yond or even to the level of the lower electrodes 57, however a dielectric overcoat should be left between the

electrodes

56 or 57 of at least one array and the gas volume 63 including cavities 64.

The ionizable gases for the devices of this type can be of a wide variety. Typical of such gases include C; C0 halogens; nitrogen; NH oxygen; water vapor; hydrogen; hydrocarbons; P 0 boron fluoride; acid fumes; TiCl Group VIII gases; air; H 0 vapors of sodium, mercury, thallium, cadmium, rubidium, and cesium; carbon disulfide; laughing gas; H 8; deoxygenated air; phosphorus vapors; C H CH naphthalene I vapor; enthracene; freon; ethyl alcohol; methylene bromide; heavy hydrogen; electron attaching gases; electron free gases; sulfur hexafluoride; tritium; radioactive gases; and the rare or inert gases.

In one embodiment hereof, there is utilized two or more rare gases selected from neon, argon, xenon, krypton, and radon in the presence or absence of effective amounts of other gaseous components such as mercury and/or helium.

In the discussion of the plural sub site cells and matrices of such cells it has been assumed that a like sus- I6 tainer voltage has been applied across all conductors of each array. That is, it has been assumed that the sustainer component on the x array conductors is identical for each conductor of each set of conductors, the a and b sets in FIGS. 1 and 3, and that the y sustainer component is applied to each set of conductors in its array. It should be understood that spatial discharge transfer employing the geometries of this invention in the display/memory device or panel can be advantageously achieved with different sustainer voltages on the several conductors of an array as where the voltages are shifted in phase or of different values. A device or panel is operable over a range of sustainer voltage levels, and while devices to which a single sustainer voltage is applied are usually operated near the center of that range, useful ouputs, for example where different levels of cell brilliance are to be achieved, can be obtained with different sustainer levels on selected conductors to impose different levels across the sub sites.

It is to be understood that spatial discharge transfer in a gaseous discharge display/memory device subjected to an alternating sustainer voltage can be achieved by other geometries than those illustrated above provided discharge sub sites are defined by at least two conductors in one may having regions in sufficient proximity to each other and to at least one conductor in another array that the ignition of a discharge between that one conductor and one of the two will cause a discharge between that one conductor and the other. Further, groups of conductors greater than the paired conductors can be arranged for spatial discharge transfer. While open celled arrangement of cell matrices have been illustrated with spacings of at least 7 mils between conductors of cells which are not to effect each other by spatial discharge transfer, barriers can be employed to enhance the operational isolation between cells. Accordingly, the variations in structure and combinations of elements shown above are intended as il: lustrative of the invention and are not to be read in a limiting sense.

What is claimed is:

1. A gas discharge display/memory device comprising a first and a second conductor having proximate portions, said first and said second conductors being spaced and non-intersecting; a third conductor having an effective electrode region proximate each of the proximate portions of said first and second conductors; a volume of ionizable gas between said first and second conductor proximate portions and said the third conductor effective electrode region; a dielectric layer between said gas volume and at least one of said conductors; an enclosure for said gas volume; said proximate portions of each of said first and second conductors each cooperating with the effective electrode region of said third conductor and the volume of gas therebetween to define respective first and second discharge sub sites; said first and second conductors being conductively isolated from each other and each so spaced from the effective electrode region of said third conductor as to be adapted to maintain an on state of discharge between either of said first and second conductors and said third conductor and to maintain an off state of discharge between both of said first and second conductors and said third conductor respectively when a periodically alternating sustaining voltage is imposed between said third conductor and both of said first and second conductors; and said first and second conductors being so spaced from each other in their portions 17 proximate the effective electroderegiori of .said third conductor as to be adapted to initiate an .on state of discharge in a discharge sub site including one of said first and second conductors which is in an off state 'ofdischarge in response to an on state of discharge in the discharge sub site of the other ofzsaidfirst and'second conductors. I

2. A gas discharge device according to claim 1 iricluding dielectric layers separatingeach of said conductors from said gas volume. I j T 3. A gas discharge device according to claim ljineluding a first dielectric member having a surface supporting said first and second conductors; and a second dielectric member having a surface supporting said third conductor. a v a 4. A gas discharge device according to claim 1 including a dielectric member having a surface supporting at least one of said conductors; a dielectric layer overlying said one conductor; said dielectric layer having a cavity proximate to said one conductor to define by the walls thereof a portion of said volume of ionizable gas; at least one of said conductors being supported on said dielectric layer and being adjacent said cavity whereby said first and second conductor discharge sub sites include a portion of the gas volume within said cavity.

5. A gas discharge device according to claim 1 wherein said first and second conductor have a spacing in the proximate portions which are proximate said third conductor at least great enough such that an on state of discharge is maintained in the sub site between either of said first and second conductors and said third conductor in response to the transfer from an on state to an off state of the other sub site between said first and second conductors and said third conductor.

6. A gas discharge display/memory device comprising a first and second conductor having surfaces lying in a common surface; said first and second conductors having closely spaced, non-intersecting proximate porare subjected to a sustaining voltage causes a discharge in the other sub site; dielectric layers on said proximate portions of said conductors; and means confining a volume of ionizable gas between said dielectric layers on said proximate portions of said conductors.

7. A device according to claim 6 including a dielec tric member having a first major surface defining said common surface and supporting said first and second conductors and having a depression between said first and second conductors, said dielectric member having a second major surface generally parallel to said common surface and supporting said third conductor in registry through the thickness of said member with said depression; said depression encompassing at least a portion of each of said first and second discharge sub sites and including at least a portion of said volume of ionizable gas.

8. A device according to claim 6 including a first dielectric member having a first major surface defining said common surface and supporting said first and second conductors, a second dielectric member having a ,major surfacespaced across said gas volume from said conductors having surfaces lying in a common surface;

aset of second conductors having surfaces lying insaid common surface, each second conductor of a set being (1) paired with, (2) electrically isolated from and (3) having a portion closely spaced to a portion of a respective conductor of said set of first conductors; first meansfor electrical connection to conductors of said first set; second means for electrical connection to conductors of said second set electrically isolated from said first connection means; a second conductor array juxtaposed and spaced from said first conductor array and cooperating therewith to form paired discharge-sub sites between itsindividual conductors and the closely spaced portions'of the conductors of said first and second conductor 'sets, the spacing of paired sub sites defined by conductors of said second array and the closely spaced portions of the paired conductors of said first conductor array being such that a discharge in one sub site of a pair causes a discharge in the other sub site of said pair without causing discharges in sub sites of other pairs while said conductive arrays have a sustaining voltage imposed between them; dielectric layers on proximate faces of said respective conductors in their regions of proximity to each other; a volume of ionizable gas between said dielectric layers on proximate faces of said conductors; and means to enclose said gas volume.

10. A display/memory device as defined in claim 9 including first and second spaced dielectric members respectively supporting said first and second arrays.

11. A display/memory device as defined in claim 9 including a dielectric member having two opposed major faces separated by a thickness; wherein said first array is mounted on one major face of said dielectric member, said second array is mounted on the second major face of said dielectric member, and said dielectric member has cavities in a major face juxtaposed adjacent to conductors of each pair of discharge sub sites, walls of said cavities comprising a portion of said gas enclosing means.

12. A display/memory device according to claim 11 wherein said cavities are in the major face of said dielectric member upon which is mounted said first array.

13. A display/memory device according to claim 12 wherein said cavities are between first and second paired conductors.

14. A display/memory device according to claim 9 wherein said second array of conductors comprises a plurality of sets of conductors with an individual conductor from each set being grouped, being electrically isolated from each other, and having portions proximate to each other which are also proximate closely spaced portions of conductors of the first array arranged so that each of a plurality of cells are comprised of proximate portions of paired first and second conductors of said first array and proximate portions of grouped conductors of individual sets of said second wherein said conductors of said first array are straight,

parallel strips; and wherein said conductors of said second array are straight, parallel strips orthogonally related to the conductors of said first array.

17. A display/memory device according to claim 12 wherein said conductors of said first array are straight,

parallel strips; and wherein said cavities are straight grooves centered between paired conductors of said first and second sets.

18. A display/memory device according to claim 11 wherein said cavities are individual to each group of said sub sites which are spaced such that a discharge in 20 one sub site causes a discharge in the remainder of the sub sites of the group.

19. A display/memory device according to claim 14 including a dielectric member having two opposed major faces separated by a thickness, wherein said first array is mounted on one major face of said dielectric member, said second array is mounted on the second major face of said dielectric member, and said dielectric member has cavities individual to each group of said sub sites which are spaced such that a discharge in one sub site causes a discharge in the remainder of the sub sites of the group, said cavities being in a major face of said dielectric member adjacent to conductors of said group of sub sites and having walls comprising a portion of said gas enclosing means.

20. A display/memory device according to claim 19 wherein each of said cavities extend through said dielectric member between paired conductors of said first array and grouped conductors of said second ar-

Claims

1. A gas discharge display/memory device comprising a first and a second conductor having proximate portions, said first and said second conductors being spaced and non-intersecting; a third conductor having an effective electrode region proximate each of the proximate portions of said first and second conductors; a volume of ionizable gas between said first and second conductor proximate portions and said the third conductor effective electrode region; a dielectric layer between said gas volume and at least one of said conductors; an enclosure for said gas volume; said proximate portions of each of said first and second conductors each cooperating with the effective electrode region of said third conductor and the volume of gas therebetween to define respective first and second discharge sub sites; said first and second conductors being conductively isolated from each other anD each so spaced from the effective electrode region of said third conductor as to be adapted to maintain an on state of discharge between either of said first and second conductors and said third conductor and to maintain an off state of discharge between both of said first and second conductors and said third conductor respectively when a periodically alternating sustaining voltage is imposed between said third conductor and both of said first and second conductors; and said first and second conductors being so spaced from each other in their portions proximate the effective electrode region of said third conductor as to be adapted to initiate an on state of discharge in a discharge sub site including one of said first and second conductors which is in an off state of discharge in response to an on state of discharge in the discharge sub site of the other of said first and second conductors.

2. A gas discharge device according to claim 1 including dielectric layers separating each of said conductors from said gas volume.

3. A gas discharge device according to claim 1 including a first dielectric member having a surface supporting said first and second conductors; and a second dielectric member having a surface supporting said third conductor.

4. A gas discharge device according to claim 1 including a dielectric member having a surface supporting at least one of said conductors; a dielectric layer overlying said one conductor; said dielectric layer having a cavity proximate to said one conductor to define by the walls thereof a portion of said volume of ionizable gas; at least one of said conductors being supported on said dielectric layer and being adjacent said cavity whereby said first and second conductor discharge sub sites include a portion of the gas volume within said cavity.

6. A gas discharge display/memory device comprising a first and second conductor having surfaces lying in a common surface; said first and second conductors having closely spaced, non-intersecting proximate portions which are conductively isolated from each other; independent electrical connections to said first and second conductors; a third conductor juxtaposed and spaced from said first and second conductors and cooperating therewith to form first and second gas discharge sub sites between said third conductor and each of said first and second conductors respectively, the spacing of said first and second discharge sub sites being such that a discharge in one of said sub sites while said sub sites are subjected to a sustaining voltage causes a discharge in the other sub site; dielectric layers on said proximate portions of said conductors; and means confining a volume of ionizable gas between said dielectric layers on said proximate portions of said conductors.

7. A device according to claim 6 including a dielectric member having a first major surface defining said common surface and supporting said first and second conductors and having a depression between said first and second conductors, said dielectric member having a second major surface generally parallel to said common surface and supporting said third conductor in registry through the thickness of said member with said depression; said depression encompassing at least a portion of each of said first and second discharge sub sites and including at least a portion of said volume of ionizable gas.

8. A device according to claim 6 including a first dielectric member having a first major surface defining said common surface and supporting said first and second conductors; a second dielectric member having a major surface spaced across said gas volume from said first major surface of said first dielectric member and supporting said third conductor.

9. A gas discharge display/memory device comprising, a first conductor array constituted by a set of first conductors having surfaces lying in a common surface; a set of second conductors having surfaces lying in said common surface, each second conductor of a set being (1) paired with, (2) electrically isolated from and (3) having a portion closely spaced to a portion of a respective conductor of said set of first conductors; first means for electrical connection to conductors of said first set; second means for electrical connection to conductors of said second set electrically isolated from said first connection means; a second conductor array juxtaposed and spaced from said first conductor array and cooperating therewith to form paired discharge sub sites between its individual conductors and the closely spaced portions of the conductors of said first and second conductor sets, the spacing of paired sub sites defined by conductors of said second array and the closely spaced portions of the paired conductors of said first conductor array being such that a discharge in one sub site of a pair causes a discharge in the other sub site of said pair without causing discharges in sub sites of other pairs while said conductive arrays have a sustaining voltage imposed between them; dielectric layers on proximate faces of said respective conductors in their regions of proximity to each other; a volume of ionizable gas between said dielectric layers on proximate faces of said conductors; and means to enclose said gas volume.

14. A display/memory device according to claim 9 wherein said second array of conductors comprises a plurality of sets of conductors with an individual conductor from each set being grouped, being electrically isolated from each other, and having portions proximate to each other which are also proximate closely spaced portions of conductors of the first array arranged so that each of a plurality of cells are comprised of proximate portions of paired first and second conductors of said first array and proximate portions of grouped conductors of individual sets of said second array spatially arranged so that the presence of a discharge between one of said first and second conductors of a pair and one of said conductors of a group initiates a discharge between all other of said first and second conductors of said pair and all other conductors of said group; and means for electrical connection to conductors of individual groups of conductors of said second array.

15. A display/memory device according to claim 14 including first and second spaced dielectric members respectively supporting said first and second arrays.

16. A display/memory device according to claim 9 wherein said conductors of said first array are straight, parallel strips; and wherein said conductors of said second array are straight, parallel stripS orthogonally related to the conductors of said first array.

17. A display/memory device according to claim 12 wherein said conductors of said first array are straight, parallel strips; and wherein said cavities are straight grooves centered between paired conductors of said first and second sets.

18. A display/memory device according to claim 11 wherein said cavities are individual to each group of said sub sites which are spaced such that a discharge in one sub site causes a discharge in the remainder of the sub sites of the group.

20. A display/memory device according to claim 19 wherein each of said cavities extend through said dielectric member between paired conductors of said first array and grouped conductors of said second array.