US3866221A

US3866221A - Beacon decoder system

Info

Publication number: US3866221A
Application number: US397950A
Authority: US
Inventors: Mitsuo Hikosaka
Original assignee: Individual
Current assignee: Individual
Priority date: 1972-09-18
Filing date: 1973-09-17
Publication date: 1975-02-11
Anticipated expiration: 1992-02-11
Also published as: JPS4950889A; JPS591987B2

Abstract

A decoder system useful in a radar beacon system for facilitating discrimination between reply signals occurring in near time coincidence. For each pair of framing pulses appearing at the ends of a delay line, an AND gate sends a strobe pulse to a plurality of NAND gates to thereby read out data pulses occurring between the framing pulses into a register for temporary storage. The register is adapted to accept or reject the data pulses dependent upon whether they have a width equal to that of their associated strobe pulse. The data bits thus stored in the register are transferred into other suitable code registers in controlled sequence. The disclosed beacon decoder is also capable of detecting the condition of at least two reply signals overlapping in time so that some of their data-pulse positions occur in exact time coincidence. Even in such overlapping condition, the decoder can derive range information from the reply signals while preventing readout of incorrect code information.

Description

United States Patent [191 Hikosaka Feb. 11, 1975 BEACON DECODER SYSTEM [57] ABSTRACT Inventor: Mnsuo Hikosakai 159048 Kokura, A decoder system useful in a radar beacon system for Kasllga, Japan facilitating discrimination between reply signals occur- [22] Filed: Sept 17, 1973 ring in near time coincidence. For each pair of framing pulses appearing at the ends of a delay line. an PP 397,950 AND gate sends a strobe pulse to a plurality of NAND gates to thereby read out data pulses occurring be- [301 Forelgn Apphcatlon Pnomy Data tween the framing pulses into a register for temporary Sept, 18, 1972 Japan i t 47-950) storage The register is p d to accept or reject h data pulses dependent upon whether they have a Width equal to that of their associated strobe pulse. [58] Field of sar ch uju jljfs"1. 3 43/65 LC, 6.8 LC T data bits are transferred into other suitable code registers in controlled se- [56] References Cited quence. The disclosed beacon decoder is also capable of detecting the condition of at least two reply signals UNITED STATES PATENTS overlapping in time so that some of their data-pulse 3.l56,895 ll/l964 Fiske etali 343/65 L positions occur in exact time coincidence. Even in 35123470 5/1970 wmnvm e 343/6-8 LC such overlapping condition, the decoder can derive range information from the reply signals while pre- 3:718:92o 2/1973 Parker et al 343/68 LC Vemmg readout Ofmcorrect Code mformat'on' Primary ExaminerMalcolm F. Hubler Attorney, Agent, or FirmEdwin E. Greigg 20 Claims, 9 Drawing Figures TT 0T 80 SEC ND ITOANDGATLBB 24 co ROL 2 56 FIRST 0T CONTROL m 62 cmcun RESET 5!;

so ml SIGNAL i REPLY SIGNAL 25 27 gg gg 2 68] 741 25 2 a l3 l:l D SIGNAL PROCESSING I E r i I 2 AND DISPLAY l I i 2 E i i 1 27m 68M 5 n-l a REGISTER QEAR SIG -SECONDCODE REGISTER n- RESET SIG Elllil 94 :D f SIGNAL PROCESSING m mu DISPLAY P/XIENTEU 1 3,866,221

SHEEIF3 'AI 29 30 A J, L 2 (u) -A M Lind H12i3i{ H I l 8| :1 1 '5 H6] (b) B ML TT m 78 SECOND '.m AND GATE,88

CONTROL T 24 FIRST m CIRCUIT 2 g CONTROL m 1 e2 58 60 ml SIGNAL l REPLY FIRST c005 m SIGNAL 25! REGISTER H JM 252 2 682: SIGNAL PROCESSING I i r 5 2 AND DISPLAY z 3 1' i 1' E 5 if I R 22 7D I -P. 25 66M n-l CLEAR s|e REGISTER SECOND CODE REGISTER as TT| I 2 1mm) EL SIG 84 I $3531? 94 CLEARS'G' & 902 SIGNAL PROCESSING m I AND DISPLAY 2 2 z 1' I FIG 2 5 5 PATEMEUFEBI H975 TO AND GATE, ee

FROM NAND GATE,25| 32] I MAIN FLIP FLIP, 34

FROM AND i GATE,24 50 STROBE (k) FOURTH GATE SIGNAL n PULSE P5??? IIII SE DATA PULSE I F DATA PULSE II DATA PULSE NANDGATE,40 NANDGATEAO U NAND GATE,40 U IIII FLO M f a -FLOP, l I LII -Fmw i IIII -FLOP, 42 I III -FLOA; 42 -FLOR 42 i NAND GATE,48 NAND GATE,48 F53 NAND GATE,48 F54 HG.4(0) FlG.4(b) Y HG.4(cI

(a) CLOCK PULSE I I I I I I I I I I (b) STROBE PULSE m (c) FIRST GATE SIGNAL m T j I (d) sacown GATE SIGNAL [5T L I I (e) THIRD GATE SIGNAL on F1 (r) FOURTH GATE SIGNAL 0T2 W II H65 (9) STROBE PULSE PE (h) FIRST GATE SIGNAL n A L J (i) SECOND GATE sIGNALfi L I (j) THIRD GATE SIGNAL TT| I BEACON DECODER SYSTEM BACKGROUND OF THE INVENTION This invention relates generally to radar beacon systems and, more particularly, to a beacon decoder subsystem for use therein for facilitating discrimination be tween reply signals occurring in near time coincidence.

Radar beacon systems are useful for the control of civilian air traffic in the vicinity of airports. In this sys tem, an interrogating transmitter at a fixed ground station periodically transmits an interrogating signal which is detected by transponders located on board targets, i.e., aircraft within the range of the ground station. Upon receiving the interrogating signal, the transponders automatically reply with a coded pulse train which is received back at the interrogator receiver. The coded reply is normally comprised of first and second framing pulses having a fixed time separation, and between these fwo framing pulses are defined a plurality of equally spaced data-pulse positions. Various information such as aircraft identity, altitude, emergency, etc. is represented by the occurrence or non-occurrence of pulses in pre-assigned positions.

Heretofore, various types of decoders have been proposed for decoding reply signals from transponders. Generally, such devices employ a delay line with its time delay equal to the time interval between first and second framing pulses. The delay line is also tapped at equal intervals to convert a reply signal from serial to parallel form. In decoders of this type, readout of data pulses is accomplished through the parallel output of the delay line in response to the first and second framing pulses appearing simultaneously at the ends of the delay line. If, however, reply signals from several transponders arrive almost simultaneously at a single interrogator receiver, there is likely to be overlap in the data-pulse positions of the signals, resulting in misinterpretations. In order to prevent undesired misinterpretation of reply signals, some prior art systems employ two delay lines by which to accept or reject reply signals dependent upon whether they are in overlapping relationship. However, this technique is prone to unwanted rejection, causing loss of replies.

OBJECTS AND SUMMARY OF THE INVENTION It is, therefore, a general object of the present invention to provide an improved beacon decoder system with a view to overcoming the above-stated disadvantages of the prior art systems.

It is a more particular object of the present invention to provide an improved beacon decoder system which functions to accept or reject data pulses dependent upon whether or not they have a width equal to a strobe pulse so as to selectively store correct data pulses in a register.

Another object of the present invention is to provide an improved beacon decoder system which is capable of deriving range information from reply signals while preventing readout of incorrect code information even if those reply signals overlap in time with each other so that some of their data-pulse positions occur in exact time coincidence.

These and other objects of the invention are achieved by providing a novel decoder unit or subsystem in a radar beacon system. More particularly, in a preferred embodiment of the present invention, a strobe pulse is derived by the use of an AND gate in response to each pair of framing pulses appearing at the ends of a delay line. The strobe pulse is supplied to a plurality of NAND gates to read out the data pulses into a register for temporary storage. The register is adapted to compare the width of each data pulse with that of the strobe pulse so as to selectively store correct data pulses having the same width as their associated strobe'pulse. The data bits thus stored in the register are transferred into other suitable code registers in controlled sequence. The present beacon decoder is also capable of detecting the condition of at least two reply signals overlapping in time so that some of their data-pulse positions occur in exact time coincidence. Even in such overlapping condition, the decoder system can derive range information from the reply signals while preventing readout of incorrect code information.

The novel features that are considered characteristics of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a waveform diagram illustrating two reply signals occurring in near time coincidence;

FIG. 2 is an overall block diagram illustrating a beacon decoder system according to one preferred embodiment of the present invention;

FIG. 3 is a diagram of a logic circuit forming part of a register shown in FIG. 2;

FIGS. 4 (a), (b) and (c) are waveform diagrams illustrating the manner of accepting or rejecting data pulses dependent upon whether they have a width equal to a strobe pulse;

FIG. 5 is a waveform diagram useful in explaining the operation of first and second control circuits shown in FIG. 2;

FIG. 6 is a diagram of a third control circuit and a strobe signal entry logic included in the device of FIG. 2; and

FIG. 7 is a waveform diagram illustrating the manner of discriminating between two reply signals which overlap in time so that some of their data-pulse positions occur in exact time coincidence.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made to FIG. 1 of the drawings which illustrates exemplary waveforms of two transpender reply signals occurring in near time coincidence. As shown in line (a) of FIG. 1, the reply signal, as from aircraft A, is comprised of a first framing pulse, identified as A1, which is subsequently followed by a second framing pulse, identified as A2. The interval between the leading edges of the framing pulses A1 and A2 is subdivided into n time slots or bit periods, and the first of these n time slots is dedicated to the first framing pulse Al. The next n-l time slots are used for the transmission of 11-! data bits. During each of these bit periods, the transponder can transmit a pulse to represent a binary l. The non-occurrence of a pulse within a bit period represents a binary 0. Thus, as shown in line (a) of FIG. I, the first and second data bits transmitted by aircraft A during

bit periods

12 and 13 are both I. The next data bit is a 0.

Assuming the presence of aircraft B, as well as aircraft A in the vicinity ofa ground station, the transponder carried by the aircraft B will also transmit a reply signal as shown in line (b) of FIG. 1. It is to be noted that the first framing pulse B1 of the reply signal from aircraft B overlaps with the second data pulse shown in line (a) of FIG. 1. Since the reply signals from both aircraft A and B are essentially combined at a scanning antenna (not shown), it will become difficult to discriminate one reply from another.

Reference is now made to FIG. 2 which illustrates a beacon decoder system constructed in accordance with 'the teachings of the present invention. Thebeacon decoder is adapted to discriminate between reply signals received on a common input line 21. As shown, the common input line 21 is connected to a delay line 22 having a time delay equal to the time interval between first and second framing pulses. The delay line 22 is provided with n-l taps which are so spaced in time that each tap corresponds to one of the data-pulse positions defined between the first and second framing pulses. It should be noted, in this connection, that a shift register could as well be employed in place of the delay line. An AND gate 24 has two inputs connected to the respective ends of delay line 22 in order to derive a single pulse (hereinafter referred to as a strobe pulse) for each pair of framing pulses. The output taps of delay line 22 are respectively connected to one input ofa plurality of

NAND gates

25,, 25 25 and the other inputs of these NAND gates 25 are connected together to the output of AND gate 24. In response to each pair of first and second framing pulses appearing simultaneously at the ends of delay line 22, a strobe pulse is applied at the other inputs of NAND gates 25 to read out in parallel data pulses occurring between the first and second framing pulses into a register 27 for temporary storage. As will be apparent, the register 27 is arranged so that it accepts correct data pulses, but rejects false or spurious data pulses as exemplified by the dotted lines 29 and 30 in line (a) of FIG. 1, which would otherwise be erroneously interpretted as forming part of the reply signal from aircraft A. The register 27 comprises n-l data bins each associated with one of the data-pulse positions defined between the first and second framing pulses.

Reference is now made to FIG. 3 which illustrates a typicalexample of the first data bin of register 27.

A data pulse passed through NAND gate 25 (see FIG. 2) is supplied through a line 32 to the set input of an asynchronous flip-flop 34 (hereinafter referred to as a main flip-flop), the flip-flop comprising

NAND gates

36 and 38. The data pulse is also fed to one input of a NAND gate 40 by way of a line 41. The other input of NAND gate 40 is connected to the output of AND gate 24 (see also FIG. 2) so as to be supplied with a strobe signal therefrom. The output of NAND gate 40 is connected to the set' input of another asynchronous flipflop 42 (hereinafter referred to as an auxiliary flip-flop) which comprises

NAND gate

44 and 46. The set output of auxiliary flip-flop 42 is connected to one input of a NAND gate 48, and the output thereof is connected to the reset inputs of main and auxiliary flip-

flops

34 and 42. Applied at the other input of NAND gate 48 is a strobe signal in inverted form which is supplied through 21 NOT gate 50 from AND gate 24.

For a better understanding of the operation of the first data bin, a timing diagram is shown in FIGS. 4 (a),

(b) and (c). By way of example, let it be assumed that a data pulse 52 supplied from delay line 22 to the particular data bin has a duration or width equal to that of a strobe pulse, as is shown in FIG. 4(a). The main flip- 5 flop 34 is set upon detection of the leading edge of the data pulse 52. Since, in this case, the NAND gate 40 is not enabled, it will fail to set the auxiliary flip-flop 42 and then to enable the NAND gate 48. Thus, the output of main flip-flop 34 remains true, which means that the data pulse is stored in the particular data bin.

If on the other hand, a data pulse has a width less than that ofa strobe pulse, as shown in FIGS. 4 (b) and (c), then the NAND gate 40 is 'enabled providing a false output. The false output will switch the auxiliary flip-flop 42 true. Thus, the NAND gate 48 is enabled upon recognition of the trailing edge of the strobe pulse and provides a false output, identified as 53 and 54, which is supplied to the main and auxiliary flip-

flops

34 and 42 to reset the same.

As will be appreciated by those familiar with the art, in decoders of the type in which a delay line is utilized to derive data pulses from a reply signal, correct data pulses can be recognized only when they have a duration or width equal to that of their associated strobe pulses, except in the case where two or more reply signals overlap with each other so that some or all of their data-pulse positions occur in exact time coincidence, as is shown in FIGS. 7 (a) and ([2). Thus, it should be understood that with the arrangement shown in FIG. 3 it is possible to derive only correct data pulses from a reply signal except in the particular case indicated above.

Reference is made again to FIG. 2. A strobe pulse derived for each pair of framing pulses is supplied also to a pulse-width discriminator 56 which is connected to one input of an AND gate 58. In order to suppress noise or other spurious effects, the pulse-width discriminator 56 prevents spurious strobe pulses from passing to a first control circuit 60 which is connected to the output of AND gate 58. More particularly, the pulse-width discriminator 56 permits passage of only such strobe pulses having a width falling within it 0.1 p. sec, for example. It is understood, in this connection, that the pulse-width discriminator can be omitted in some installations. The first control circuit 60 produces four different gate signals in response to each strobe pulse.

Attention is now called to FIG. 5 which illustrates exemplary waveforms of the gate signals produced by the first control circuit 60 and a second control circuit 62 to be described later. Line (a) of FIG. 5 illustrates clock pulses, and line (b) of that figure shows a strobe pulse SP which results from the framing pulses of a reply signal from aircraft A. In response to the strobe pulse SP the first control circuit 60 produces a firt gate signal DT shown in line (0) of FIG. 5. The first gate signal DT is true for a duration T equal to the fixed time interval between first and second framing pulses after the trailing edge of the strobe pulse SP As will be described later, the first gate signal is used to gate a second strobe pulse SP shown in line (g) of FIG. 5, which results from the reply signal from aircraft B occurring in near time coincidence with that from aircraiA. Line (d) of FIG. 5 illustrates a second gate signal DT which is an inverted signal of the first gate signal DT. The second gate signal DT is supplied to the other input of AND gate 58 (see FIG. 2) to inhibit the second. third, fourth strobe pulses from entering the first control circuit 60 for the duration T. A third gate signal DT, is true for one clock-pulse repetition period after the first strobe signal SP as is shown in line (e) of FIG. 5. Also, a fourth gate signal DTglS true for one clock-pulse repetition period before the end of duration T of the first gate signal DT, as is shown in line U) of FIG. 5. These third and fourth gate signals DT and DT are used to successively transfer date bits stored in the register 27, as will be described below.

As seen in FIG. 2, the output of each data bin of register 27 is connected through an AND gate 66 to a first code register 68. The first code register 68 is also of the type capable of storing data bits in parallel and comprises n-l data bins each associated with one of the data-pulse positions. The AND gates 66, 66,,., are connected together to an AND gate 70 which in turn is connected to the first control circuit 60 so as to be supplied with the third gate signal DT, therefrom. The function of AND gate 70 will be described later in detail. Thus, as will be understood, the data bits stored in register 27 are transferred in parallel into the firs t code register 68 in response to the third gate signal DT In order to further transfer the data bits stored in first code register 68, the fourth gate signal DT is supplied through a line 72 to a plurality of AND gates 74,, 74 74,, each of which is connected to the output of each data bin of first code register 68. The date bits thus transferred, together with the fourth gate signal DT are supplied to a suitable circuitry (not shown) for further processing and/or display. It will be appreciated that the fourth gate signal DT is utilized as an ordinary radar echo to determine range.

With continued reference to FIG. 2, the second strobe pulse SP (see also FIG. 5) is passed through a line 76 to an AND gate 78 where it is gated in response to the first gate signal DT from the first control circuit 60. The second strobe pulse SP is then supplied through an AND gate 80 to the second control circuit 62 to activate the same. When activated, the second control circuit 62 produces the same set of gate signals as those generated by the first control circuit 60, as is shown in FIG. 5. A first gate signal, identified as TT, may be used to gate a third strobe pulse, although not specifically shown. A second gate signal, identified as TT, is supplied to the input of AND gate 80 to inhibit the third strobe signal from entering the second control circuit 62 during a duration T equal to the time interval between first and second framing pulses after the second strobe pulse ST Third and fourth gate signals, identified respectively as TT and TT are used to suecessively transfer the data pulses of a second occurring reply signal, i.e., those from aircraft B as in the case of FIG. 1.

As seen in FIG. 2, the output of each data bin of register 27 is also connected through another AND gate 84 to a second code register 86 which is of the same type as the first code register 68. Each AND

gate

84,, 84 84,, is connected together to an AND gate 88 which in turn in connected to the output of second control circuit 62 to receive the third gate signal TT, therefrom. Also, the parallel outputs of second code register 86 are connected to one inputs of a plurality of AND gates 90,, 90 90,,.,. Thus. as will be apparent, the third gate signal TT, is supplied from second control circuit 62 to each of the AND gates 84 to transfer data bits stored in the register 27 into the second code register 86 for temporary storage.

Also, in response to the fourth gate signal TT appearing at the AND gates 90, the data bits stored in the second code register 86 are transferred to a suitable circuitry (not shown) for further processing. The fourth gate signal TT is also supplied to the circuitry to serve as a radar echo to determine the range between the ground station and the aircraft B.

With reference to FIG. 2, it is to be noted that, in addition to the third gate signilT the AND gate 88 receives the inverted signal DT, of the third gate signal DT, produced by the first control circuit 60. Also, it should be noted that at o n e input of AND gate is applied the inverted signal TT, of the third gate signal TT produced by the second control circuit 62. These inverted signals are utilized to ensure readout of data bits stored in the register 27 into the two different code registers 68 and 86 in the case where two reply signals occur in such near time coincidence that the third gate signals produced by their associated strobe pulses overlap.

Shown in the lower left-hand portion of FIG. 2 is a third control circuit 94 which functions to recognize a certain garbling situation and to prevent an incorrect code readout during such a situation. By the certain garbling situation, it is meant that two or more reply signals are received by a particular decoder in such a time relationship that they overlap with each other with some or all of their data-pulse positions occurring in exact time coincidence, as is shown in FIGS. 7 (a) and (b). As will become clear hereinafter, the present beacon decoder is capable of deriving range information from reply signals while inhibiting readout of incorrect code information, even in the certain garbling situations.

Reference is now made to FIG. 6 which illustrates a block diagram of the third control circuit 94 which comprises a delay line 96 for recognizing the certain garbling situations. Similar to the delay line 22 (see FIG. 2), the delay line 96 has a time delay equal to the time interval between first and second framing pulses and is also provided with n-l taps equally spaced in time thercbetween. The input of delay line 96 is connected to the output of AND gate 24 to receive strobe pulses therefrom, as is best shown in FIG. 2. Each output tap of delay line 96 is connected to one input of an OR gate 98, and the output thereof is connected to one input of an AND gate 100. The other input of AND gate 100 is connected to the input terminal of delay line 96 through a line 102. A pulse-width discriminator 104 is connected to the output of AND gate 100 so as to inhibit such strobe pulses having a width less than I 0.1 ,a sec, for example, from passing to a control signal generator 106. However, the pulse-width discriminator may be omitted, if desired.

The operation of third control circuit 106 will be described below in detail with reference to FIG. 7. Lines (a) and'(b) of FIG. 7 illustrate exemplary waveforms of two reply signals from aircraft A and B, which overlap with each other so that some of their data-pulse positions occur in exact time coincidence, representing a typical certain garbling situation as defined above. As the time I, when the reply signal from aircraft A appears on the delay line 22 (see FIG. 2), the framing pulses A and A enable the AND gate 24 to produce a strobe pulse SP shown in line (d) of FIG. 7. Under the abovedescribed garbling situation, since the spacing between the first data pulse 110 of the reply signal from aircraft A and the penultimate data pulse 112 of the reply signal from aircraft B is exactly the same as the fixed time interval first and second framing pulses, a spurious strobe pulse, identified as SP is derived from the AND gate 24 (see FIG. 2). Similarly, another spurious strobe pulse SP is derived for a pair of the second data pulse 114 of the reply signal from aircraft A and the last data pulse 116 of the reply signal from aircraft B. A strobe pulse, identified as SP is a real or true strobe pulse derived for the framing pulses B and B of the reply signal from aircraft B. Since these strobe pulses are mutually spaced by an integer multiple of the spacing between two adjacent output taps of delay line 96, the AND gate 100 of third control circuit 94 is enabled in response to each strobe pulse except for the first true strobe pulse SP providing an output signal as shown in line (e) of FIG. 7. The output of AND gate I enables the control signal generator 106 to produce. a reset signal RS and a clear signal CS, as shown in lines (1) and (g) of FIG. 7, respectively. The clear signal CS will be true until it is reset in response to the fourth gate signal DT from first control circuit 60 (see FIG. 6). In order to eliminate incorrect data bits stored in the first and second code registers 68 and 86, the clear signal CS is appliedto those coderegisters. As shown in line (I) of FIG. 7, the reset signal RS is comprised of three pulses R5,, RS and RS each of which is produced in response to one pulse from AND gate 100. These reset pulses are supplied to the second control circuit 62 to reset the same for the purpose which will be apparent hereinafter.

In FIG. 6, there is shown a strobe signal entry logic 120, the function of which is to repeatedly reset the second control circuit 62 until it is set in response to the second true or real strobe pulse SP,,. As shown, the signal entry circuit 120 includes an AND gate 122 which corresponds to the AND gate 80 shown in FIG. 2. That is, the AND gate 122 receives the second gate signal TT from the second control circuit 62 to permit passage of only the second strobe pulse, irrespective of whether the strobe pulse is a true one or a spurious one. The output of AND gate 122 is supplied to the second control circuit 62 through an OR gate 124. An AND gate 126 is provided to permit passage of only the third, fourth, strobe pulses occurring in the certain garbling situation. The AND gate 126 has three input terminals, one of which is connected to the output of AND gate 78 (seeFIG. 2) to receive strobe pulses therefrom, and another of which is connected to the output of second control circuit 62 so as to be supplied with the first gate signal TT therefrom. Applied at the remaining output of AND gate 126 is the reset signal RS.

The manner in which the second control circuit 62 is repeatedly reset until it is set by the second true or real strobe pulse SP will be explained hereinafter in conjunction with FIG. 7. As seen in line (d) of FIG. 7, the first true or real strobe pulse SP enters the first control circuit 60 (see FIG. 2), and the first spurious strobe pulse SP is permitted to pass through AND

gates

78 and 122 into second control circuit 62. The strobe pulse SP sets the second control circuit 62, causinglt to produce the first and second gate signals TT and TT, respectively. As a result, the se cond spurious strobe pulse SP is prohibited by the TT signal from passing through AND gate 122. On the contrary, the strobe signal SP is permitted to pass through AND gate 126 into the second control circuit 62 because of the coincidence of the signal SP with the first gate signal TT and the second reset pulse R5,. The second reset pulse RS is produced by the control signal generator 106 (see FIG. 6) in response to the strobe signal SP The reset pulse RS is also supplied to the second control circuit 62 to reset the same. It should be noted, in this connection, that the second control circuit 62 is designed so that it is reset in response to each reset pulse RS, but it is also capable of being set to produce a set of gate signals by the very strobe signal that has caused the particular reset pulse to be generated. More particularly, by way of example, the second control circuit includes input means capable of remaining in its set condition without responding to a reset signal for a certain period, e.g., until the detection of the next clock pulse, and counter means to which a reset signal is applied to reset the same.

Thus, as will be understood, the second control circuit 62 is reset upon detection of the second reset pulse RS and immediately thereafter is set by the second spurious strobe signal SP i.e., the very strobe signal which has enabled the control signal generator 106 to vproduce the second reset signal RS It should be appreciated that under the certain garbling situation this operation of the second control circuit 62 repeats itself until it is set by a second occurring, true or real strobe signal, i.e., the strobe pulse SP in the case of FIG. 7. When the second control circuit 62 is set by the second true or real strobe signal SP it produces a fourth gate signal TT which will provide range information on aircraft B. Thus, it should be understood that even in the certain garbling situation the present beacon decoder is capable of deriving range information from reply signals while eliminating incorrect code information.

While a description of the present invention has been made with the particular embodiment capable of discriminating two different reply signals which occur in near time coincidence, it will be obvious to those skilled in the art that by the connection of a desired number of control circuits in cascade with the arrangement shown in FIG. 2, it can be adapted to such a garbling situation that more than two reply signals arrive in near time coincidence.

Further, it will be appreciated that an additional pulse discriminator may be provided for detecting spurious strobe pulses having a width falling outside of I i l ,u. see, for example, in order to produce a reset pulse for each spurious strobe pulse to thereby reset the first and second control circuits which have been set by those spurious strobe pulses.

From the foregoing, it should be appreciated that in accordance with the teachings of the present invention, an improved beacon decoder system is provided for discriminating between reply signals which overlap in time with each other. Further, it should be understood that even in the certain garbling situation where two or more reply signals overlap so that some of their datapulse positions occur in exact time coincidence, the present beacon decoder system can successfully derive range information from the reply signals while inhibiting readout of incorrect code information.

Although particular embodiments of the present invention have been shown and described, it is recognized that modifications and variations may readily occur to those skilled in the art and, accordingly, it is intended that the claims be i'nterpretted to cover such modifications and equivalents.

What is claimed is:

1. A decoder system for use in a communication system of the character in which the format of a signal is comprised of a first and second framing pulses spaced in time by a fixed interval, said signal format additionally containing a plurality of data bits represented by the presence and absence of pulses, each occurring during a corresponding timeslot of a sequence of such time slots defined between said first and second framing pulses, said decoder system being useful in discriminating between signals occurring in near time coincidence and comprising:

converter means for converting said signals from serial to parallel form, said converter means having a plurality of output taps each associated with one of said data bits provided between said framing pulses;

coincidence means, connected to said converter means to detect the coincidence of the first and second framing pulses of each signal and connected to produce a coincidence signal when such coincidence is detected;

a plurality of gating means, each connected to one of said converter means output taps, said gating means being responsive to said coincidence signal to read out said data pulses from said converter means; and

memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether it has a width equal to that of said coincidence signal.

2. A system as defined in claim 1, further comprising:

a plurality of control means, each associated with one of said signals, each of said control means being responsive to only its associated coincidence signal for producing a transfer signal;

a plurality of groups of gating means, each of said gating means in each group being connected to one of said memory means data bins and connected together to its associated control means to read out said data bits from said memory means in response to said transfer signal; and plurality of code memory means, each comprising a plurality of data bins, each of said data bins being connected to its associated gating means to receive said data bit from said memory means.

3. A system as defined in claim 2, further comprising:

detecting means, connected to said coincidence means to detect the condition of at least two signals overlapping in time so that some of their time slots occur in exact time coincidence; and

clear signal generating means, connected to said detecting means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.

4. A system as defined in claim 3, further comprising:

reset signal generating means, connected to said detecting means to generate a reset signal in response to the occurrence of said overlapping condition;

said control means being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.

5. A decoder system useful in a radar beacon system for discriminating between reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses .spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising:

delay means for converting said reply signals from serial to parallel form, said delay means having a time delay equal to the fixed time interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay means;

coincidence means, connected to said delay means to detect the coincidence of the first and second framing pulses of each reply signal and connected to produce a coincidence signal when such coincidence is detected;

a plurality of gating means, each. connected to one of said delay means output taps, said gating means being responsive to said coincidence signal to read out said data pulses appearing at said output taps; and

memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse from said delay means with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.

6. A system as defined in claim 5, in which each of said memory means data bins comprises:

a first binary storage device, connected to the output of its associated gating means to set said first binary storage device upon receipt of each data pulse;

a first gate, connected to the outputs of said associated gating means and of said coincidence means to enable said first gate when said data pulse does not have a width equal to that of said coincidence signal;

a second storage device, connected to the output of said first gate to set said storage device when said first gate is enabled; and

a second gate, connected to the outputs of said second storage device and of said coincidence means to enable said second gate when said second storage device is in its set state and the trailing edge of said coincidence signal is detected, the output of said second gate being connected to said first and second storage devices to reset the same in response to said second gate being enabled.

7. A system as defined in claim 5., further comprising:

a plurality of control circuits, each associated with one of said reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal;

a plurality of groups of gating means, each of said gating means in everygroup being connected to one of said memory means data bins and connected together to its associated control circuit to read out the data bit stored in said memory means in response to said transfer signal; and

a plurality of code memory means, each comprising a plurality of data bins, each of said code memory data bins being connected to its associated gating means to receive the data bit from said memory means in response to said transfer signal.

8. A system as defined in claim 7, in which each of said control circuits is responsive to its associated coincidence signal to produce another transfer signal;

a plurality of groups of another gating means, each of said another gating means in every group being connected to one of said data bins of its associated code memory means and connected together to its associated control circuit toread out the data bit stored in its associated code memory means in response to said another transfer signal.

9. A system as defined in claim 8, in which said another transfer signal is utilized as a radar echo to determine range.

10. A system as defined in claim 7, further comprising:

detecting means, connected to said coincidence means to detect the condition of at least two reply signals overlapping in time so that some of their time slots occur in exact time coincidence; and

clear signal generating means, connected to said coincidence means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.

11. A system as defined in claim 10, further comprising:

said control circuits being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.

12. A decoder system useful in a radar beacon system for discussing between first and second reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality ofdata pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses,

comprising:

a delay line for converting said reply signals from serial to parallel form, said delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay line;

an AND gate, connected to said delay line to produce a coincidence signal in response to each pair of said first and second framing pulses;

a plurality of NAND gates, each connected to one of said delay line output taps to read out said data pulse from said delay line in response to said coincidence signal; and

a register having a plurality of data bins, said register including comparator means for comparing the width of each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.

13. A system as defined in claim 12, in which each of said register data bins comprises:

a main flip-flop, connected to the output of its associated NAND gate to set said main flip-flop upon receipt of each data pulse;

a first NAND gate, connected to the outputs of said associated NAND gate and of said AND gate to enable said first NAND gate when said data pulse does not have a width equal to that of said coincidence signal;

an auxiliary flip-flop, connected to the output of said first NAND gate to set said auxiliary flip-flop when said first NAND gate is enabled;

a NOT gate, connected to the output of said AND gate to invert said coincidence signal; and

a second NAND gate, connected to the outputs of said auxiliary flip-flop and of said NOT gate to enable said second NAND gate when said auxiliary flip-flop is in its set state and the trailing edge of said coincidence signal is detected, the output of said second NAND gate being connected to said main and auxiliary flip-flops to reset the same in response to said second NAND gate being enabled.

14. A system as defined in claim 12, further comprising:

first and second control circuits, each associated with one of said first and second reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal;

' first and second groups of AND gates, each of said AND gates in each group being connected to one of said register data bins and connected together to its associated control circuit to read out the data bit stored in said data bin in response to said transfer signal; and

first and second code registers, each comprising a plurality of data bins, each of said code register data bins being connected to its associated AND gate to receive the data bit from said register in response to said transfer signal.

15. A system as defined in claim 14, in which said first and second control circuits are responsive to their associated coincidence signals to produce another transfer signals;

first and second groups of another AND gates, each of said another AND gates in each group being connected to one of said data bins of its associated code register and connected together to its associated control circuit to read out the data stored in its associated code register in response to said another transfer signal.

16. A system as defined in claim 15, in which said another transfer signal is utilized as a radar echo to determine range.

17. A system as defined in claim 14, in which each of said first and second control circuits produces first and second gate signals in response to its associated coincidence signal, said first and second gate signals having a duration equal to the fixed time interval between said first and second framing pulses;

a first AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal to said first control circuit only when said second gate signal from said first control circuit is present;

a second AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal through said second AND gate only when said first gate signal from said first control circuit is present; and

a third AND gate. connected to said second AND gate and said second control circuit to permit passage of said coincidence signal to said second control circuit only when said second gate signal from said second control circuit is present.

18. A system as defined in claim 17, further comprisa fourth AND gate, connected to said first and second control circuits and also to said first group of AND gates to permit passage of said transfer signal from said first control circuit to said AND gates only when said transfer signal from said second control circuit is absent; and

a fifth AND gate, connected to said first and second control circuits and also to said second group of AND gates to permit passage of said transfer signal from said second control circuit to said AND gates only when said transfer signal from said first control circuit is absent.

19. A system as defined in claim 17, further comprising:

another delay line, connected to the output of said AND gate to receive said coincidence signals, said another delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving a sequence of said coincidence signals which occur when said first and second reply sig nals overlap in time so that some of their time slots occur in exact time coincidence;

an OR gate, connected to the output taps of said another delay line to enable said OR gate when said coincidence signal appears at any of said output taps;

a sixth AND gate, connected to the input of said another delay line and also to the output of said OR gate to enable said sixth AND gate when said overlapping condition of the first and second reply signals is present; and

means for generating a clear signal in response to said sixth AND gate being enabled, said clear signal being supplied to said first and second code registers to clear the same.

20. A system as defined in claim 19, further comprising:

means for generating a reset pulse each time said sixth AND gate is enabled; said reset pulse being supplied to said second control circuit to reset the same;

a seventh AND gate, connected to the outputs of said second AND gate, said reset pulse generating means and said second control circuit to enable said seventh AND gate in response to each of said coincidence signals except for the first and second occurring ones; and

a second OR gate, connected to the outputs of said third AND gate and of said seventh AND gate to couple said coincidence signals to said second con trol circuit when said second OR gate is enabled;

whereby said second control circuit is repeatedly reset in response to said reset pulses until it is set by the particular coincidence signal which results from the framing pulses of said second reply signal.

Claims

1. A decoder system for use in a communication system of the character in which the format of a signal is comprised of a first and second framing pulses spaced in time by a fixed interval, said signal format additionally containing a plurality of data bits represented by the presence and absence of pulses, each occurring during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, said decoder system being useful in discriminating between signals occurring in near time coincidence and comprising: converter means for converting said signals from serial to parallel form, said converter means having a plurality of output taps each associated with one of said data bits provided between said framing pulses; coincidence means, connected to said converter means to detect the coincidence of the first and second framing pulses of each signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said converter means output taps, said gating means being responsive to said coincidence signal to read out said data pulses from said converter means; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether it has a width equal to that of said coincidence signal.

2. A system as defined in claim 1, further comprising: a plurality of control means, each associated with one of said signals, each of said control means being responsive to only its associated coincidence signal for producing a transfer signal; a plurality of groups of gating means, each of said gating means in each group being connected to one of said memory means data bins and connected together to its associated control means to read out said data bits from said memory means in response to said transfer signal; and a plurality of code memory means, each comprising a plurality of data bins, each of said data bins being connected to its associated gating means to receive said data bit from said memory means.

3. A system as defined in claim 2, further comprising: detecting means, connected to said coincidence means to detect the condition of at least two signals overlapping in time so that some of their time slots occur in exact time coincidence; and clear signal generating means, connected to said detecting means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.

4. A system as defined in claim 3, further comprising: reset signal generating means, connected to said detecting means to generate a reset signal in response to the occurrence of said overlapping condition; said control means being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.

5. A decoder system useful in a radar beacon system for discriminating between reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: delay means for converting said reply signals from serial to parallel form, said delay means having a time delay equal to the fixed time interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay means; coincidence means, connected to said delay means to detect the coincidence of the first and second framing pulses of each reply signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said delay means output taps, said gating means being responsive to said coincidence signal to read out said data pulses appearing at said output taps; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse from said delay means with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.

6. A system as defined in claim 5, in which each of said memory means data bins comprises: a first binary storage device, connected to the output of its associated gating means to set said first binary storage device upon receipt of each data pulse; a first gate, connected to the outputs of said associated gating means and of said coincidence means to enable said first gate when said data pulse does not have a width equal to that of said coincidence signAl; a second storage device, connected to the output of said first gate to set said storage device when said first gate is enabled; and a second gate, connected to the outputs of said second storage device and of said coincidence means to enable said second gate when said second storage device is in its set state and the trailing edge of said coincidence signal is detected, the output of said second gate being connected to said first and second storage devices to reset the same in response to said second gate being enabled.

7. A system as defined in claim 5, further comprising: a plurality of control circuits, each associated with one of said reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal; a plurality of groups of gating means, each of said gating means in every group being connected to one of said memory means data bins and connected together to its associated control circuit to read out the data bit stored in said memory means in response to said transfer signal; and a plurality of code memory means, each comprising a plurality of data bins, each of said code memory data bins being connected to its associated gating means to receive the data bit from said memory means in response to said transfer signal.

8. A system as defined in claim 7, in which each of said control circuits is responsive to its associated coincidence signal to produce another transfer signal; a plurality of groups of another gating means, each of said another gating means in every group being connected to one of said data bins of its associated code memory means and connected together to its associated control circuit to read out the data bit stored in its associated code memory means in response to said another transfer signal.

10. A system as defined in claim 7, further comprising: detecting means, connected to said coincidence means to detect the condition of at least two reply signals overlapping in time so that some of their time slots occur in exact time coincidence; and clear signal generating means, connected to said coincidence means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.

11. A system as defined in claim 10, further comprising: reset signal generating means, connected to said detecting means to generate a reset signal in response to the occurrence of said overlapping condition; said control circuits being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.

12. A decoder system useful in a radar beacon system for discussing between first and second reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: a delay line for converting said reply signals from serial to parallel form, said delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay line; an AND gate, connected to said delay line to produce a coincidence signal in response to each pair of said first and second framing pulses; a plurality of NAND gates, each connected to one of said delay line output taps to read out said data pulse from said delay line in response to said coincidence signal; and a register having a plurality of data bins, said register including comparator means for comparing the width of Each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.

13. A system as defined in claim 12, in which each of said register data bins comprises: a main flip-flop, connected to the output of its associated NAND gate to set said main flip-flop upon receipt of each data pulse; a first NAND gate, connected to the outputs of said associated NAND gate and of said AND gate to enable said first NAND gate when said data pulse does not have a width equal to that of said coincidence signal; an auxiliary flip-flop, connected to the output of said first NAND gate to set said auxiliary flip-flop when said first NAND gate is enabled; a NOT gate, connected to the output of said AND gate to invert said coincidence signal; and a second NAND gate, connected to the outputs of said auxiliary flip-flop and of said NOT gate to enable said second NAND gate when said auxiliary flip-flop is in its set state and the trailing edge of said coincidence signal is detected, the output of said second NAND gate being connected to said main and auxiliary flip-flops to reset the same in response to said second NAND gate being enabled.

14. A system as defined in claim 12, further comprising: first and second control circuits, each associated with one of said first and second reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal; first and second groups of AND gates, each of said AND gates in each group being connected to one of said register data bins and connected together to its associated control circuit to read out the data bit stored in said data bin in response to said transfer signal; and first and second code registers, each comprising a plurality of data bins, each of said code register data bins being connected to its associated AND gate to receive the data bit from said register in response to said transfer signal.

15. A system as defined in claim 14, in which said first and second control circuits are responsive to their associated coincidence signals to produce another transfer signals; first and second groups of another AND gates, each of said another AND gates in each group being connected to one of said data bins of its associated code register and connected together to its associated control circuit to read out the data stored in its associated code register in response to said another transfer signal.

17. A system as defined in claim 14, in which each of said first and second control circuits produces first and second gate signals in response to its associated coincidence signal, said first and second gate signals having a duration equal to the fixed time interval between said first and second framing pulses; a first AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal to said first control circuit only when said second gate signal from said first control circuit is present; a second AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal through said second AND gate only when said first gate signal from said first control circuit is present; and a third AND gate, connected to said second AND gate and said second control circuit to permit passage of said coincidence signal to said second control circuit only when said second gate signal from said second control circuit is present.

18. A system as defined in claim 17, further comprising: a fourth AND gate, connected to said first and second control circuits and also to said first group of AND gates to permit passage of said transfer signal from said first control cIrcuit to said AND gates only when said transfer signal from said second control circuit is absent; and a fifth AND gate, connected to said first and second control circuits and also to said second group of AND gates to permit passage of said transfer signal from said second control circuit to said AND gates only when said transfer signal from said first control circuit is absent.

19. A system as defined in claim 17, further comprising: another delay line, connected to the output of said AND gate to receive said coincidence signals, said another delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving a sequence of said coincidence signals which occur when said first and second reply signals overlap in time so that some of their time slots occur in exact time coincidence; an OR gate, connected to the output taps of said another delay line to enable said OR gate when said coincidence signal appears at any of said output taps; a sixth AND gate, connected to the input of said another delay line and also to the output of said OR gate to enable said sixth AND gate when said overlapping condition of the first and second reply signals is present; and means for generating a clear signal in response to said sixth AND gate being enabled, said clear signal being supplied to said first and second code registers to clear the same.

20. A system as defined in claim 19, further comprising: means for generating a reset pulse each time said sixth AND gate is enabled; said reset pulse being supplied to said second control circuit to reset the same; a seventh AND gate, connected to the outputs of said second AND gate, said reset pulse generating means and said second control circuit to enable said seventh AND gate in response to each of said coincidence signals except for the first and second occurring ones; and a second OR gate, connected to the outputs of said third AND gate and of said seventh AND gate to couple said coincidence signals to said second control circuit when said second OR gate is enabled; whereby said second control circuit is repeatedly reset in response to said reset pulses until it is set by the particular coincidence signal which results from the framing pulses of said second reply signal.