US3858207A

US3858207A - Range sensing target detecting device

Info

Publication number: US3858207A
Application number: US00583497A
Authority: US
Inventors: B Macomber; N Gravelle
Original assignee: US Department of Navy
Current assignee: US Department of Navy
Priority date: 1966-09-29
Filing date: 1966-09-29
Publication date: 1974-12-31
Anticipated expiration: 1991-12-31

Abstract

A target detecting device having a plurality of gate circuits and time delay computers for determining after intercept of a target, the optimum missile-target range to effect maximum target damage.

Description

Macomber et al.

RANGE SENSING TARGET DETECTING DEVICE nited States Patent Inventors: Bennie D. Macomber, Norco; Noel D, Gravelle, Riverside, both of Calif.

Assignee:

Filed:

Appl. No.:

The United States of America as represented by the Secretary of the Navy, Washington, DC.

Sept. 29, 1966 US, Cl. 343/7 PF, 102/702 P Int. Cl.

[ Dec. 31, 1974 Primary ExaminerT. H. Tubbesing Attorney, Agent, or Firm--Richard S. Sciascia; Joseph M. St. Amand; T. M. Phillips 5 7 ABSTRACT A target detecting device having a plurality of gate circuits and time delay computers for determining after intercept of a target, the optimum missile-target range Field of Search 343/7, 7 PF, 12 MD; 102/702 P to effect maximum target damage.

5 Claims, 8 Drawing Figures MODULATOR ,CLOCK Y J -i THRESHOLD A DISCHARGE l IZ ,22 TT ,2a ,34 I ,40

74s TARGET VARIABLE TARGET T|ME DE| .AY V ELAY A GATE D THRESHOLD. COUNT COMPUTER T f ds ,|4 24 30- as 42 4a TARGET DELAY VARIABLE TARGET T|ME.DE| AY a GATE 2 THRESHOLD COUNT COMPUTER |o T 1 dz TARGET DELAY VARIABLE TARGET nME DELAY E GATE 3" THRESHOLD COUNT I COMPUTER 4 l8 EMITTER FOLLOWER 'V R AND PEAK i DETECTOR 3 PATENTEDBEB31 I914 3, 858.207

SHEET 10F 4 I mt ' MAXIMUM ERROR "*TM\DIOPTIMUM BURST T 0 Z BENNIE D. MACOMBER NOEL D. GRAVELLE INVENTORS y ATTORNEYS ATTORNEYS PATENTEU 3.858.207 SHEET 2 BF 4 5 MODULATOR T THRESHOLD DISCHARGE l lz 22

IT

28 ,34 ,40 TARGET DELAY VARIABLE TARGET TIME DELAY GATE I THRESHOLD COUNT COMPUTER J ds [l4 24 30 36 42 48 TARGET DELAY VARIABLE TARGET T|ME DELAY a GATE 2 THRESHOLD COUNT COMPUTER I0 4 f f T l6 26 32 38 44 TARGET DELAY VARIABLE TARGET TIME DELAY GATE 3 THRESHOLD COUNT COMPUTER ,Ia EMITTER FOLLOwER DR'VER AND PEAK 5 DETECTOR vIDEO GATE CUTOFF TRANSMIT PULSE RECEIVE PULsE f ON 25 FT +50 NSEC-b 30 FT TRANSMIT PULSE OFF TARGET GATE I ON -|5NSEC OFF OFF TARGET GATE 2 25 mm 0N OFF TARGET I ON GATE 3 I I v TIME I OUTPUT OF 3 vIDEO GATE 25H FIG 4 30 FT BENNIE D. MACOMBER I THRESHOLD SET NOEL D. GRAVELLE BY AMPLITUDE OF INVENTORS INPUT TO RECEIVED PULSE THRESHOLD CIRCUIT BEFORE GATING BY 25 FT 2/, 30 FT J 2 PATEHTEDUEE3 1 I974 SHEET 3 OF 4 BENNIE D. MACOMBER NOEL D. GRAVELLE W Aw INVENTORS ATTORNEYS AIENTEDB B 3.858.207

SHEET l UF 4 COMPUTER 2 M131 (D A) i: l j o m TARGET GATE CONTROL FIG.8

BENNIE D. MACOMBER NOEL D. GRAVELLE INVENTORS TTORNEYS FIG.- 6

RANGE SENSING TARGET DETECTING DEVICE The invention herein described may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

The present invention relates to target detecting devices and more particularly to target detecting devices having a controlled warhead burst initiation.

In proximity fuze systemspresently in use on antiaircraft guided missiles, atime delay between target detection and warhead burst is implemented as a function of relative closing velocity between the target and the missile. The purpose of this time delay is to maximize the probability of the lethal portions of the warhead striking a vulnerable area of the target. If correctly determined, this time delay would be a function not only of closing velocity as in present systems, but also of.

' to effect maximum target damage.

The present invention provides a circuit arrangement,

which permits the use of multiple range gates and special adapted thresholds which permit sharp range deflnition, resulting in the determination of target range at the time of target detection. The input from a radar receiver consisting of a unipolar video pulse train which is the result of the detection of microwave pulses reflected from a target is applied to the inputs of three gates and an amplitude detector. The timing of the gates is such that the pulses pass through target gate one if they have been reflected from anobject the range of which is between R1 feet. Pulses passed through target gate two if they have been reflected from an object the range of which is between 0 and R2 feet. In a similar manner pulses passed through target gate three if they have been reflected from an object the range of which is between 0 and R3 feet. An ampli- I tude detector and threshold driver set the thresholds on an individual pulse basis, thereby providing sharp discrimination between ranges regardless of pulse amplitude. Accordingly, an object of the invention is to provide a means of determining the missile-to-target range at the time of intercept, to permit a more optimum control over warhead burst time to effect maximum target damage. 7

Other objects and many of the attendant advantages of this invention will become readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

FIGS. 1 and 2 show the relationship between target and missile at time of intercept.

' FIG. 3 is a graph showing the time relationship between transmit pulse and target gates. FIG. 4 is a graph of a specific example of transmit pulse and a target return from two different targets.

FIG. 5 is a block diagram of a preferred embodiment of the invention.

FIGS. 6-8 are a schematic diagram of the embodiment of FIG. 4.

Referring now to the drawings there is shown in FIG. 1 an intercept condition with look angle, 6, relative missile target velocity, V,,,,, and miss-distance, RT. The relative velocity of the warhead which may be of the expanding rod type is V,.. T, is the time for rod to travel from warhead to target. The time delay, T between time of detection and time of warhead burst to obtain maximum effectiveness can be determined as follows:

In FIGS. 1 and 2, the detection angle represents the locus of the position of the first portion of all targets which may be detected by the proximity fuze. The warhead burst lines represents the locus of a vulnerble portion of these targets at optimum warhead burst time. Rod hit lines represent the locus of a vulnerable portion of these targets at the time the warhead lethal agent arrives at the target. In FIG. 2, the blast radius is the radius of a sphere within which a target will be destroyed if the target is present within this sphere at the time of warhead burst.

The present invention provides a system which breaks up the miss-distance factor, RT, into a plurality of parts so that the time delay between target detection and warhead detonation can be computed on the basis of range as well as relative velocity thereby reducing the compromise of present systems. This is illustrated by considering that if the miss distance were X instead of RT (FIG. 1) that the time delay T which was optimum for miss distance RT would allow the target to pass the missile to point Y when the warhead is burst and the damage to the target would be reduced. Therefore the delay time from target detection to warhead burst must take into account the miss distance to the target to achieve maximum damage to the target. FIG.

2 shows how, RT, is broken into three sub-ranges, R R -R and R R This is accomplished as shown by the timing diagram of FIG. 3.' Referring to FIG. 3, all target gates are off while the transmitter is on and all target gates are turned on as the transmitter goes off. Target gate L is on only for a period of time corresponding to the time required for the transmitted energy to reach an object at slant range SR 1 (FIG. 2) and return through the receiver at which time it isturned off. The on times for

target gates

2 and 3 are determined in a similar manner by the time required for energy to be reflected from objects at slant ranges SR 2 and SR 3 respectively. In a radar type proximity fuze the transmit pulse which is reflected from a target is called a target return. If thetarget return should occur during the time interval that target gate 1 is on, the target return will appear at the output of target gates l, 2, and 3 simultaneously and the slant range to the target is known to be less than SR 1. If the target return should, instead, occur after target gate 1 is off but before target gate 2 is off, the target return will appear at the output of

target gates

2 and 3 only and the slant range to the target is known to be greater than SR 1 but less than SR 2. If thetarget return should, instead, occur after target gate 2 is off but before target gate 3 is off, the target return will appear at the output of target gate 3 only and the slant range to the target is known to be greater than SR 2 but less than SR 3. R is larger than R R and R -R since the effective blast radius of the warhead does not require fine resolution at close range and the length of the first range gate sets the IF and video bandwidth of the system and the length of the transmitted pulse. As shown above, the time delay equation shows that the time delay required is directly proportional to range, RT. Hence if the correct time delay for targets detected in range R R for a given V,,,,, V,, and 6 is T then the correct time delay for the other two range intervals is a fraction of T determined by the ratio of the midpoints of the range intervals. Thus time delay for range R -R, is:

and the time delay for range R, is:

where:

K,, K are constants to be determined by intercept lethality analysis. To implement a range sensing target detecting device effectively, the cutoff from one range bracket to another should be kept to a minimum to reduce the possibility of range ambiguity.

Referring to the waveforms of FIG. 4, there is shown a fifty nsec transmit pulse and target return signals at twenty-five and thirty feet. A video gate is applied to the received signals allowing only the first fifty nsec of the received pulse (which has been stretched and rounded by the IF amplifier) to pass. The pulse returned from a twenty-five feet range now has an effective pulse of twenty-five nsec and the pulse returned from the thirty feet range now has an effective pulse width of fifteen nsec. These pulses are now separately fed through a low pass filter to a variable threshold circuit which has been set to the peak amplitude before gating action had diminished the pulse width. The pulse corresponding to the object at twenty-five feet range would exceed the threshold whereas the pulse corresponding to the object at thirty feet would not because of the greater attenuation of the narrower pulse by the low pass filter.

As shown in FIG. 5, the reflected target signal is received at terminal 10 and fed to

gates

12, 14, and 16 and to peak detector 18.

Gates

12, 14, and 16 are each controlled by a gate control circuit 20 which is initiated by input signals from the radar modulator l3 controlled by clock 15. The signals passed by

gates

12, 14, and 16 are coupled through

delay lines

22, 24, and 26 to

variable threshold circuits

28, 30, and 32 respectively which will produce an output signal as determined by the output of detector 18. As soon as target gate 16 is turned off, a discharge pulse is fed from threshold discharge circuit 17 to peak detector 18 and will later be described in more detail. The pulses generated by a threshold circuit are counted by their corresponding counter (34, 36, 38) and if a sufficient number of pulses are counted within a predetermined time, an output pulse will be fed to a corresponding computer (40, 42, 44). Each computer will produce an output pulse at its output terminal (46, 48, 50). However the output of each computer will be delayed from its input by an amount proportional to the closing velocity information supplied by the missile homing system, R, and the particular target gate from which the target return was processed. Thus if a target is detected within

target gate

1, 2, and 3, there will be simultaneous inputs to all three computers but since the delay within computer 1 is less than the delay within

computer

2 and 3 the warhead burst will be controlled by time delay computer I. In a similar manner targets detected at a range such that the target return signals are processed only by

target gates

2 and 3 will cause warhead burst to be controlled by time delay computer 2. Likewise target return processed only by target gate 3 will cause warhead detonation to be controlled by time delay computer 3.

For illustrative purposes, only one channel of the block diagram of FIG. 4 has been shown in the schematic diagrams of FIGS. 6-8. Referring to FIG. 6 there is shown in schematic diagram form the gate control circuit 20 of FIG. 4. Input signals from the radar modulator 13 are fed to input terminal where it is fed to a variable width blocking oscillator 62 which generates a series of pulses that are fed to a fixed width blocking oscillator 64 and a delay line 66. Blocking oscillator 64 generates an output pulse at terminal 68 for each pulse received from blocking oscillator 62 and is fed as the gating pulse to target gate 12 (FIG. 5). The delayed signal from delay line 66 is fed to fixed blocking oscillator 70 and delay line 72. Blocking oscillator 70 generates an output pulse at terminal 74 which is fed to target gate 14. The twice delayed signal at the output of delay line 72 is fed to fixed width blocking oscillator 76 which generates an output pulse at terminal 78 which is fed to target gate 16. Delay lines 66 and 72 may be of the lumped constant type.

Referring to FIG. 7, target gate 12 is shown as a normally conducting transistor 80 having a transistor 82 connected between the base and emitter for turning it off in response to a timing pulseat terminal 84 received from gate control 20 (FIG. 5). The video signal received at terminal 10 and passed by gate 12 is fed through delay line 22 to the base 86 of transistor 88 pled through a compound emitter follower driver circuit 96 to the base of transistor 90.'Thevoltage stored on capacitor is the threshold voltage and will be discharged through diode 97 to'the threshold discharge circuit 17 through terminal 50 (FIG. 5). Discharge circuit 17 may be a one shot multivibrator which is triggered by the output of clock 15 and has a pulse width sufficient to permit target gate 16 to turn off. Capacitor 95 is discharged at the end of the output pulse from discharge circuit 17.

The output signal from transistor 88 is coupled by coupling capacitor 98 to emitter follower 100 of target counter 34. The pulse out of emitter follower 100 is fed to blocking oscillator 102 which generates an output pulse for every input pulse received. The pulses generated by blocking oscillator 102 are fed to staircase generator 104. Resistor 105 provides a decay for capacitor 107 so that if a predetermined number of pulses are not received with a given time the voltage of capacitor 107 will never build up to a sufficient amplitude to cause Zener diode 106 to break down and discharge capacitor 107. The discharge pulse from capacitor 107 triggers a Schmitt trigger 108 to produce an output signal suitable for processing by computer 40.

Computer 40 (FIG. 8) consists of a monostable multivibrator 110 which is triggered by the input signal from Schmitt trigger 108 (FIG. 7). The bias supplied from emitter follower circuit 112 to the base of transistor 114 is proportional to the closing velocity of the missile and target and is for the purpose of controlling the pulse width or delay of multivibrator 110. The inputsignal to emitter follower circuit 112 is the R voltage from impedance network 41 (FIG. and represents velocity and is supplied by the missile guidance (not shown) range. The output pulse from the computer is coupled through a differentiating capacitor 115 to diodes 116 and 118 which are to permit only negative pulses to be fed to output terminal 120 for utilization by a firing circuit (not shown).

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

What is claimed is:

1. In a guided missile range sensing target detecting device, the combination comprising:

a. a plurlity of target gate circuits for receiving video signals reflected from a target,

b. target gate control means coupled to said plurality of target gate circuits for controlling the time interval each gate is open,

c. peak detector circuit means having an input for receiving and producing an-output proportional to the amplitudeof the reflected video signals,

d. 'delay filter circuit means coupled to each of said target gate circuits for attenuating signals which have a pulse width less than a predetermined value,

e. variable threshold circuit means coupled to each of said delay filter circuit means for passing only the video signals received from said delay filter circuit means when they exceed the output signal from said peak detector circuit,

f. target count circuit means coupled to each of said variable threshold circuit means for producing an output pulse in response to a predetermined number of video pulses received from said variable threshold circuit means within a predetermined time interval,

g. a plurality of computer circuit means each having a first input coupled to the output of a target count circuit means and having a second input for receiving a voltge proportional to missile to target closing velocity for producing an output firing pulse in response to the presence of a pulse from said target count circuit.

said target gate circuits comprises:

a. first and second transistors each having a base, emitter and a collector,

b. the base of said first transistor being coupled to an input terminal for receiving said video signals,

c. the base of said second transistor being coupled to said target gate control means,

d. the collector'of said second transistor being connected to thebase of said first transistor,

e. the emitter of said first transistor being connected to an output terminal and through a load'resistor to the emitter of said second transistor.

3. The detecting device of claim 1 wherein said delay filter circuit means provides a sufficient delay of the video signal passed to permit the output voltage of said peak detector resulting from the same video signal to reach said variable threshold circuit means first.

4. The detecting device of claim 1 wherein said target gate control means comprises:

a. an input terminal coupled to receive input pulses from a periodic pulse generating means,

b. a variable width blocking oscillator having an input coupled to said input terminal for producing a series of output pulses in response to the periodic pulses at said input terminal,

c. a first fixed width blocking oscillator coupled directly to said variable width blocking oscillator for producing a first series of gating pulses,

d. a first delay circuit having a first predetermined delay coupled to the output of said variable width blocking oscillator,

e. a second fixed width blocking oscillator coupled to said delay circuit for producing a second series of gating pulses delayed with respect to said first series of timing pulses by the amount of said first predetermined delay,

f. a second delay circuithaving a delay equal to that of said first delay circuit,

g. a third fixed w'idth blocking oscillator coupled to said second delay circuit for producing a series of gating pulses delayed with respect to said first series of gating pulses by the amount of delay of said first and second delay circuits combined.

5. The detecting device of claim 1 wherein said computer circuit comprises a monostable multivibrator triggered by the output of said target count circuit and biased by a voltage proportional to the missile to target closing velocity as modified to represent slant range to

Claims

1. In a guided missile range sensing target detecting device, the combination comprising: a. a plurlity of target gate circuits for receiving video signals reflected from a target, b. target gate control means coupled to said plurality of target gate circuits for controlling the time interval each gate is open, c. peak detector circuit means having an input for receiving and producing an output proportional to the amplitude of the reflected video signals, d. delay filter circuit means coupled to each of said target gate circuits for attenuating signals which have a pulse width less than a predetermined value, e. variable threshold circuit means coupled to each of said delay filter circuit means for passing only the video signals received from said delay filter circuit means when they exceed the output signal from said peak detector circuit, f. target count circuit means coupled to each of said variable threshold circuit means for producing an output pulse in response to a predetermined number of video pulses received from said variable threshold circuit means within a predetermined time interval, g. a plurality of computer circuit means each having a first input coupled to the output of a target count circuit means and having a second input for receiving a voltge proportional to missile to target closing velocity for producing an output firing pulse in response to the presence of a pulse from said target count circuit.

2. In the detecting device of claim 1 wherein each of said target gate circuits comprises: a. first and second transistors each having a base, emitter and a collector, b. the base of said first transistor being coupled to an input terminal for receiving said video signals, c. the base of said second transistor being coupled to said target gate control means, d. the collector of said second transistor being connected to the base of said first transistor, e. the emitter of said first transistor being connected to an output terminal and through a load resistor to the emitter of said second transistor.

4. The detecting device of claim 1 wherein said target gate control means comprises: a. an input terminal coupled to receive input pulses from a periodic pulse generating means, b. a variable width blocking oscillator having an input coupled to said input terminal for producing a series of output pulses in response to the periodic pulses at said input terminal, c. a first fixed width blocking oscillator coupled directly to said variable width blocking oscillator for producing a first series of gating pulses, d. a first delay circuit having a first predetermined delay coupled to the output of said variable width blocking oscillator, e. a second fixed width blocking oscillator coupled to said delay circuit for producing a second series of gating pulses delayed with respect to said first series of timing pulses by the amount of said first predetermined delay, f. a second delay circuit having a delay equal to that of said first delay circuit, g. a third fixed width blocking oscillator coupled to said second delay circuit for producing a series of gating pulses delayed with respect to said first series of gating pulses by the amount of delay of said first and second delay circuits combined.

5. The detecting device of claim 1 wherein said computer circuit comprises a monostable multivibrator triggered by the output of said target count circUit and biased by a voltage proportional to the missile to target closing velocity as modified to represent slant range to the target.