US3777769A

US3777769A - Counting device having memory-readout and logic circuits

Info

Publication number: US3777769A
Application number: US00330417A
Authority: US
Inventors: S Ueno
Original assignee: Tokai Rika Co Ltd
Current assignee: Tokai Rika Co Ltd
Priority date: 1972-02-12
Filing date: 1973-02-07
Publication date: 1973-12-11
Anticipated expiration: 1990-12-11
Also published as: DE2306758A1

Abstract

A device for counting articles capable of by far speeding up the counting time, which comprises a plurality of gates through which the articles are fed, a plurality of detecting means provided on the respective gates for generating a signal upon detection of the article, a plurality of memory-readout circuits connected to the respective detecting means and adapted to memorize the signals therefrom, a sweep signal generator for periodically reading out the signals memorized by said memory-readout circuit, a logical circuit and a digital counter or an analogic indicator for integratingly indicating signals obtained through said logical circuit.

Description

United States Patent 1 Ueno [ Dec. 11, 1973 COUNTING DEVICE HAVING MEMORY-READOUT AND LOGIC CIRCUITS [75] Inventor:

[22] Filed: Feb. 7, 1973 [21] Appl. No.: 330,417

Shinichi Ueno, Inazawa, Japan [30] Foreign Application Priority Data [56] References Cited UNITED STATES PATENTS Klopp 133/8 R Johnson 194/10 X Bowring 194/10 Primary Examiner-Stanley I-I. Tollberg AttorneyRobert Osann et al.

[57] ABSTRACT A device for counting articles capable of by far speeding up the counting time, which comprises a plurality of gates through which the articles are fed, a plurality of detecting means provided on the respective gates for generating a signal upon detection of the article, a plurality of memory-readout circuits connected to the respective detecting means and adapted to memorize the signals therefrom, a sweep signal generator for periodically reading out the signals memorized by said memory-readout circuit, a logical circuit and a digital counter or an analogic indicator for integratingly indicating signals obtained through said logical circuit.

5 Claims, 10 Drawing Figures PATENTED DEC 1 1 I975 SHEET 10F 5 FIG.

FIG. 2

PATENIEIJHEC 1 1 I973 SHEEI 2 OF 5 puls e osclllofor FIG. 7

COUNTING DEVICE HAVING MEMORY-READOUT AND LOGIC CIRCUITS This invention relates to a counting device and more particularly to a counting device capable of by far reducing the time required for counting articles.

In a conventional counting device, such as a coin counting device, coins are fed through one passage where they are detected through an optical or mechanical means and converted into pulse signals for actuating a counter to indicate the number of coins.

With this conventional counting device, however, the counting speed could be hardly improved even by quickening the feeding speed of the coins, since the coins are fed and passed through one passage in such a coin counting device.

This invention is made to overcome the abovementioned problem and therefore it is an object of the present invention to provide a device for counting articles, in which a conveyor means is provided for transporting the articles and a plurality of passages are provided for detecting a plurality of articles simultaneously, thereby to improve the counting speed very much.

It is another object of the present invention to provide a device for counting articles, in which a conveyor means is adapted to be intermittently driven to even the articles to be detected, without overlapping each other.

It is a further object of the present invention to provide a device for counting articles, in which a conveyor means is adapted to be driven continuously so long as the articles are fed in an even position without overlapping each other.

According to the present invention, there is provided a counting device comprising a hopper; a conveyor driven by a motor and provided below said hopper; a chute disposed adjacently to the forward end of said conveyor, inclined downwardly of said forward end of the conveyor and provided with a plurality of gates; photoelectric detecting means provided on the respective gates and adapted to generate a pulse signal upon detection of articles to be counted; a plurality of memcry-readout circuits respectively connected to the corresponding photoelectric detecting means and adapted to memorize the pulse signalsfrom said photoelectric detecting means for a predetermined time; a sweep signal generator adapted to generate a sweep signal for periodically reading out the signals memorized by said memory-readout circuit; a logical circuit for obtaining logical sum of each of the signals read out through said sweep signal generator; and a display means for integratingly indicating the number of the signals from said logical circuit.

The invention will be better understood from the following description taken in connection with the accompanying drawings in which:

FIG. 1 is a perspective view of a counting device in accordance with the present invention;

FIG. 2 is a cross sectional view of FIG. 1;

FIGS. 3 and 4 are side views of a switch means for a motor employed in the present invention, showing its operating condition;

FIG. 5 is a diagram of an electric circuit for controlling the motor;

FIG. 6 is an explanatory-view of photoelectric detecting means employed in this invention;

FIG. 7 is a cross sectional view of FIG. 6 taken along line VII-VII;

FIG. 8 is a block diagram of a counting circuit;

FIG. 9 is an electric diagram of a part of FIG. 8, and

FIG. 10 is a timing chart of signals of the counting circuit shown in FIG. 8.

Referring now to the drawings, there is illustrated a counting device embodying the present invention, which has a frame 1, a hopper 2 fixed to said frame 1 at the upper portion thereof and a conveyor 3 provided under said hopper 2. A lower front plate 2a of said hopper 2 is provided to form a suitable opening for feeding articles 4 to the conveyor 3. The articles 4 charged into said hopper 2 are thus fed onto the conveyor 3 and transported through the opening defined by said lower front plate 2a of the hopper 2, according to the movemerit of the conveyor 3. Said conveyor 3 is stretched between a drive roller 3a and another roller 3b which are rotatably provided on the frame 1. A belt 3f is put on between a. pulley 3d of a motor 30 mounted on the frame 1 and a pulley 3e of said drive roller 3a. A chute 5 is fixed to the frame 1 so as to be adjacent to the forward end of said conveyor 3 and inclined downwardly of said forward end of the conveyor 3. This chute 5 has a plurality of gates 5b formed identically by partitions 5a, according to the size of the articles 4 to be counted. To each of said gates 5b is provided a photoelectric detecting means 6 consisting of a light source 6a and a light receiver 6b such as 'CdS. The photoelectric detecting means 6 is mounted on the respective gate 5b at a position one sided from the longitudinal central line of said gate 5b. If said photoelectric detecting means 6 is centrally mounted, a signal can hardly be obtained when the articles 4 are continuously fed close to one another. A vibrator 7 is mounted on the chute 5 to give vibration to said chute 5 so that the articles 4 thereon may fall down smoothly.

Numeral 8 designates a detecting plate pivotably fixed to the frame 1 so as to be disposed above the conveyor 3 in height just sufficient to pass one article 4 in the even position. Said detecting plate 8 has a spring 8a fitted thereto to urge said plate 8 toward a microswitch 9 fixed to the frame 1, pressing a movable contact 9a of said micro-switch.

As shown in FIG. 5, numeral 10 designates an oscillator which generates rectangular pulse at given intervals. An output terminal of the oscillator 10 is connected to a normally closed contact of the micro-switch 9. A normally opened contact of said micro-switch 9 is connected to a ground and a movable contact thereof is connected to the base of a PNP type transistor Tr through a resistor R The emitter of said transistor Tr is connected to a positive terminal of a power source and the collector thereof to the gate of a bilateral controlled rectifier such as TRIAC (Trade name of the product manufactured by GE.) T through a resistor R A first terminal of an A.C. power source E and a second terminal thereof is connected to another terminal of said A.C. power source E through said motor 3c and a power switch S.

In operation, it will be seen that when the article 4 are charged into the hopper 2, they are gradually fed onto the conveyor 3 and transported by said conveyor 3 to the chute 5, if the power switch S is closed in this stage and the TRIAC T is in the on position. At this time, if the detecting plate 8 is not displaced and kept in such a position for keeping the contact 9a of the micro-switch 9 in the condition as shown in FIG. 5, to wit, the articles 4 are transported in even state without overlapping one another as shown in FIG. 3, the base of the transistor Tr is at a grounding potential to allow a base current to flow and accordingly, a collector current to flow to the gate of the TRIAC T through the resistor R As a result, said TRIAC T is turned on to rotate the motor 30.

On the other hand, if some of the articles 4 are fed overlapping one another as shown in FIG. 4, they will displace the detecting plate 8 against the action of the spring 8a and the contact 9a of the micro-switch 9 is switched from the position of FIG. so that the base of the transistor Tr is connected to a rectangular pulse generator through the resistor R,. In the transistor Tr, a base current flows at 0 level of the rectangular wave and, then, a collector current flows to the gate of the TRIAC T through the resistor R to turn on said TRIAC T. The motor 3c is then rotated. At a high level of said rectangular wave, a base current does not flow and the transistor Tr is turned off so that a gate current does not flow in the TRIAC T and said TRIAC is turned off. Accordingly, the motor 3c is not rotated. It is thus seen that when the base of the transistor Tr is connected to the oscillator 10, the motor 30 is adapted to be driven and halted repeatedly according to the level of the rectangular wave. Thus, the conveyor 3 is driven intermittently, giving shocks to the articles 4 to make them even and feed to the chute 5.

The articles 4 fed to the chute 5 slide down smoothly since said chute 5 is inclined downwardly and vibrated by the vibrator 7, and are passed through respective gates 5b formed by the partitions 5a. When these articles 4 pass through the gates 512, they interrupt lights from respective light sources 6a, thereby to be detected by the respective light receivers 6b to generate signals. These signals will be counted through a counting circuit as mentioned later to indicate the number of the articles 4. In this embodiment of the present invention, since a plurality of gates 5b are provided, the sum ofthe articles 4 passed through the respective gates is indicated as the number of the articles 4.

The counting-circuit is explained referring to FIG. 8 wherein l,, I I,, l, are input terminals thereof connected to the respective light receivers 6b and adapted to receive input pulse signals therefrom.

A,, A A, A,, are memory-readout circuits to which said input terminals I,, l l 1,, are connected, respectively. Each of said memory-readout circuits A,, A A A, includes a memory circuit 11, a delay circuit 12, a monostable multivibrator 13, a gate circuit 14 and a build-up delay circuit 15. The signals received by said input terminals l,, l l l,, are memorized for a predetermined period of time, read out by signals from a sweep signal generator B as mentioned below and applied to a logical circuit, more particularly a NOR circuit C.

The sweep signal generator B has output terminals corresponding to the respective input terminals l,, 1 I, l, of the memory-readout circuits A,, A A, A, and connected to said memory-readout circuits A,, A A, A, to transmit sweep signals thereto sequently. As the sweep signal generator B, a ring counter or a shift register may be employed to generate sweep signals respectively for the input terminals 1,, l 1,, l, with a cycle of T. The high level of such sweep signals is determined to last for t, period of time. Through the NOR circuit C, logical sum of each of the signals memorized by the memory-readout circuits A,, A A, A and read out through the sweep signal generator B is obtained. In other words, the NOR circuit C is adapted to produce an output or a signal upon receipt of an output or a signal from the memory-readout circuit A,, A A or A, through the sweep signal generator B. A display means D may be a digital counter which is adapted to count one upon every receipt of the output or signal from said NOR circuit.

FIG. 9 shows the memory-readout circuit A, more particularly. The memory circuit 11 forms a flip-flop circuit of

NAND gates

11a and 11b having two input terminals. An input terminal of the NAND gate 11a is connected to the input terminal I, and an input terminal of the NAND gate 11b is connected to the delay circuit 12. The delay circuit 12 is composed of a resistor R, and a condenser C, and adapted to apply an output to said NAND gate 11b after a time delay determined by said resistor R, and said condenser C,. An input terminal of said delay circuit 12 is connected to an output terminal of the monostable multivibrator 13. This monostable multivibrator 13 is composed of a NAND gate 13a, a condenser C a resistor R and an inverter 13b. The gate circuit 14 has a NAND gate one input terminal of which is connected to an output terminal of the NAND gate 11a of said memory circuit 11 and the other input terminal of which is connected to an output terminal of the build-up delay circuit 15. An output terminal of said gate circuit 14 is connected to an input terminal of the monostable multivibrator l3 and an input terminal of the NOR circuit C. The build-up delay circuit 15 includes resistors R and R,, a condenser C,

inverters

15a and 15b and a diode D,. An input terminal of said circuit 15 is connected to one output terminal of the sweep signal generator B and the output terminal thereof is connected to one input terminal of the gate circuit 14. The build-up delay is obtained by the resistor R and the condenser C and falling is effected by the diode D, without any delay.

The other memory-readout circuits A A, A, are composed identically with the above specified memory-readout circuit A,.

It will be thus seen in operation that when a low level signal 11a, is applied to the input terminal I, of the memory circuit 11, the output 11a, obtained therefrom is a high level signal and that when a reset signal (low level) is applied to the input terminal of the NAND gate 11b of the memory circuit 11, the output of said memory circuit 11 becomes low level. Accordingly, when a sweep signal b, is transmitted by the sweep signal generator B under the condition an input signal has been applied to the input terminal l,, this sweep signal is applied as a signal 15, to the input terminal of the gate circuit 4 through the build-up delay circuit 15 after delay of 1, determined by the resistor R and the condenser C Since this gate circuit 14 has already received a high level signal from the memory circuit 11, the output signal therefrom is of low'level. When the output signal 14, from the gate circuit 14 is applied to the NOR circuit C, a high level signal 0, is generated to actuate the digital counter D and count one.

On the other hand, since the output signal 14, from the gate circuit 14 is applied to the monostable multivibrator 13, an output signal 13, from said monostable multivibrator 13 has width of t, and a signal 11b, is applied to the input signal of the NAND gate 11b which is a resetting input terminal of the memory circuit 11 after delay of I: obtained by a time constant circuit composed of the resistor R, and the condenser C of the delay circuit 12. The memory circuit 11 is thus reset and restored to its original position to cancel the memory. The output signal 14, from the gate circuit 14 normally has width of t A second stage circuit A is operated-identically with the above-mentioned first stage circuit A When an input signal lla is applied to the input terminal I an output signal Illais generated and an output signal 14 is obtained from the memory-readout circuit A Subsequently, an output signal is produced from the NOR circuit to actuate the digital counter D, counting one, and indicate two.

However, as shown in FIG. 10, if an input signal lla is applied to an input terminal 1 just before fall of the sweep signal b an output signal 0 has a width reduced than the above-mentioned cases. At this time, even if the input signal 110;, remains after the sweep signal has disappeared, the memory circuit 11 can be surely reset insofar as I is determined to be longer than the input signal 11 since the resetting signal is retained for period of by the monostable multivibrator 13.

Accordingly, there must be a relation r t wherein 1 is a width of an input signal applied to the input terminal of the memory circuit 11 and is a width of an output signal of the monostable multivibrator 13. There must be another relation t T/n wherein t, is a width of an output signal of the sweep signal generator B and T is a cycle of the sweep signals. T should be determined to be shorter than any cycle of the input signals 1a,, 111 1a,, applied to this counting circuit.

The similar operation will be effected in the following memory-readout circuits (A, A

In the present circuit arrangement, when a signal is not applied to an input terminal of the memory-readout circuit, an output is not produced from the gate circuit 14 if the sweep signal is applied to the build-up delay circuit 5.

Thus, signals arbitrarily applied to the input terminals l,, l l l, of the memory-readout circuits A A A A irregularly, are drawn out at the output of the NOR circuit C at intervals of t,. The digital counter D, then, counts one at every arrival of the signal from said NOR circuit to indicate the number of the input signals.

By combining input terminals 1,, l l l,, to the coin detecting means 6, it becomes possible to count coins passed randomly through 11 gates.

In the foregoing, a digital counter D is employed for indicating the number of the coins, but analogic indication means such as a meter may be alternatively employed for indicating the number of the articles applied in unit time.

According to the present invention, when a plurality of articles are fed simultaneously or at arbitrary intervals, the number of the articles can be accurately counted.

What is claimed is:

1. A counting device comprising a hopper; a conveyor driven by a motor and provided below said hopper; a chute disposed adjacently to the forward end of said conveyor, inclined downwardly of said forward end of the conveyor and provided with a plurality of gates; photoelectric detecting means provided on the respective gates and adapted to generate a pulse signal upon detection of articles to be counted; a plurality of memory-readout circuits respectively connected to the corresponding photoelectric detecting means and adapted to memorize the pulse signals from said photoelectric detecting means for a predetermined time; a sweep signal generator adapted to generate a sweep signal for periodically reading out the signals memorized by said memory-readout circuit; a logical circuit for obtaining logical sum of each of the signals read out through said sweep signal generator; and a display means for integratingly indicating the number of the signals from said logical circuit.

2. A counting device as claimed in claim 1, wherein each of said memory-readout circuits includes a mem-.

ory circuit adapted to be turned on to produce an output upon receipt of the input signal from said photoelectric detecting means and kept turned on until a signal is applied thereto from a delay circuit connected in said memoryreadout circuit; and a gate circuit adapted to produce an output when the output signal from said memory circuit and the sweep signal from said sweep signal generator are applied thereto; said delay circuit being adapted to apply the output signal from said gate signal to said memory circuit after the predetermined time delay to turn off said memory circuit.

3. A counting device as claimed in claim 2, wherein said memory-readout circuit further includes a buildup delay circuit which is adapted to apply said sweep signal from the sweep signal generator to said gate circuit after a predetermined time delay.

4. A counting device as claimed in claim 2, wherein said memory-readout circuit further includes a monostable multivibrator for making the width of said output signal from said gate signal larger than that of the input signal from the photoelectric detecting means.

5. A counting device as claimed in claim 1, which further comprises a detecting means disposed over said conveyor in height just for passing one article thereunder and adapted to be displaced by the articles fed on said conveyor overlapping one another; a switch adapted to be operated by the displacement of said detecting means; and a motor control circuit having a pulse oscillator electrically connected when said switch is operated by the displacement of the detecting means to intermittently drive said motor.

Claims

1. A counting device comprising a hopper; a conveyor driven by a motor and provided below said hopper; a chute disposed adjacently to the forward end of said conveyor, inclined downwardly of said forward end of the conveyor and provided with a plurality of gates; photoelectric detecting means provided on the respective gates and adapted to generate a pulse signal upon detection of articles to be counted; a plurality of memory-readout circuits respectively connected to the corresponding photoelectric detecting meaNs and adapted to memorize the pulse signals from said photoelectric detecting means for a predetermined time; a sweep signal generator adapted to generate a sweep signal for periodically reading out the signals memorized by said memoryreadout circuit; a logical circuit for obtaining logical sum of each of the signals read out through said sweep signal generator; and a display means for integratingly indicating the number of the signals from said logical circuit.

2. A counting device as claimed in claim 1, wherein each of said memory-readout circuits includes a memory circuit adapted to be turned on to produce an output upon receipt of the input signal from said photoelectric detecting means and kept turned on until a signal is applied thereto from a delay circuit connected in said memory-readout circuit; and a gate circuit adapted to produce an output when the output signal from said memory circuit and the sweep signal from said sweep signal generator are applied thereto; said delay circuit being adapted to apply the output signal from said gate signal to said memory circuit after the predetermined time delay to turn off said memory circuit.

3. A counting device as claimed in claim 2, wherein said memory-readout circuit further includes a build-up delay circuit which is adapted to apply said sweep signal from the sweep signal generator to said gate circuit after a predetermined time delay.