US3718502A - Enhancement of diffusion of atoms into a heated substrate by bombardment - Google Patents

Enhancement of diffusion of atoms into a heated substrate by bombardment Download PDF

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US3718502A
US3718502A US00866692A US3718502DA US3718502A US 3718502 A US3718502 A US 3718502A US 00866692 A US00866692 A US 00866692A US 3718502D A US3718502D A US 3718502DA US 3718502 A US3718502 A US 3718502A
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor

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  • This invention describes a method of enhancing the 51 Int. Cl ..B44d 1/18, B44d 1/20 diffusion of atomic Species tried on the Surface of a [58] Field of Search 17/212 933 38 solid substrate into the substrate by elevating the teml 48,1188 H perature of the substrate to permit atoms and vacancies to propagate and then creating vacancies in selected regions of the substrate through bombard- [56] References Cited ment by a beam of protons or other particles, said UNITED STATES PATENTS bombard-merit acting to enhance diffusion of the surface atom species into the substrate at said regions.
  • PATENTEB 75 O sumaora ⁇ 1 5 2 N SUBSTRATE WITH P LAYER PREPARED I As IN FIG 6.
  • This invention describes a method for controlling and enhancing diffusion of atoms into a solid substrate by employing a beam of protons or other particles to raise the apparent temperature of the substrate and more particularly to the use of such a method in the formation of P-N junctions, alloyed contacts and ohmic contacts in a solid substrate and in the control of surface effects and reduction of surface imperfections.
  • Diffusion of atoms into a substrate to form a junction or ohmic contact depends upon the movement of atoms into the crystalline lattice of the substrate.
  • the impurity atoms rest in substitutional lattice sites in the host crystal or substrate.
  • the host atom occupying the site In order for the atoms to diffuse to an adjacent lattice site, the host atom occupying the site must be moved away to create a vacant lattice site and the impurity atom must be given sufficient energy to move into the vacant lattice site.
  • Two energies correspond to these two processes: the host atom must absorb an energy E, to escape from its lattice site, and the impurity atom must absorb an energy E to migrate from its original position into the newly-created vacancy.
  • the diffusion coefficient for the impurity is proportional to the probability P calculated above and can be expressed in the form D D -E' lkT E /k1' I
  • the constants take on the values D my/(hr), E,- 3 eV and E 0.3 eV.
  • D 0.16 V/( Values of D of this magnitude are essential for efficient fabrication of semiconductor devices by the diffusion process, since the depth to which impurity atoms will diffuse from a surface is d-5 VZium where D is the diffusion coefficient and t is the time in hours.
  • electroluminescent diodes in silicon carbide requires the formation of P-N junctions that must be diffused at temperatures of 1,800 2,000C. on account of the very high values of E, that characterize this material. These very high temperatures are difficult to achieve. This makes accurate fabrication difficult and, furthermore, results in devices whose properties are frequently dominated by the crystal imperfections introduced during high temperature diffusion processes rather than the dopant which is introduced.
  • FIGS. 1A 1D show the steps in forming a P-N junction in accordance with the invention.
  • FIG. 2 shows the vacancy concentration profile for two particle beam energies.
  • FIG. 3 shows the impurity profile for boron diffusion in a silicon semiconductor wafer with proton energies of 10 keV.
  • FIG. 4 shows the impurity profile for boron diffusion in a silicon semiconductor wafer with proton energies of 50 keV.
  • FIGS. 5A 5C show forming an inset region in a semiconductor substrate.
  • FIGS. 6A 6C show application of the process employing a mask to define the diffusion region.
  • FIGS. 7A 7B show the steps in forming an N-P-N device in accordance with the invention.
  • FIGS. 8A 8B show the steps in forming an N-P-N device by the use of a single film or layer having two atom species.
  • FIGS. 9A 9B show the steps of forming an inset region with an oxide protected junction.
  • FIGS. 10A 10C show the steps in forming an inset region in a device in which the atom species is captured by protected film.
  • FIGS. 11A 11F show the steps in forming a junction field effect transistor.
  • the substrate may, for example, be a silicon wafer having impurities characterizing N type semiconductor material.
  • the wafer is suitably etched and processed to provide a clean upper surface 11. Thereafter, by thermal deposition, evaporation from an elemental source, chemical deposition, ion implantation or other well known technique to those versed in the art, a shallow layer or film of material 12 containing atom species to be diffused into the semiconductor wafer is applied to the upper surface of the slab, FIG. 1B.
  • the layer of material 12 may, for example, be a relatively thin boron layer which is a P type dopant for silicon.
  • the wafer is then placed in an evacuated chamber and means are provided within the chamber to elevate the temperature of the semiconductor wafer, FIG. 1C.
  • the temperature of the wafer is elevated to a temperature in which the interstitial lattice atoms and lattice vacancies move relatively freely. This is generally well below typical diffusion temperatures, being in the range of 450 700C. and above for silicon, and 360 500C. and above for germanium.
  • the surface of the device is bombarded with protons using conventional isotope separator equipment which delivers protons to the wafer at any desired energy over a wide range of values, for example, between 1 keV to several hundreds keV.
  • the high energy particles create lattice vacancies which tend to diffuse through the structure and enhance the diffusion of the P type boron atoms into the wafer to form the P- Njunction 13, FIG. 1D.
  • the proton bombardment is continued for a time adequate for the surface deposited atom species, boron in this instance, to diffuse to a desired depth thereby forming the P-N junction 13 in the N type silicon substrate.
  • the time required may be 0.5 to 1.5 hours, but can be even shorter than this.
  • the vacancy concentration in the surface layers of the substrate can be increased several orders of magnitude above the value it would have at the substrate temperature in the absence of proton bombardment.
  • the increase in vacancy concentration in the surface layers can be thought of as an increase in the surface temperature of the substrate.
  • Experimental results to be presented later show that the equivalent temperature of the surface layers can be 1,000 l,200C. in a silicon target where the body is maintained at a temperature of only 700C. This permits the atoms predeposited on the surface to diffuse rapidly into the semiconductor until they reach the cooler portions of the target. The. final result is that impurity diffusion can be obtained to a depth determined by the energy of the proton beam.
  • diffusion does not typically occur at depths significantly greater than the range of the protons, nor does it occur on those portions of the surface that may have been masked by standard techniques or on which the beam is not allowed to fall as a result of ion focusing arrangements.
  • V(x) Theoretical techniques exist for computing V(x). I have found that many different forms'for V(x) can be obtained, depending on initial energy of the proton beam, the type of substrate used and the temperature at which the substrate is maintained during the process.
  • V(x) takes the form where A and B are constants that have to do with the efficiency with which energetic protons produce vacancies, u is the range or average distance travelled by a proton in coming to rest in the crystal, and 0' is a socalled range straggling parameter, common in particle physics, which accounts for the fact that all protons do not suffer exactly the same sequence of collisions, so there is a distribution in the stopping points for the protons about the average.
  • a more precise form for V(x) can be obtained by correcting p. and 0' for vacancy diffusion effects.
  • V(x) takes on the form labelled 10 keV in FIG. 2
  • the vacancy concentration in the surface layers of the target will take on a value substantially different from the thermal equilibrium value.
  • the diffusion constant will take on a large value.
  • doping atoms predeposited in the surface will diffuse rapidly into the surface layers until they reach a depth where V(x) falls rapidly back to its thermal equilibrium value.
  • the high vacancy concentration in the surface layers is equivalent to a very high temperature in the surface layers. Atoms can diffuse rapidly through this highly agitated region, but they stop abruptly when they reach the cooler" portions of the target (i.e., portions not affected by the proton beam).
  • FIG. 3 Typical experimental impurity profiles for bombardment-enhanced diffusion of boron into silicon are shown in FIG. 3 for a 10 Kev, 40 nanoampere proton beam and several different diffusion times. It will be clear to persons skilled in the art that the diffusion constant for boron in silicon has been increased many orders of magnitude over its value at the substrate tem perature of 700C.
  • both abrupt impurity profiles such as those shown in FIG. 3 and gradually graded impurity profiles such as those shown in FIG. 4 are important in the semiconductor industry; and further that a great variety of profiles in addition to those shown can be generated by employing a sequence of different proton bombardment cycles and substrates temperatures.
  • the bombarding particles need not be protons (e.g., electrons, neutrons, helium atoms or other species could be used); though protons have the advantage of producing vacancies at depths of practical interest more efficiently than other types of bombarding species.
  • FIG. 5 shows the formation of an inset P-N junction in a substrate.
  • the N type substrate, FIG. 5, is provided with a layer containing atoms of the species which is to be diffused into the substrate, for example, a layer of P type material such as boron.
  • the substrate is then heated to a temperature in which the interstitial lattice atoms and lattice vacancies move freely and it is then bombarded with high energy particles, such as protons, over the selected area 14 as, for example, by controlling the proton beam to only impinge upon the selected area, by masking as will be presently described or other suitable means.
  • the bombardment causes the apparent temperature in the selected area or region 14 whereby atoms from the P type layer diffuse into the substrate to a depth corresponding generally to the depth of proton or particle penetration. Thereafter, the substrate may be treated by etching (not shown) to remove the layer and leave a planar P-Njunction in the device.
  • FIG. 6 illustrates the above process and shows the use of a mask for defining the area which is bombarded.
  • a substrate with a layer containing the desired species of atoms which are to be diffused.
  • a mask applied over the N type layer with an opening 15.
  • the mask may be relatively thick oxide, metal or the like which prevents penetration of the beam particles into the substrate in the area underlying the mask.
  • the substrate is heated and the complete surface is bombarded to provide the N type diffusion shown in FIG. 6C.
  • FIG. 7 illustrates generally the use of the process in the formation of an N-P-N junction.
  • FIG. 7A there is shown a properly treated substrate containing a P type layer.
  • the substrate is then heated and bombarded over a selected area to form an inset P type region 16.
  • a layer containing impurity atoms of opposite conductivity type, for example, phosphorus atoms FIG. 7C.
  • the wafer is then again heated and bombarded over a selected smaller region or area to form another inset region 17.
  • the wafer can then be treated as, for example, by etching to remove the surface layers and leave a device of the type shown in FIG. 7E.
  • FIG. 8A shows an N type substrate provided with a layer containing two atom species having different diffusion constants. Thereafter, the substrate is heated and a selected area is bombarded with high energy particles and the two atom species diffuse into the N type substrate at different rates to form N and P inset regions in the substrate thereby forming an N-P-N device.
  • FIGS. 9A 9E illustrate the process in connection with a semiconductor device having an oxide protected junction.
  • FIG. 9A shows an N type substrate. Thereafter, the substrate is provided with an oxide layer 21, FIG. 9B. The oxide layer is etched to form a window or opening 22, FIG. 9C, and thereafter, there is deposited a P type layer which may, for example, be boron and which overlies the oxide 21 and is in contact with the substrate at the window 22. The wafer or substrate is then heated and bombarded to provide diffusion into the substrate to form an inset P type region 23. The wafer may then be suitably etched and diffused to form a P-N-P device having oxide protected junctions.
  • a P type layer which may, for example, be boron and which overlies the oxide 21 and is in contact with the substrate at the window 22.
  • the wafer or substrate is then heated and bombarded to provide diffusion into the substrate to form an inset P type region 23.
  • the wafer may then be suitably etched and diffused to form a
  • FIG. 10 illustrates another embodiment of the invention.
  • material such as Group III-V and Group II-VI compounds of the lattice species may have such high vapor pressure that the lattice species escape from the surface during processing so the surface must be protected.
  • the substrate 24 has applied thereto a layer containing the desired impurity atoms 25.
  • a layer 26 which may be a relatively thick protective oxide layer or the like is deposited over the impurity dopant layer 25 to prevent escape of lattice species.
  • the device is then heated and bombarded by suitable high energy particles such as proton particles to cause diffusion of the layer 25 in the region 2511 into the underlying wafer.
  • suitable high energy particles such as proton particles to cause diffusion of the layer 25 in the region 2511 into the underlying wafer.
  • the proton beam completely penetrates the protective layer, elevates the temperature of the desired area whereby diffusion of the impurity in layer 25 is enhanced into the material, while at the same time the protective layer prevents the escape of lattice species due to high vapor pressures.
  • a P layer 26 is first formed on a lightly doped N substrate 27 as described in FIG. 6.
  • An oxide or other protective mask 28 is then placed over selected areas of the surface as shown in FIG. 11B, and a layer 29 containing P type dopant atoms is deposited.
  • the material is then heated and bombarded to diffuse the P type dopant into the previously diffused P layer, producing heavily doped P+ source 30 and drain 31 contacts.
  • the surface oxide and residual dopant are then etched away and a second oxide layer 32 is placed over the surface in the position shown in FIG. 11E.
  • a layer 33 containing N type dopant atoms is then deposited and the material is heated and bombarded to produce a heavily doped N+ gate contact 34, yielding the junction field effect transistor shown in FIG. 11F.
  • a depletion mode metal-oxide-semiconductor (MOS) field effect transistor can be fabricated by depositing an oxide layer over the structure shown in FIG. 11D, leaving windows over the P+ regions to make ohmic contact to the source and drain regions, and then, using well known masking and evaporation techniques, place an appropriate metallic gate electrode to lie parallel to the source and drain contacts overlying the oxide layer in the region between said source and drain contacts.
  • MOS metal-oxide-semiconductor
  • N and P type dopants can be diffused into a semiconductor substrate of either N or P type conductivity.
  • the process of the present invention can now be equally used for making both P-N junctions, diffused resistors and ohmic contacts in a wide variety of semiconductor materials. Materials such as copper, gold, platinum, lithium and chromium, that are commonly introduced into semiconductors for the purpose of controlling carrier lifetime or for producing high resistivity material by impurity compensation, can be diffused to precise depths in selected areas through use of my present enhanced diffusion process.
  • the process can be repeated several times with different dopants to form multiple N and P type layers such as are required in the fabrication of transistors, integrated circuits and silicon controlled rectifiers and the like.
  • Conventional oxide or nitride masking may be utilized on the wafer before the dopant is deposited so that predeposition and diffusion of the impurity can be limited to those areas where it is desired, or ultimately the ion or particle bean can be focused into selected areas of slabs so that the selective diffusion can occur without requiring the fabrication of masks.
  • the process of the present invention can be employed to enhance diffusion of atoms into metals as well as semiconductors.
  • the process of the present invention can also be used to repair heavy damage that occurs during an ion implantation of a heavy atom.
  • a heavy atom for example, if boron is implanted into silicon at an energy of 80 keV, and the material is annealed at 625C, either during the implantation of afterward, then only percent of the boron atoms will have annealed into substitutional positions in the crystal, where they produce electrical conductivity. If the silicon is heated to l,l00C., nearly all of the boron atoms will anneal into substitutional positions and, therefore, be electrically active in the crystal.
  • the present invention can be used together with a low temperature ion implantation process to achieve an equivalent high annealing temperature in the layers that contain the implanted species without raising the substrate to high temperatures.
  • a low temperature ion implantation process can be performed into a silicon wafer that is held at a temperature of 700C.
  • the boron beam may be switched off and a proton beam introduced, with the dose and energy of the protons being selected to provide an equivalent temperature of approximately l,l00C. in the region where the implanted boron atoms lie.
  • the proton beam is applied for an adequate time min.) to ensure that the boron atoms will have annealed into proper lattice positions.
  • Another application of this same type is related to repairing damage produced at the interface between silicon and silicon-dioxide during preparation of the oxide. It is known by persons skilled in the art of silicon planar technology that when a surface layer of silicon dioxide is formed on a silicon substrate by any of the conventional techniques, undesirable surface states remain until the oxide layer has been annealed at an elevated temperature on the order of 1,050C. Using the process of the present invention, the interfacial area between the silicon and silicon dioxide, which contains the undesirable surface states, can be annealed without raising the substrate to high temperatures that create imperfections in the substrate crystal.
  • the method of enhancing diffusion of selected atom species in a solid semiconductor substrate which comprises elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in the substrate, providing said selected atom species at a surface of the substrate, and bombarding at least one surface of said substrate while the temperature is elevated with a beam of non-dopant particles selected such that the particles collide with atoms of the substrate to dislodge the atoms from their lattice positions and create lattice vacancies which move freely in the substrate, said temperature being such that said lattice vacancies can move to interact with said selected atom species to cause atoms of the species to diffuse in said substrate, said elevated temperature and particles further being selected such that the bombarding particles do not cause gross damage in the substrate at said elevated temperature.
  • the method as in claim 2 including additionally providing a mask having one or more openings on said surface whereby to intercept particles and prevent the formation of lattice vacancies in the substrate beneath the mask and permit particles to pass through said openings to bombard the substrate and form lattice vacancies in the region of said openings by dislodging atoms from their lattice positions.
  • said particle beam comprises a proton beam having energies above 1 keV.
  • the method of enhancing diffusion of selected atom species into a semiconductor substrate which comprises the steps of predepositing on at least one surface of said substrate a layer of material containing the selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in the substrate, said temperature being below the temperature which would produce significant diffusion of the selected atom species into the substrate, and simultaneously bombarding at said surface selected areas of the substrate with a non-dopant particle beam for the substrate so that the particles collide with atoms in the substrate to dislodge atoms from their lattice position and create lattice vacancies which move freely in the substrate at said elevated temperature to interact with said selected atom species at said elevated temperature to enhance diffusion of the selected atom species from the surface into the substrate, said temperature and particle beam being such that no gross damage is caused in the substrate.
  • said substrate is semiconductor material characterizing one conductivity type and said layer contains atom species characterizing both said one conductivity type and an opposite conductivity type, said atom species of opposite conductivity type having a higher diffusion coefficient than said atom species of said one conductivity type whereby said atom species of said opposite conductivity type diffuses further into said substrate than the atom species of said one conductivity type to form two rectifyingjunctions in said substrate.
  • the predeposited layer of material contains atomic species that act to compensate the doping effect provided by atomic species previously introduced into the semiconductor.
  • the method of enhancing diffusion of selected atom species in a semiconductor substrate which comprises the steps of providing said selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in said substrate and bombarding at least one surface of said substrate while the temperature is elevated with a non-dopant beam of particles selected such that the particles collide with the atoms in the substrate to dislodge atoms from the lattice positions, said temperature selected whereby no gross damage is caused in the substrate by said particle beam, said particle beam serving to create lattice vacancies which move freely in the substrate at said elevated temperature to interact with the atom species to enhance the diffusion of said selected atom species in the substrate.

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Abstract

This invention describes a method of enhancing the diffusion of atomic species carried on the surface of a solid substrate into the substrate by elevating the temperature of the substrate to permit atoms and vacancies to propagate and then creating vacancies in selected regions of the substrate through bombardment by a beam of protons or other particles, said bombard-ment acting to enhance diffusion of the surface atom species into the substrate at said regions.

Description

O United States Patent [1 1 [111 3,718,502
Gibbons [4 1 Feb. 27, 1973 ENHANCEMENT 0F DIFFUSION 0F 3,514,348 5 1970 Ku ..148/188 ATOMS INTQA HEATED SUBSTRATE 3,481,776 12/1969 Manchester ..117/212 3,420,719 1 1969 Potts ..148/188 BY BOMBARDMENT 3,351,503 11/1967 Fotland ..148/188 [76] Inventor: James F. Gibbons, 735 De Soto Drive, Palo Alto, Calif. 94303 Primary Examiner-Ralph S. Kendall Assistant Examiner-M. F. Esposito [22] Flled' 1969 Attorney-Flehr, Hohbach, Test, Albn'tton and Her- [21] Appl. No.: 866,692 bert 57 ABSTRACT [52] US. Cl ..117/212, 117/38, 117/47 H, 1
117/213, 148/183, 148/188, 148/191 This invention describes a method of enhancing the 51 Int. Cl ..B44d 1/18, B44d 1/20 diffusion of atomic Species tried on the Surface of a [58] Field of Search 17/212 933 38 solid substrate into the substrate by elevating the teml 48,1188 H perature of the substrate to permit atoms and vacancies to propagate and then creating vacancies in selected regions of the substrate through bombard- [56] References Cited ment by a beam of protons or other particles, said UNITED STATES PATENTS bombard-merit acting to enhance diffusion of the surface atom species into the substrate at said regions. 3,562,022 2/1971 Shifrin ..148/188 3,523,042 8/1970 Bower et a1. ..148/188 29 Claims, 11 Drawing Figures S U B S T R ATE 12 {P I\\\\\\\\\\\\\\\'\\\ l DOPANT LAYER B CONTAINING DESIRED N ATO Ms 6 N H E AT B O M BA R D W 1T H D j 1 H IGH E N E R GY 13 h PROTONS VACANCY CONCENTRATION, cm
PAIEIITEDFEBZTIEIYS SHEET 10F 8 G I N SUBSTRATE DOPANT LAYER CONTAINING DESIRED ATOMS HEAT BOMBARD WITH 0 HIGH ENERGY N PROTONS I I I I I I I I VACANCY CONCENTRATION 5 Ev PROFILE DISTANCE FROM SURFACE,PM v INVENTOR I JAMES F GIBBONS 2 BY F/ 6 W M AI I'ORN FYi PATEN'IIEIJ SHEET 2 0F 8 6 TI O C ll SWIIO I l L O m M R R I U. HH E Ah M i; O I m T +QX .l C O O O/ *F X D I RWS m U N D O V M N m 2 W U. O I m II B M II D E m m m w m 5 M m m m m m m w zo ESzou Exams:
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PATENTEB 75 8, O sumaora {1 5 2 N SUBSTRATE WITH P LAYER PREPARED I As IN FIG 6.
PROTECTIVE MASK OXlDE OR OTHER I LAYER CONTAINING {JP TYPE DOPANT ATOMS N TYPE DOPANT OXIDE JAMES F. G BBONS I NVENTOR,
w) W ATTORNEYS ENHANCEMENT OF DIFFUSION OF ATOMS INTO A HEATED SUBSTRATE BY BOMBARDMENT BACKGROUND OF THE INVENTION This invention describes a method for controlling and enhancing diffusion of atoms into a solid substrate by employing a beam of protons or other particles to raise the apparent temperature of the substrate and more particularly to the use of such a method in the formation of P-N junctions, alloyed contacts and ohmic contacts in a solid substrate and in the control of surface effects and reduction of surface imperfections.
In the prior art diffusion of atomic species predeposited on a semiconductor surface has, in general, been carried out at relatively high temperatures. As a consequence, there has been resulting damage and imperfections formed, both in the diffused layers and elsewhere in the'substrate, said damage and imperfections having detrimental effects on the characteristics of devices produced by the conventional diffusion process. This invention permits diffusion to occur without raising the substrate to the high temperatures that produce detrimental effects.
Diffusion of atoms into a substrate to form a junction or ohmic contact, in general, depends upon the movement of atoms into the crystalline lattice of the substrate. In general, the impurity atoms rest in substitutional lattice sites in the host crystal or substrate. In order for the atoms to diffuse to an adjacent lattice site, the host atom occupying the site must be moved away to create a vacant lattice site and the impurity atom must be given sufficient energy to move into the vacant lattice site. Two energies correspond to these two processes: the host atom must absorb an energy E, to escape from its lattice site, and the impurity atom must absorb an energy E to migrate from its original position into the newly-created vacancy.
In a thermally-activated diffusion process, it can be shown that the probability for the host atom to absorb an energy E is proportional to where k is Boltzmanns constant and T is the absolute temperature; and similarly that the probability for the impurity atom to absorb an energy E,, is proportional The probability P t h at both of these events will occur is proportional to the product of the individual probabilities, or
The diffusion coefficient for the impurity is proportional to the probability P calculated above and can be expressed in the form D D -E' lkT E /k1' I As an example, in a conventional diffusion of boron into silicon, the constants take on the values D my/(hr), E,- 3 eV and E 0.3 eV. As a result, it is necessary to raise the temperature of the silicon to l,l0OC. to achieve a diffusion constant D 0.16 V/( Values of D of this magnitude are essential for efficient fabrication of semiconductor devices by the diffusion process, since the depth to which impurity atoms will diffuse from a surface is d-5 VZium where D is the diffusion coefficient and t is the time in hours. To achieve boron doping to a depth d of lam in a silicon substrate, therefore, requires that the silicon be held at 1,100C. for 1.5 hours. If a substantially lower temperature is used, for example, 700C, the value of D given by Eq. (1) becomes so small that prohibitively long processing times are required.
It is clear from the above description that large values of D are useful if diffusion processing is to be accomplished in reasonable times. It is also clear that, if the diffusion process if thermally activated, large values of D can only be achieved by increasing T to large values. In some cases this is acceptable, though many disadvantages can be cited. For instance, crystal imperfections form more easily and residual dislocation loops increase in size more rapidly at high temperatures than they do at low temperatures. Hence, in a thermally activated diffusion, the process that permits the desired species to diffuse also creates undesirable imperfections in the crystal. These imperfections may affect the diffusion of the desired species unfavorably and may also act as trapping centers for carriers. The trapping centers produce short carrier lifetimes, and, in general, have deleterious effects on the performance of devices such as transistors and integrated circuits, and particularly photodiodes, phototransistors and silicon vidicons.
Furthermore, the fabrication of electroluminescent diodes in silicon carbide requires the formation of P-N junctions that must be diffused at temperatures of 1,800 2,000C. on account of the very high values of E, that characterize this material. These very high temperatures are difficult to achieve. This makes accurate fabrication difficult and, furthermore, results in devices whose properties are frequently dominated by the crystal imperfections introduced during high temperature diffusion processes rather than the dopant which is introduced.
OBJECTS AND SUMMARY OF THE INVENTION It is a general object of the present invention to provide a method of enhancing the diffusion of desired atom species into a solid substrate.
It is another object of the present invention to provide a method of diffusing desired atom species into a solid substrate at relatively low temperatures.
It is another object of the present invention to provide a method of forming P-N junctions, ohmic and alloyed contacts in a solid substrate by enhancing diffusion through the use of a proton or other high energy beam.
It is a further object of the present invention to provide a method of treating semiconductor substrate to control electronic properties characterizing the interfaces between the substrate and the oxide surfaces forming interfaces therewith.
It is a further object of the present invention to provide a method in which energetic protons and other particles create lattice vacancies for enhancing the diffusion process.
The foregoing and other objects of the invention are achieved by subjecting a solid substrate having a thin surface film containing the desired atom species to be diffused into the substrate to bombardment by energetic particles such as protons which create lattice vacancies and enhance the diffusion of the atom species into the substrate in those areas of the substrate where diffusion of the atom species into the substrate is desired.
The foregoing and other objects of the invention may become more clearly apparent from the following description taken in connection with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A 1D show the steps in forming a P-N junction in accordance with the invention.
FIG. 2 shows the vacancy concentration profile for two particle beam energies.
FIG. 3 shows the impurity profile for boron diffusion in a silicon semiconductor wafer with proton energies of 10 keV.
FIG. 4 shows the impurity profile for boron diffusion in a silicon semiconductor wafer with proton energies of 50 keV.
FIGS. 5A 5C show forming an inset region in a semiconductor substrate.
FIGS. 6A 6C show application of the process employing a mask to define the diffusion region.
FIGS. 7A 7B show the steps in forming an N-P-N device in accordance with the invention.
FIGS. 8A 8B show the steps in forming an N-P-N device by the use of a single film or layer having two atom species.
FIGS. 9A 9B show the steps of forming an inset region with an oxide protected junction.
FIGS. 10A 10C show the steps in forming an inset region in a device in which the atom species is captured by protected film.
FIGS. 11A 11F show the steps in forming a junction field effect transistor.
DESCRIPTION OF PREFERRED EMBODIMENTS The method of the present invention will be first described in connection with the formation of a P-N junction in a semiconductor substrate. Referring to FIG. 1A, the substrate may, for example, be a silicon wafer having impurities characterizing N type semiconductor material. The wafer is suitably etched and processed to provide a clean upper surface 11. Thereafter, by thermal deposition, evaporation from an elemental source, chemical deposition, ion implantation or other well known technique to those versed in the art, a shallow layer or film of material 12 containing atom species to be diffused into the semiconductor wafer is applied to the upper surface of the slab, FIG. 1B. In order to form a P-N junction, in silicon, the layer of material 12 may, for example, be a relatively thin boron layer which is a P type dopant for silicon. The wafer is then placed in an evacuated chamber and means are provided within the chamber to elevate the temperature of the semiconductor wafer, FIG. 1C. Preferably, the temperature of the wafer is elevated to a temperature in which the interstitial lattice atoms and lattice vacancies move relatively freely. This is generally well below typical diffusion temperatures, being in the range of 450 700C. and above for silicon, and 360 500C. and above for germanium. Thereafter, the surface of the device is bombarded with protons using conventional isotope separator equipment which delivers protons to the wafer at any desired energy over a wide range of values, for example, between 1 keV to several hundreds keV. The high energy particles create lattice vacancies which tend to diffuse through the structure and enhance the diffusion of the P type boron atoms into the wafer to form the P- Njunction 13, FIG. 1D.
The proton bombardment is continued for a time adequate for the surface deposited atom species, boron in this instance, to diffuse to a desired depth thereby forming the P-N junction 13 in the N type silicon substrate. Typically, the time required may be 0.5 to 1.5 hours, but can be even shorter than this.
It is, of course, apparent that by starting with a P type substrate and providing an N type layer or film and elevating the temperature and bombarding the wafer, a P-N junction having a diffused N type region with a P type substrate is formed. Furthermore, by applying a layer containing atom species of the type characterizing the conductivity type of the slab, an ohmic connection can be formed to the upper surface of the wafer. The ohmic contact can have a relatively high impurity concentration thereby providing an ohmic contact having a very low resistance.
Operation of the invention to enhance diffusion can be explained qualitatively as follows. The energetic protons enter the target where they occasionally collide with atoms of the host crystal (substrate) and dislodge them from their lattice positions. Both the dislodged host atoms and the resulting vacancies in the host crystal diffuse away from their point of creation, propagating a region of high defect concentration both toward the surface and deeper into the body of the crystal. An adequate propagation effect can be achieved by maintaining the crystal (substrate) at an elevated temperature. The temperature required will depend on the substrate, being in the range of 450 700C. and above for silicon, 350 500C. and above for germanium. The propagation effect is necessary since otherwise dislodged host atoms may simply fall back into the lattice sites from which they came with no net effect; or possibly the vacancies produced from damage clusters, dislocation loops or other crystal imperfections.
When conditions for propagation of the bombardment-produced vacancies are favorable, however, the vacancy concentration in the surface layers of the substrate can be increased several orders of magnitude above the value it would have at the substrate temperature in the absence of proton bombardment. For qualitative purposes the increase in vacancy concentration in the surface layers can be thought of as an increase in the surface temperature of the substrate. Experimental results to be presented later show that the equivalent temperature of the surface layers can be 1,000 l,200C. in a silicon target where the body is maintained at a temperature of only 700C. This permits the atoms predeposited on the surface to diffuse rapidly into the semiconductor until they reach the cooler portions of the target. The. final result is that impurity diffusion can be obtained to a depth determined by the energy of the proton beam.
It should be mentioned that diffusion does not typically occur at depths significantly greater than the range of the protons, nor does it occur on those portions of the surface that may have been masked by standard techniques or on which the beam is not allowed to fall as a result of ion focusing arrangements.
A variety of different impurity profiles can be obtained by proper choice of proton beam energy, dose rate, and diffusion time, as will be shown later. In every case permanent damage in the body of the target is avoided so the electronic properties and strength of the material outside the region of diffusion are far superior to what they would be if the predeposited species were driven into the target by a conventional thermally activated high temperature diffusion process.
Thus, the energetic protons create the lattice vacancies required for diffusion. The mathematical effect is that the exponential involving E; will be eliminated in Eq. (I) with the result that D a D e V(x) 2. where V(x) is the vacancy concentration profile produced by the bombarding protons. This is a very important modification since it is the large value of E, in the exponent of Eq. (I) that requires that a high temperature be reached before practical values of the diffusion coefficient can be achieved. By controlling V(x), D can be controlled without raising the substrate to temperatures that produce imperfections or to diffusion temperatures which are difficult to achieve for certain materials such as silicon carbide.
Theoretical techniques exist for computing V(x). I have found that many different forms'for V(x) can be obtained, depending on initial energy of the proton beam, the type of substrate used and the temperature at which the substrate is maintained during the process. To a first approximation V(x) takes the form where A and B are constants that have to do with the efficiency with which energetic protons produce vacancies, u is the range or average distance travelled by a proton in coming to rest in the crystal, and 0' is a socalled range straggling parameter, common in particle physics, which accounts for the fact that all protons do not suffer exactly the same sequence of collisions, so there is a distribution in the stopping points for the protons about the average. A more precise form for V(x) can be obtained by correcting p. and 0' for vacancy diffusion effects.
Precise computations of the vacancy concentration profiles including all vacancy diffusion effects have been made for a silicon target using two different proton energies with the results shown in FIG. 2. For the case of keV protons, the range p. of the protons is small (0.15 p. m), so that the vacancies are all produced near the surface. The curve labelled 50 keV shows V(x) for a higher energy proton beam where the proton range is deeper 0.55 n m).
A precise mathematical form for the diffusion coefficient D can be obtained by substituting these forms for V(x) into Eq. (2). It is then possible to solve the impuri ty diffusion equation using these spatially varying diffusion constants to obtain precise predictions of the impurity doping profiles which would be obtained. However, for present purposes, it will suffice to give a qualitative picture.
If a relatively low energy proton beam is used, so that V(x) takes on the form labelled 10 keV in FIG. 2, only the vacancy concentration in the surface layers of the target will take on a value substantially different from the thermal equilibrium value. Where the vacancy concentration is high, the diffusion constant will take on a large value. As a result, doping atoms predeposited in the surface will diffuse rapidly into the surface layers until they reach a depth where V(x) falls rapidly back to its thermal equilibrium value. To a first approximation, the high vacancy concentration in the surface layers is equivalent to a very high temperature in the surface layers. Atoms can diffuse rapidly through this highly agitated region, but they stop abruptly when they reach the cooler" portions of the target (i.e., portions not affected by the proton beam).
Typical experimental impurity profiles for bombardment-enhanced diffusion of boron into silicon are shown in FIG. 3 for a 10 Kev, 40 nanoampere proton beam and several different diffusion times. It will be clear to persons skilled in the art that the diffusion constant for boron in silicon has been increased many orders of magnitude over its value at the substrate tem perature of 700C.
A similar analysis can be made for a vacancy concentration profile of the form shown in FIG. 2 for a 50 KeV proton beam. Here the equivalent high temperature layer is inside the crystal rather than on its surface, so the diffusion constant will be much higher inside the substrate than it is on the surface. This results in very gradually graded impurity profiles such as those shown in FIG. 4.
It should be noted that both abrupt impurity profiles such as those shown in FIG. 3 and gradually graded impurity profiles such as those shown in FIG. 4 are important in the semiconductor industry; and further that a great variety of profiles in addition to those shown can be generated by employing a sequence of different proton bombardment cycles and substrates temperatures. Furthermore, the bombarding particles need not be protons (e.g., electrons, neutrons, helium atoms or other species could be used); though protons have the advantage of producing vacancies at depths of practical interest more efficiently than other types of bombarding species.
The following description and figures are various examples of the use of the process in forming devices. These are only illustrative of the wide application of the process. One skilled in the art can readily adapt the process to enhance various diffusion processes.
FIG. 5 shows the formation of an inset P-N junction in a substrate. The N type substrate, FIG. 5, is provided with a layer containing atoms of the species which is to be diffused into the substrate, for example, a layer of P type material such as boron. The substrate is then heated to a temperature in which the interstitial lattice atoms and lattice vacancies move freely and it is then bombarded with high energy particles, such as protons, over the selected area 14 as, for example, by controlling the proton beam to only impinge upon the selected area, by masking as will be presently described or other suitable means. The bombardment causes the apparent temperature in the selected area or region 14 whereby atoms from the P type layer diffuse into the substrate to a depth corresponding generally to the depth of proton or particle penetration. Thereafter, the substrate may be treated by etching (not shown) to remove the layer and leave a planar P-Njunction in the device.
FIG. 6 illustrates the above process and shows the use of a mask for defining the area which is bombarded. Thus, in FIG. 6A, there is shown a substrate with a layer containing the desired species of atoms which are to be diffused. In FIG. 6B, there is shown a mask applied over the N type layer with an opening 15. The mask may be relatively thick oxide, metal or the like which prevents penetration of the beam particles into the substrate in the area underlying the mask. Thereafter, the substrate is heated and the complete surface is bombarded to provide the N type diffusion shown in FIG. 6C.
FIG. 7 illustrates generally the use of the process in the formation of an N-P-N junction. Thus, in FIG. 7A, there is shown a properly treated substrate containing a P type layer. The substrate is then heated and bombarded over a selected area to form an inset P type region 16. Thereafter, there is provided a layer containing impurity atoms of opposite conductivity type, for example, phosphorus atoms, FIG. 7C. The wafer is then again heated and bombarded over a selected smaller region or area to form another inset region 17. The wafer can then be treated as, for example, by etching to remove the surface layers and leave a device of the type shown in FIG. 7E.
FIG. 8A shows an N type substrate provided with a layer containing two atom species having different diffusion constants. Thereafter, the substrate is heated and a selected area is bombarded with high energy particles and the two atom species diffuse into the N type substrate at different rates to form N and P inset regions in the substrate thereby forming an N-P-N device.
FIGS. 9A 9E illustrate the process in connection with a semiconductor device having an oxide protected junction. FIG. 9A shows an N type substrate. Thereafter, the substrate is provided with an oxide layer 21, FIG. 9B. The oxide layer is etched to form a window or opening 22, FIG. 9C, and thereafter, there is deposited a P type layer which may, for example, be boron and which overlies the oxide 21 and is in contact with the substrate at the window 22. The wafer or substrate is then heated and bombarded to provide diffusion into the substrate to form an inset P type region 23. The wafer may then be suitably etched and diffused to form a P-N-P device having oxide protected junctions.
FIG. 10 illustrates another embodiment of the invention. In certain applications, for example, in the fabrication of ohmic contacts and P-Njunctions on material such as Group III-V and Group II-VI compounds of the lattice species may have such high vapor pressure that the lattice species escape from the surface during processing so the surface must be protected. In the example shown in FIG. 10, the substrate 24 has applied thereto a layer containing the desired impurity atoms 25. Thereafter, a layer 26 which may be a relatively thick protective oxide layer or the like is deposited over the impurity dopant layer 25 to prevent escape of lattice species. The device is then heated and bombarded by suitable high energy particles such as proton particles to cause diffusion of the layer 25 in the region 2511 into the underlying wafer. Thus, the proton beam completely penetrates the protective layer, elevates the temperature of the desired area whereby diffusion of the impurity in layer 25 is enhanced into the material, while at the same time the protective layer prevents the escape of lattice species due to high vapor pressures.
It is, of course, apparent that the method of the present invention can also be applied to the formation of field effect transistors and the like. An example of the application of the process in the formation of field effect transistors is shown in FIGS. 11A 11F.
A P layer 26 is first formed on a lightly doped N substrate 27 as described in FIG. 6. An oxide or other protective mask 28 is then placed over selected areas of the surface as shown in FIG. 11B, and a layer 29 containing P type dopant atoms is deposited. The material is then heated and bombarded to diffuse the P type dopant into the previously diffused P layer, producing heavily doped P+ source 30 and drain 31 contacts. The surface oxide and residual dopant are then etched away and a second oxide layer 32 is placed over the surface in the position shown in FIG. 11E. A layer 33 containing N type dopant atoms is then deposited and the material is heated and bombarded to produce a heavily doped N+ gate contact 34, yielding the junction field effect transistor shown in FIG. 11F. Alternately, a depletion mode metal-oxide-semiconductor (MOS) field effect transistor can be fabricated by depositing an oxide layer over the structure shown in FIG. 11D, leaving windows over the P+ regions to make ohmic contact to the source and drain regions, and then, using well known masking and evaporation techniques, place an appropriate metallic gate electrode to lie parallel to the source and drain contacts overlying the oxide layer in the region between said source and drain contacts.
From the foregoing description and explanation, it will be clear to those versed in the art that both N and P type dopants can be diffused into a semiconductor substrate of either N or P type conductivity. The process of the present invention can now be equally used for making both P-N junctions, diffused resistors and ohmic contacts in a wide variety of semiconductor materials. Materials such as copper, gold, platinum, lithium and chromium, that are commonly introduced into semiconductors for the purpose of controlling carrier lifetime or for producing high resistivity material by impurity compensation, can be diffused to precise depths in selected areas through use of my present enhanced diffusion process. The process can be repeated several times with different dopants to form multiple N and P type layers such as are required in the fabrication of transistors, integrated circuits and silicon controlled rectifiers and the like. Conventional oxide or nitride masking may be utilized on the wafer before the dopant is deposited so that predeposition and diffusion of the impurity can be limited to those areas where it is desired, or ultimately the ion or particle bean can be focused into selected areas of slabs so that the selective diffusion can occur without requiring the fabrication of masks. Furthermore, the process of the present invention can be employed to enhance diffusion of atoms into metals as well as semiconductors.
The process of the present invention can also be used to repair heavy damage that occurs during an ion implantation of a heavy atom. Thus, for example, if boron is implanted into silicon at an energy of 80 keV, and the material is annealed at 625C, either during the implantation of afterward, then only percent of the boron atoms will have annealed into substitutional positions in the crystal, where they produce electrical conductivity. If the silicon is heated to l,l00C., nearly all of the boron atoms will anneal into substitutional positions and, therefore, be electrically active in the crystal.
However, one of the major advantages sought in the ion implantation process is the possibility of processing semiconductor wafers at low temperatures. Therefore, annealing the crystal at 1,100C. defeats one of the major reasons for introducing dopant atoms by ion implantation.
From the previous description of the present invention, it will be clear that the present invention can be used together with a low temperature ion implantation process to achieve an equivalent high annealing temperature in the layers that contain the implanted species without raising the substrate to high temperatures. For example, an 80 keV boron implantation can be performed into a silicon wafer that is held at a temperature of 700C. When sufficient boron ions have been implanted to achieve the desired conductivity, the boron beam may be switched off and a proton beam introduced, with the dose and energy of the protons being selected to provide an equivalent temperature of approximately l,l00C. in the region where the implanted boron atoms lie. The proton beam is applied for an adequate time min.) to ensure that the boron atoms will have annealed into proper lattice positions.
Another application of this same type is related to repairing damage produced at the interface between silicon and silicon-dioxide during preparation of the oxide. It is known by persons skilled in the art of silicon planar technology that when a surface layer of silicon dioxide is formed on a silicon substrate by any of the conventional techniques, undesirable surface states remain until the oxide layer has been annealed at an elevated temperature on the order of 1,050C. Using the process of the present invention, the interfacial area between the silicon and silicon dioxide, which contains the undesirable surface states, can be annealed without raising the substrate to high temperatures that create imperfections in the substrate crystal.
Having thus described the preferred embodiments of the invention and set forth the basic steps of the process, it is not intended that the description be limited except as may be required by the appended claims.
Iclaim:
l. The method of enhancing diffusion of selected atom species in a solid semiconductor substrate which comprises elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in the substrate, providing said selected atom species at a surface of the substrate, and bombarding at least one surface of said substrate while the temperature is elevated with a beam of non-dopant particles selected such that the particles collide with atoms of the substrate to dislodge the atoms from their lattice positions and create lattice vacancies which move freely in the substrate, said temperature being such that said lattice vacancies can move to interact with said selected atom species to cause atoms of the species to diffuse in said substrate, said elevated temperature and particles further being selected such that the bombarding particles do not cause gross damage in the substrate at said elevated temperature.
2. The method as in claim 1 wherein said temperature is below the temperature which would produce significant diffusion of atomic species in the solid substrate.
3. The method as in claim 2 in which said selected atom species at a surface of the substrate is provided by the additional step of predepositing on said surface a layer of material containing the selected atom species which is to be diffused into the substrate.
4. The method as in claim 2 wherein said substrate is silicon and said predetermined temperature is in the range of 450 700C.
5. The method as in claim 2 wherein said substrate is germanium and the elevated temperature is in the range of 360 500C.
6. The method as in claim 3 wherein said predeposited layer is deposited only over selected areas of the surface.
7. The method as in claim 2 including additionally providing a mask having one or more openings on said surface whereby to intercept particles and prevent the formation of lattice vacancies in the substrate beneath the mask and permit particles to pass through said openings to bombard the substrate and form lattice vacancies in the region of said openings by dislodging atoms from their lattice positions.
8. The method as in claim 2 wherein selected areas are bombarded by focusing and directing the particle beam.
9. The method as in claim 2 wherein said particle beam comprises a proton beam having energies above 1 keV.
10. The method as in claim 1 wherein the damage previously existing in the semiconductor is annealed on account of the enhanced diffusion.
11. The method as in claim 10 wherein the damage is produced by introducing the atomic species using the ion implantation technique.
12. The method as in claim 10 wherein the damage is produced during the formation of an oxide layer or other protective coating on said semiconductor surface.
13. The method as in claim 10 wherein a protective layer is applied over said semiconductor to inhibit the escape of atomic species from the surface during the enhanced diffusion.
14. The method of enhancing diffusion of selected atom species into a semiconductor substrate which comprises the steps of predepositing on at least one surface of said substrate a layer of material containing the selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in the substrate, said temperature being below the temperature which would produce significant diffusion of the selected atom species into the substrate, and simultaneously bombarding at said surface selected areas of the substrate with a non-dopant particle beam for the substrate so that the particles collide with atoms in the substrate to dislodge atoms from their lattice position and create lattice vacancies which move freely in the substrate at said elevated temperature to interact with said selected atom species at said elevated temperature to enhance diffusion of the selected atom species from the surface into the substrate, said temperature and particle beam being such that no gross damage is caused in the substrate.
15. The method as in claim 14 in which said substrate is semiconductive material characterizing one conductivity type and said layer contains atom species characterizing an opposite conductivity type to thereby form a region in said substrate which defines a rectifying junction in said substrate.
16. The method as in claim 14 in which said substrate is semiconductor material characterizing one conductivity type and said layer contains atom species characterizing said one conductivity type.
17. The method as in claim 14 in which said substrate is semiconductor material characterizing one conductivity type and said layer contains atom species characterizing both said one conductivity type and an opposite conductivity type, said atom species of opposite conductivity type having a higher diffusion coefficient than said atom species of said one conductivity type whereby said atom species of said opposite conductivity type diffuses further into said substrate than the atom species of said one conductivity type to form two rectifyingjunctions in said substrate.
18. The method as in claim 14 in which said layer is applied on selected areas of said surface.
19. The method as in claim 14 wherein a mask is provided over said layer, said mask containing openings in those regions which are to be diffused into said substrate and serving to inhibit penetration of said particles in said substrate in other regions.
20. The method as in claim 14 wherein said bombardment is focused and directed to selected areas of said surface.
21. The method as in claim 15 in which there is provided the additional step of applying a second layer of said one conductivity type to said substrate, elevating the temperature of the substrate, and thereafter bombarding said substrate to form a second region which forms a rectifying junction with the first region.
22. The method as in claim 15 in which there is thereafter provided a layer of said opposite conductivity type, the temperature is elevated and the surface is bombarded to form an ohmic connection to said region.
23. The method as in claim 14 in which the energy of said beam is controlled to provide diffusions at different depths in said substrate.
24. The method as in claim 14 wherein a protective coating is applied over said layer and the energy of the bombarding beam is selected to penetrate said layer into said substrate whereby to inhibit the escape of either predeposited atom species or semiconductor lattice atom species from the surface during the enhanced diffusion.
25. The method as in claim 14 wherein the predeposited layer of material contains atomic species that control carrier lifetime in said semiconductor.
e method as in claim 14 wherein the predeposited layer of material contains atomic species that act to compensate the doping effect provided by atomic species previously introduced into the semiconductor.
27. The method of enhancing diffusion of selected atom species in a semiconductor substrate which comprises the steps of providing said selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in said substrate and bombarding at least one surface of said substrate while the temperature is elevated with a non-dopant beam of particles selected such that the particles collide with the atoms in the substrate to dislodge atoms from the lattice positions, said temperature selected whereby no gross damage is caused in the substrate by said particle beam, said particle beam serving to create lattice vacancies which move freely in the substrate at said elevated temperature to interact with the atom species to enhance the diffusion of said selected atom species in the substrate.
28. The method as in claim 27 wherein said selected atom species is deposited on said surface.
29. The method as in claim 27 wherein said particle beam comprises a proton beam having energies above 1 keV.

Claims (28)

  1. 2. The method as in claim 1 wherein said temperature is below the temperature which would produce significant diffusion of atomic species in the solid substrate.
  2. 3. The method as in claim 2 in which said selected atom species at a surface of the substrate is provided by the additional step of predepositing on said surface a layer of material containing the selected atom species which is to be diffused into the substrate.
  3. 4. The method as in claim 2 wherein said substrate is silicon and said predetermined temperature is in the range of 450* -700*C.
  4. 5. The method as in claim 2 wherein said substrate is germanium and the elevated temperature is in the range of 360* - 500*C.
  5. 6. The method as in claim 3 wherein said predeposited layer is deposited only over selected areas of the surface.
  6. 7. The method as in claim 2 including additionally providing a mask having one or more openings on said surface whereby to intercept particles and prevent the formation of lattice vacancies in the substrate beneath the mask and permit particles to pass through said openings to bombard the substrate and form lattice vacancies in the region of said openings by dislodging atoms from their lattice positions.
  7. 8. The method as in claim 2 wherein selected areas are bombarded by focusing and directing the particle beam.
  8. 9. The method as in claim 2 wherein said particle beam comprises a proton beam having energies above 1 keV.
  9. 10. The method as in claim 1 wherein the damage previously existing in the semiconductor is annealed on account of the enhanced diffusion.
  10. 11. The method as in claim 10 wherein the damage is produced by introducing the atomic species using the ion implantation technique.
  11. 12. The method as in claim 10 wherein the damage is produced during the formation of an oxide layer or other protective coating on said semiconductor surface.
  12. 13. The method as in claim 10 wherein a protective layer is applied over said semiconductor to inhibit the escape of atomic species from the surface during the enhanced diffusion.
  13. 14. The method of enhancing diffusion of selected atom species into a semiconductor substrate which comprises the steps of predepositing on at least one surface of said substrate a layer of material containing the selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in the substrate, said temperature being below the temperature which would produce significant diffusion of the selected atom species into the substrate, and simultaneously bombarding at said surface selected areas of the substrate with a non-dopant particle beam for the substrate so that the particles collide with atoms in the substrate to dislodge atoms from their lattice position and create lattice vacancies which move freely in the substrate at said elevated temperature to interact with said selected atom species at said elevated temperature to enhance diffusion of the selected atom species from the surface into the substrate, said temperature and particle beam being such that no gross damage is caused in the substrate.
  14. 15. The method as in claim 14 in which said substrate is semiconductive material characterizing one conductivity type and said layer contains atom species characterizing an opposite conductivity type to thereby form a region in said substrate which defines a rectifying junction in said substrate.
  15. 16. The method as in claim 14 in which said substrate is semiconductor material characterizing one conductivity type and said layer contains atom species characterizing said one conductivity type.
  16. 17. The method as in claim 14 in which said substrate is semiconductor material characterizing one conductivity type and said layer contains atom species characterizing both said one conductivity type and an opposite conductivity type, saiD atom species of opposite conductivity type having a higher diffusion coefficient than said atom species of said one conductivity type whereby said atom species of said opposite conductivity type diffuses further into said substrate than the atom species of said one conductivity type to form two rectifying junctions in said substrate.
  17. 18. The method as in claim 14 in which said layer is applied on selected areas of said surface.
  18. 19. The method as in claim 14 wherein a mask is provided over said layer, said mask containing openings in those regions which are to be diffused into said substrate and serving to inhibit penetration of said particles in said substrate in other regions.
  19. 20. The method as in claim 14 wherein said bombardment is focused and directed to selected areas of said surface.
  20. 21. The method as in claim 15 in which there is provided the additional step of applying a second layer of said one conductivity type to said substrate, elevating the temperature of the substrate, and thereafter bombarding said substrate to form a second region which forms a rectifying junction with the first region.
  21. 22. The method as in claim 15 in which there is thereafter provided a layer of said opposite conductivity type, the temperature is elevated and the surface is bombarded to form an ohmic connection to said region.
  22. 23. The method as in claim 14 in which the energy of said beam is controlled to provide diffusions at different depths in said substrate.
  23. 24. The method as in claim 14 wherein a protective coating is applied over said layer and the energy of the bombarding beam is selected to penetrate said layer into said substrate whereby to inhibit the escape of either predeposited atom species or semiconductor lattice atom species from the surface during the enhanced diffusion.
  24. 25. The method as in claim 14 wherein the predeposited layer of material contains atomic species that control carrier lifetime in said semiconductor.
  25. 26. The method as in claim 14 wherein the predeposited layer of material contains atomic species that act to compensate the doping effect provided by atomic species previously introduced into the semiconductor.
  26. 27. The method of enhancing diffusion of selected atom species in a semiconductor substrate which comprises the steps of providing said selected atom species, elevating the temperature of the substrate to a temperature which permits interstitial lattice atoms and lattice vacancies to move freely in said substrate and bombarding at least one surface of said substrate while the temperature is elevated with a non-dopant beam of particles selected such that the particles collide with the atoms in the substrate to dislodge atoms from the lattice positions, said temperature selected whereby no gross damage is caused in the substrate by said particle beam, said particle beam serving to create lattice vacancies which move freely in the substrate at said elevated temperature to interact with the atom species to enhance the diffusion of said selected atom species in the substrate.
  27. 28. The method as in claim 27 wherein said selected atom species is deposited on said surface.
  28. 29. The method as in claim 27 wherein said particle beam comprises a proton beam having energies above 1 keV.
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US3841917A (en) * 1971-09-06 1974-10-15 Philips Nv Methods of manufacturing semiconductor devices
US3865633A (en) * 1972-01-31 1975-02-11 Philips Corp Methods of manufacturing semiconductor bodies
US3880675A (en) * 1971-09-18 1975-04-29 Agency Ind Science Techn Method for fabrication of lateral transistor
US3895430A (en) * 1972-03-17 1975-07-22 Gen Electric Method for reducing blooming in semiconductor array targets
US3902930A (en) * 1972-03-13 1975-09-02 Nippon Musical Instruments Mfg Method of manufacturing iron-silicon-aluminum alloy particularly suitable for magnetic head core
US3936321A (en) * 1973-01-31 1976-02-03 Nippon Electric Company Limited Method of making a compound semiconductor layer of high resistivity
US3982967A (en) * 1975-03-26 1976-09-28 Ibm Corporation Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths
US4088799A (en) * 1971-02-02 1978-05-09 Hughes Aircraft Company Method of producing an electrical resistance device
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
US4278475A (en) * 1979-01-04 1981-07-14 Westinghouse Electric Corp. Forming of contoured irradiated regions in materials such as semiconductor bodies by nuclear radiation
US4364969A (en) * 1979-12-13 1982-12-21 United Kingdom Atomic Energy Authority Method of coating titanium and its alloys
US4434025A (en) 1981-06-04 1984-02-28 Robillard Jean J Controlling crystallinity and thickness of monocrystalline layer by use of an elliptically polarized beam of light
US4465529A (en) * 1981-06-05 1984-08-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device
US4521441A (en) * 1983-12-19 1985-06-04 Motorola, Inc. Plasma enhanced diffusion process
US4565710A (en) * 1984-06-06 1986-01-21 The United States Of America As Represented By The Secretary Of The Navy Process for producing carbide coatings
US4668527A (en) * 1985-03-06 1987-05-26 Osaka University Method for amorphizing a material by means of injection of exotic atoms into a solid with electron beams
US4670292A (en) * 1985-02-27 1987-06-02 Osaka University Method for injecting exotic atoms into a solid with electron beams
US4720469A (en) * 1985-06-10 1988-01-19 Bbc Brown, Boveri & Company, Limited Method for diffusing aluminum
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
EP0938130A2 (en) * 1998-02-12 1999-08-25 Lucent Technologies Inc. A process for fabricating a device with shallow junctions
US6057216A (en) * 1997-12-09 2000-05-02 International Business Machines Corporation Low temperature diffusion process for dopant concentration enhancement
US6670255B2 (en) * 2001-09-27 2003-12-30 International Business Machines Corporation Method of fabricating lateral diodes and bipolar transistors
US20060073684A1 (en) * 2004-09-22 2006-04-06 Hans-Joachim Schulze Method for fabricating a doped zone in a semiconductor body
US20060166394A1 (en) * 2003-07-07 2006-07-27 Kukulka Jerry R Solar cell structure with solar cells having reverse-bias protection using an implanted current shunt
US20110042791A1 (en) * 2006-01-20 2011-02-24 Infineon Technologies Austria Ag Method for treating an oxygen-containing semiconductor wafer, and semiconductor component
WO2017112353A1 (en) * 2015-12-22 2017-06-29 Varian Semiconductor Equipment Associates, Inc. Damage free enhancement of dopant diffusion into a substrate
US20190214521A1 (en) * 2018-01-10 2019-07-11 International Business Machines Corporation Photodetector having a tunable junction region doping profile configured to improve contact resistance performance

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US3481776A (en) * 1966-07-18 1969-12-02 Sprague Electric Co Ion implantation to form conductive contact
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Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4088799A (en) * 1971-02-02 1978-05-09 Hughes Aircraft Company Method of producing an electrical resistance device
US3841917A (en) * 1971-09-06 1974-10-15 Philips Nv Methods of manufacturing semiconductor devices
US3880675A (en) * 1971-09-18 1975-04-29 Agency Ind Science Techn Method for fabrication of lateral transistor
US3865633A (en) * 1972-01-31 1975-02-11 Philips Corp Methods of manufacturing semiconductor bodies
US3902930A (en) * 1972-03-13 1975-09-02 Nippon Musical Instruments Mfg Method of manufacturing iron-silicon-aluminum alloy particularly suitable for magnetic head core
US3895430A (en) * 1972-03-17 1975-07-22 Gen Electric Method for reducing blooming in semiconductor array targets
US3936321A (en) * 1973-01-31 1976-02-03 Nippon Electric Company Limited Method of making a compound semiconductor layer of high resistivity
US3982967A (en) * 1975-03-26 1976-09-28 Ibm Corporation Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths
DE2611559A1 (en) * 1975-03-26 1976-10-07 Ibm PROCESS FOR MANUFACTURING SEMICONDUCTOR STRUCTURES
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
US4278475A (en) * 1979-01-04 1981-07-14 Westinghouse Electric Corp. Forming of contoured irradiated regions in materials such as semiconductor bodies by nuclear radiation
US4364969A (en) * 1979-12-13 1982-12-21 United Kingdom Atomic Energy Authority Method of coating titanium and its alloys
US4465524A (en) * 1979-12-13 1984-08-14 United Kingdom Atomic Energy Authority Titanium and its alloys
US4434025A (en) 1981-06-04 1984-02-28 Robillard Jean J Controlling crystallinity and thickness of monocrystalline layer by use of an elliptically polarized beam of light
US4465529A (en) * 1981-06-05 1984-08-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device
US4521441A (en) * 1983-12-19 1985-06-04 Motorola, Inc. Plasma enhanced diffusion process
US4565710A (en) * 1984-06-06 1986-01-21 The United States Of America As Represented By The Secretary Of The Navy Process for producing carbide coatings
US4670292A (en) * 1985-02-27 1987-06-02 Osaka University Method for injecting exotic atoms into a solid with electron beams
US4668527A (en) * 1985-03-06 1987-05-26 Osaka University Method for amorphizing a material by means of injection of exotic atoms into a solid with electron beams
US4720469A (en) * 1985-06-10 1988-01-19 Bbc Brown, Boveri & Company, Limited Method for diffusing aluminum
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US6057216A (en) * 1997-12-09 2000-05-02 International Business Machines Corporation Low temperature diffusion process for dopant concentration enhancement
EP0938130A2 (en) * 1998-02-12 1999-08-25 Lucent Technologies Inc. A process for fabricating a device with shallow junctions
EP0938130A3 (en) * 1998-02-12 1999-10-20 Lucent Technologies Inc. A process for fabricating a device with shallow junctions
US6136673A (en) * 1998-02-12 2000-10-24 Lucent Technologies Inc. Process utilizing selective TED effect when forming devices with shallow junctions
US6670255B2 (en) * 2001-09-27 2003-12-30 International Business Machines Corporation Method of fabricating lateral diodes and bipolar transistors
US20060166394A1 (en) * 2003-07-07 2006-07-27 Kukulka Jerry R Solar cell structure with solar cells having reverse-bias protection using an implanted current shunt
US20060073684A1 (en) * 2004-09-22 2006-04-06 Hans-Joachim Schulze Method for fabricating a doped zone in a semiconductor body
US10651037B2 (en) * 2004-09-22 2020-05-12 Infineon Technologies Ag Method for fabricating a doped zone in a semiconductor body
US20110042791A1 (en) * 2006-01-20 2011-02-24 Infineon Technologies Austria Ag Method for treating an oxygen-containing semiconductor wafer, and semiconductor component
WO2017112353A1 (en) * 2015-12-22 2017-06-29 Varian Semiconductor Equipment Associates, Inc. Damage free enhancement of dopant diffusion into a substrate
US9953835B2 (en) 2015-12-22 2018-04-24 Varian Semiconductor Equipment Associates, Inc. Damage free enhancement of dopant diffusion into a substrate
US20190214521A1 (en) * 2018-01-10 2019-07-11 International Business Machines Corporation Photodetector having a tunable junction region doping profile configured to improve contact resistance performance
US10546971B2 (en) * 2018-01-10 2020-01-28 International Business Machines Corporation Photodetector having a tunable junction region doping profile configured to improve contact resistance performance

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DE2050497A1 (en) 1971-04-22

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