US3657718A - Code compression system - Google Patents

Abstract

A code compression system comprises a generator for producing a maximal length sequence code at a first predetermined frequency. The code is delayed with respect to the generated code, and both codes are then combined to produce an output code having an identical maximal length sequence code as the generated code, at a higher multiple frequency than the generated code. The circuit for combining the generated code and the delayed code may comprise an exclusive OR gate.

Description

United States Patent DELQV 15] 3,657,718 OFarrell [4s 1 Apr. 18, 1972 [541 CODE COMPRESSION SYSTEM 3,069,657 12/ 1962 Green et al. ..340/ 146.1 1 3,518,547 6/1970 Filipowsky ..l79/ 150 R X [72] Invent 0 Sepulveda' 3,155,818 11/1964 Goetz ..340/l46.l x {73] Assignee: International Telephone and Telegraph 'p t New York, Primary Examiner-Thomas A. Robinson Attorney-C. Cornell Remsen, Jr., Walter J. Baum, Paul W. [22] Flled' June 1970 l-lemmin er and Thomas E. Kristofi'erson [21] A IN 50628 g [57] ABSTRACT v U.S. DD, A code compression ystem comprises a generator for produc. [51] Int. Cl ..l-l03r 13/32, H03r 13/00 ing a i l length sequence code at a first predetermined [58] Field of Search ..340/347 DD, 348, 35 I, 355: frequency The code is delayed with respect to the generated 340/ 6 328/32 code, and both codes are then combined to produce an output 307/271 325/38 178/66 23 235/154 code having an identical maximal length sequence code as the generated code, at a higher multiple frequency than the [56] References cued generated code. The circuit for combining the generated code UNITED STATES PATENTS and the delayed code may comprise an exclusive OR gate. 3,105,955 10/1963 Mauchly ..340/ 146.1 3 Claims, 7 Drawing Figures 38 4 52, I2; 5e 58 eq 607p DELRY Patented April 18, 1972 2 Sheets-Sheet 2 BY KM FITTORA/(EY BACKGROUND OF THE INVENTION of sampled Prior art high frequency codes have been produced by directly generating the high frequency code from a clock source, which has required the use of very fast adders and shift registers. Alternatively, high frequency sampling has been utilized to produce high frequency codes which utilized state eof the art coders. A typical high frequency sampler is described in US. Pat. application Ser. No. 885,087 filed Dec. 15, I969 and assigned to the assignee of the present application. The aforementioned patent application produces a maximal length sequence code at a multiple frequency of an input maximal length sequence code. The input maximal length sequence codes are provided at a predetennined frequency and are delayed by a fixed amount with respect to each other. The codes are sampled at a rate higher than the frequencies of the codes. The sample codes are then combined to produce the output code at a multiple of the input frequency.

In order to overcome the attendant disadvantages of prior art code frequency compressors, the present invention eliminates the need for direct generation of the code using high frequency'clock sources. Moreover, high frequency sampling of the. input codes is not required. By delaying the input code utilizing conventional delay techniques and adding the delay code to the input code the input code can be compressed so that a high frequency code is generated. Moreover, state of the art components can be utilized in the system.

The advantages of this invention, both as to its construction and mode of operation will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connecting with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENT In describing the apparatus of the present invention, a convention is employed wherein an exclusive OR gate is shown as Inputs are applied to the exclusive OR gate at the left and an output appears on the right. In'the present case, an exclusive OR gate produces an output signal C in accordance with the following formula: C A F B A where A and B are inputs to the exclusive OR gate.

Referring now to FIG. I of the drawings, thereis sown a schematic block diagram of a preferred embodiment of the apparatus of the present invention. The code compression system of FIG. 1 contains a shift register 12 which has n stages with proper interstage feedback connections and is driven by a clock 14. The output of the shift register 12 is a linear maximal sequence of L 2" 1 bits length.

. z As described in Us. Pat. application Set. No. 885,087 filed Dec. 15, 1969, a linear maximal sequency is a binary sequence generated by a linear shift register generator and which has the longest possible word length period for this generation method. This longest possible period is given by the fonnula where L equals the length of the maximal length sequence;

and n equals the number of stages in the shift register, and f equals the clock frequency.

The present invention describes a method and apparatus by which code words of a repetition period L/Kf= 2'"- 1/10 can be generated without higher frequency clocks or sampling devices. It has been found that each identical K number of codes at clock frequency f with proper relative delays are sequentially added in binary fashion by use of an exclusive OR gate and a compressed code of clock frequency Kf is obtained.

Thus, referring once again to FIG. 1, an exclusive OR gate 16 has one input tenninal connected to the output of the shift register 12. Further, the output of the shift register 12 is also connected to a delay network 18 having a delay L/2 f. The output of the delay network is coupled to another input terminal of the exclusive OR gate 16 whose output is coupled to the output tenninal 22.

Referring now to FIG. 2, there are shown in FIG. 2a the clock pulses at a clock frequency f which are coupled to the input of the shift register 12. The output of the shift register is shown in FIG. 2b and comprises a maximal length sequency which is coupled to one of the inputs of the exclusive OR gate 16. Further, this maximal length sequence of FIG. 2a is coupled to the delay network 18 whose output, shown in FIG. 20 comprises a one-half word delayed code. FIG. 2d depicts the output of the exclusive OR gate 16 which is produced at terminal 22. As can be readily seen, the output at terminal 22 is a maximal length code which is twice the frequency of the code of FIG. 2b.

' As shown with respect to FIG. 1 and 2, for K 2, the relative delay is'one-half word and the binary sequence consists of a single addition. For K 3, the relative delay is one-third word and two additions-are required, namely the zero delayed code with the one-third word delayed code and then, the resultant of this addition with the two-thirds word delayed code. 1

Referring now to FIG. 3, there is illustrated a block diagram of the code compression system for the condition where K 3. A clock ,l4'is coupled to a shift register 12 both of which may be similar to that of FIG. I. The output of the shift register is coupled to an input terminal of a first exclusive OR gate 24 and to a delay network 26 having a delay of one-third word. The output of the delay network 26 is coupled to the other input terminal of the exclusive OR gate 24. Further, the output of the shift register is coupled to a second delay network 28 which delays the code two-thirds of a word. The output of the gate 24, as well as the output of the delay network 28 are each coupled to input terminals of an exclusive OR gate 29, respectively. The output of the gate 29 is coupled to an output terminal 30.

FIG. 4 (a. through f) depicts the waveform for K 3. FIG. 4 (a) depicts the clock pulses having a frequency coupled from the clock 14 to register 12 which code depicted in FIG. 4 (b). FIG. 4 (c) depicts the maximal length code of FIG. 4 (b) delayed one-third word by the delay network 26. Use of the exclusive OR gate 24 to perform binary addition to the codes of FIGS. 4 (b) and 4 (0) results in the binary sum shown in FIG. 4 (d). Further, the code of FIG. 4 (b) is delayed two-thirds of a word by delay 28 as shown in FIG. 4(a) and the binary sum of FIG. 4 (d) 4 (e) are then binary added together to produce a binary sum shown in FIG. 4

Q). As can be readily seen, the code of FIG. 4 (f) has a repetition rate of three times the frequency of the code of FIG. 4 (b).

For K 4, it is possible to obtain the detailed code by two K 5 2 operations which require two delays and two additions.

produces a maximal length' Further, thestraightforward application of one-fourth word 1 delays requires three delays and three additions. In general,

a the number of delays and additions required are always equal and can be computed by factoring K into its primitive factors of I a =2a3e5c7d.....

where a, b, c, d are the number of times the respective factor is repeated which then establishes thenumber of required delays or additions Q as Q=a+2b+4c+6d+.....

It must be noted that Kvmay assume any value, except those thatare factors of L.

The only high frequency device required for the present in-* vention are the binary adders of the final multiplication series which must respond with sufficient speed to allow variation of pulses UK of the width of the original wave form pulses. The relative. delay required between base frequency codes is unique and not other delay or combination of delays will pro vide the desired results.

Referring nowto FIGS. 5. through 7, there are shown three alternate ways of generating a code having a frequency of 60 cation required. For K 60 the number of steps equals four (2 X2 X 3 X 5).

The first step is a multiplication by 2 and therefore requires a relative delay of one-half the periodof the f frequency code L'/ 2 f to produce the compressed code of frequency 2 f.

The second step is a multiplication by 2 of the 2 f frequency codeand therefore requires a relative delay of one-half the code and, therefore, requires two relative delays of one-third the period of the 4 f frequency code or one-third (L/4f) and two-thirds the period of two-thirds L/4f).

The fourth step is a multiplication by 5 of the 12 f frequency a code and therefore requires four relative delays of one-fifth or 1/5 (L/12f), two-fifths or 2/5 (L/ 12)), three-fifths or 3/5 (L/ 12f and four-fifths or 4/5 (L/ 12]), the period of the 12 f frequency code. The combined addition then yields acompressed code of clock frequency 60 f with only 8 delay elements. The straightforward approach wouldrequire 59 delays each spaced L/60 f or one-sixtieth of a code word interval apart. a

More particularly, in FIG. 5, the shift register 12 couples a maximal length code such as that depicted in FIGS. 1 through 4 to one of the input terminals of an exclusive OR circuit 34 as well as to a delay network 36 having a delay L/2f. The output of the delay network 36 is also coupled to an input terminal of the exclusive OR gate 34, and, as was previously explained with respect to the circuit of FIGS. 1 and 2, an output is present at the output of the exclusive OR gate 34 whose frequency is twice that of the input code to the circuit 34. This, output signal is then coupled to a second exclusive OR gate 38 as well as through a delay network 42 having a delay one-half that of the delay network 36. The output code at the output of the exclusive OR gate 38 will be, of course, twice the frequency as the code coupled to the input of gate 34.

Thecode at the output of gate 38 may then be, as in the technique shown in FIGS. 3 and 4, coupled to a first input terminal of an exclusive OR gate 44 as well as through a onethird word delay 46 to another input terminal of the exclusive OR gate 44. Further, the input signal is coupled through a twothirds word delay 48 to an input terminal of an exclusive OR gate 52. The outputsignal at the OR gate 44 is also coupled to the other input terminal of the gate 52. The resultant output at the exclusive OR gate 52 will be a code having a frequency 1 times the frequency of theinitial code generated bythe shift register or three times the frequency of the code at the output of the exclusive OR gate 38.

Moreover, this compressed code is coupled to the input and output terminals of exclusive OR gates 54, 56, 58 and 60 as well as'through code word delays produced by networks 62, 64, 66 and 68, respectively, and hence into the other input terminal of the gates 54, 56, 58 and 60, respectively. Finally, the output at an output terminal of the gate 60 will be five times the input frequency at the gate or 60 times the input frequency of the code generated by the shift register.

An alternate way of generating the required delays, keeping in mind that hardware weight and volume increase as the delay increases, is to arrange the delays in series. For instance, four delays of one-fifth word will provide a total delay of fourfifths. FIG. 6 shows this alternate arrangement wherein four delays 72, 74, 76 and 78 of U5 (U12 1) connected in series replace the delays 62, 64, 66 and 68 ofFlG, 5. i

For the code described in' FIG. 6 for a starting clock frequencyf= 1.67 MHz and n 3 or L 2" l 7, the individual delay types required for the 60 f code MHz) are as follows:

Delay nesis'asaBinariesirageaeaasr; an; sweats using the lowest valued K factors first and then increasing the multiplication process (2 X 2 X 3 X 5). The largest delay required is L/2 f or 2.1 11. sec. By reversing the multiplication factors the largest delay required can be significantly reduced. FIG. 8 shows the delays required. It is noted that the largest delay is US for 0.84 a see which is two and one-half times lower than that required for FIG. 6.'Therefore, to keep the amount of delay at a minimum the highest order K factors should be used first. Also, the order of multiplication (highest factor first) requires a minimum number of fast gates. For the code depicted in FIG. 7 and the same starting clock frequency, f 1.67 MHz and code length L 7, are that of FIG. 7 the individual delay types required for the 60 f code (100 MHz) are as follows:

Delay In FIG. 7, four gates, 82, 84, 86 and 88 are connected in series combination with delay networks 92, 94, 96 and 98, respectively, the four delays having a delay of U5 f. Thus, the resultant output at the exclusive OR gate 88 is a compressed code of frequency 5f.

The output signal at the gate 88 is then again utilized as an input to a pair of series connected delays 102 and 104, each of which provides a one-third word delay for the output signal from the gate 88. The output signal from the gate 88 together with the output from the delay 102 are coupled to an exclusive OR gate 106. The output of gate 106, together with the output signal from the delay 104 are coupled to an exclusive OR gate 108. The output code at the gate 108 has a frequency three times the output code of the gate 88, or times the original code. Then the output signal from gate 108 is coupled to one input terminal of an exclusive OR gate 112 and through a delay 114 having one-half code word delay. The output of the delay 114 is coupled to the other input terminal of the gate 112 with the resultant output frequency being twice the input frequency to the gate 112. Finally, in order to produce a code word having an output frequency 60 times the input frequency, the delay of gate 112 is coupled to still another OR gate 116 and through a delay 118 having a delay one-half code word for the signal from the output of gate 112. This, of course, results in an output code word at the output of gate 116 having a frequency equal to 60 times the input frequency to the system.

In summary, the novel method of code compression described herein allows the basic coder circuitry to operate at a lower speed and only the exclusive OR gates need operate at the higher speeds. Speeds of gate circuits are inherently faster than flip flops, shift registers in that these latter elements are made up of multiple gate circuits.

It should be further understood that other alternative arrangements for producing multiple frequency codes with respect to an input frequency code are possible with the illustrations provided in the drawings being merely typical and not limiting.

What is claimed is:

1. A code compression system comprising:

means for generating a first maximal length sequence code at a predetennined frequency;

means for producing a second maximal length sequence code at said predetermined frequency having a'wavefonn identical to said first maximal length sequence code, said second maximal length sequence code being delayed a predetermined interval with respect to said first maximal length sequence code; and

means for producing a maximal length sequence code identical to said fist and second maximal length sequence codes at a frequency higher than said predetennined frequency comprising an exclusive OR gate having a first input terminal and a second input terminal, said first and second maximal length sequence codes being coupled to said first and second input terminals, respectively.

2. A code compression system in accordance with claim 1 wherein said means for producing said second maximal length sequence code comprises a delay network having a delay D, where D L/Kf where L=the length of the maximal length sequence;

f the clock frequency of the maximal length sequence;

and

K the number of codes at clock frequency f which must be added to obtain a compressed code of clock frequency K 3. A code compression system in accordance with claim 2 wherein the input to said delay network is said first maximal length sequence code.

Claims (3)

1. A code compression system comprising: means for generating a first maximal length sequence code at a predetermined frequency; means for producing a second maximal length sequence code at said predetermined frequency having a waveform identical to said first maximal length sequence code, said second maximal length sequence code being delayed a predetermined interval with respect to said first maximal length sequence code; and means for producing a maximal length sequence code identical to said fist and second maximal length sequence codes at a frequency higher than said predetermined frequency comprising an exclusive OR gate having a first input terminal and a second input terminal, said first and second maximal length sequence codes being coupled to said first and second input terminals, respectively.

2. A code compression system in accordance with claim 1 wherein said means for producing said second maximal length sequence code comprises a delay network having a delay D, where D L/Kf where L the length of the maximal length sequence; f the clock frequency of the maximal length sequence; and K the number of codes at clock frequency f which must be added to obtain a compressed code of cloCk frequency Kf.

3. A code compression system in accordance with claim 2 wherein the input to said delay network is said first maximal length sequence code.

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