US3631294A - Electronic storage tube utilizing a target comprising both silicon and silicon dioxide areas - Google Patents

Electronic storage tube utilizing a target comprising both silicon and silicon dioxide areas Download PDF

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US3631294A
US3631294A US840698A US3631294DA US3631294A US 3631294 A US3631294 A US 3631294A US 840698 A US840698 A US 840698A US 3631294D A US3631294D A US 3631294DA US 3631294 A US3631294 A US 3631294A
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insulating
conducting
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silicon
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Steven R Hofstein
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Princeton Electronic Products Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H01J29/10—Screens on or from which an image or pattern is formed, picked up, converted or stored
    • H01J29/36—Photoelectric screens; Charge-storage screens
    • H01J29/39—Charge-storage screens
    • H01J29/41—Charge-storage screens using secondary emission, e.g. for supericonoscope
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/3167—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation
    • H01L21/31675—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation of silicon

Definitions

  • ABSTRACT An electronic storage tube having a target whose conducting areas are silicon and whose insulating areas are silicon dioxide.
  • One configuration of the target is a pattern of alternating strips of conducting areas and insulating areas.
  • electronic storage tubes are comprised of a target for storing information of a writing signal, means for directing the writing signal (generally an electron beam) onto the target and means for reading the stored information at an output terminal.
  • targets of electronic storage tubes are made of a conducting mesh covered with a thin insulating film or of a continuous dielectric film with an overlay of a conductive mesh material.
  • the invention is directed toward providing a target pattern of alternating stripes of insulating areas and conducting areas wherein the conducting areas are silicon which has been doped with either n or p material and the insulating areas are silicon dioxide.
  • One such pattern is in the form of alternating stripes of conducting areas and insulating areas.
  • the silicon dioxide is genetically derived from the silicon.
  • FIG. I is a diagrammatic, elevational view of an electron storage tube utilizing the targets of the invention.
  • FIG. 2 is a plan view of a target of the invention wherein the pattern is comprised of alternating stripes of conducting areas and insulating areas;
  • FIG. 3 is a sectional view taken along the lines 3-3 of FIG. 2, viewed in the direction of the arrows;
  • FIG. 4 is a sectional view illustrating the steps of a preferred method for producing targets of the invention.
  • FIG. 5 is a plan view of another embodiment of target of the invention.
  • FIG. 6 is a sectional view taken along the lines 6-6 of FIG. 5, viewed in the direction of the arrows;
  • FIG. 7 is a view similar to that of FIG. 6 of a further embodiment of the target of the invention.
  • FIG. Bis a view similar to that of FIG. 6 ofa still further embodiment of the target of the invention.
  • Storage tube 10 is seen to comprise (FIG. 1) envelope 12, control grid 14, cathode l6, accelerating anode 18, wall anode 20, target 22 which comprises substrate 24 and mosaic layer 26, deflecting coil 28, focusing coil 30, output terminal 32 and grid mesh 34.
  • the Write signal is applied to the target by either x-y deflection of the electron beam emitted by the cathode 16 or by zaxis modulation of a raster scanned beam.
  • the Read signal is a normal raster scan electron beam which is applied to the target. During the Read cycle, output current proportional to the charge pattern on the target (the distribution of charge on the insulating areas of the target) is obtained at output terminal 32 when the normal raster scan electron beam sweeps the target 22.
  • the insulating mosaic of the target acts essentially as a coplanar grid so that the more negative the potential on the insulating areas is, the lower the current on the conducting areas. It is possible to completely cut off the current to the conducting areas by placing a sufficiently high negative potential on the insulating areas.
  • This charge pattern may be positive, negative or zero depending on the requirement of the Write mode.
  • a uniform, high, negative charge is required to be left on the insulating mosaic after the Erase mode is completed. If Equilibrium or low-velocity" Write signals are used, a zero or slightly negative charge should remain on the insulating mosaic after the Erase mode is completed.
  • Target 40 comprises conducting substrate 42 and insulating stripes 44.
  • the conducting substrate 42 is silicon.
  • the silicon may be of the P-type or N-type.
  • the insulating stripes are preferably formed of silicon dioxide.
  • Targets which are formed with the pattern of alternating insulating stripes and conducting stripes have some advantage over other target mosaic configurations such as are illustrated in FIGS. 5-8.
  • the pattern of target 50 is formed, as is illustrated in FIGS. 5 and 6, with a mosaic of insulating pads 54 on a conducting substrate 52, certain limitations in operation exist. a
  • the exposed conducting areas 52 actually comprise crossed grid of both vertical and horizontal stripes; This crossed or double grid increases the possibility of failure due to insulator crossovers or insulator gaps. Furthermore, both the horizontal and vertical resolution are determined by the structure of the target, namely, the vertical and horizontal spacing dimensions.
  • the widths of the insulating stripes 44 and the conducting stripes 43 are approximately equal.
  • the dimensions may be made equal and minimized for maximum resolution while maintaining the area ratio at lzl. This ratio is optimum for satisfactory control of the Read beam.
  • an additional advantage resides in the fact that resolution in the longitudinal direction of the stripes is no longer limited by the target structure, resulting in higher resolution capability. Since thisconstruction is a single grid, only one failure or bridging" mode is possible, namely, that across the stripes.
  • the conducting areas are formed of the doped silicon, either P or N, and the insulating areas are formed of the silicon dioxide.
  • Excellent targets of the type described are obtained when the silicon dioxide layer 'is genetically derived from the silicon.
  • a genetically derived layer is one in which the insulating layer is derived from the conducting base or substrate material. This can be accomplished, for example, by immersing the silicon in a chemical solution such as N-Methyl-Acetamide or similar materials while applying a voltage to the silicon (anodically grown). Other methods of genetically deriving the insulating layer may also be used. I
  • FIG. 4 A preferred process for forming a genetically derived target of the invention is illustrated in FIG. 4.
  • a silicon wafer of doped silicon is specially cleaned with a suitable solvent to eliminate all surface imperfections and contaminants. It is then oxidized at temperatures of the order of l,ll ,250 C. so that a high quality silicon dioxide layer 62 is formed on silicon substrate 60. Layer 62 is about l micron thick.
  • the silicon dioxide surface is coated with a photosensitive lacquer 64.
  • the unit is exposed to light through an optical mask of the desired pattern and then developed.
  • the exposed portions of silicon dioxide layer 62 are then removed by dilute hydrofluoric .acid and the photoresist 64 is stripped from the surfaces of the stripes of silicon dioxide.
  • the width of each of the stripes 43 is of the order of 3-7 microns.
  • FIG. 7 there is illustrated a target wherein the substrate 70 is conductive and the insulator film 72 is provided with holes 73 so that the desired pattern of substrate 70 is exposed to the electron beam.
  • substrate 74 is an insulator and conductive film 76 is provided with holes 77 so that the desired pattern of substrate 74 is exposed to the electron beam.
  • FIGS. 7 and 8 may be used with the particular patterns illustrated in FIGS. 2 and 5 or with any other desired pattern.
  • the desired target of one of the types described is installed in electron tube 10 which is produced in any manner which is well known in the art.
  • operation of electronic storage tubes of the invention may then proceed as follows.
  • target 22 is placed at about +250 volts and grid 14 is kept at approximately -60 volts.
  • the information to be stored is placed on grid 14 with a peak-to-peak signal of approximately 10 volts. Under these conditions the information can be written in about one-thirtieth of a second (I TV frame).
  • the target is returned to about +8 volts. It is scanned in conventional raster format with the voltage on grid 14 adjusted to yield an output signal at terminal 32 of approximately 200 n. Continuous readout is possible under the above conditions for more than [0 minutes. Longer storage time is possible if the readout signals are smaller. Because of the dielectric relaxation time of silicon dioxide, with the beam off, the storage time will be a week or more.
  • the storage signal on the target can be erased by applying about volts to target 22, setting grid M at approximately zero volts to yield maximum beam current and scanning the area to be erased. Now, the erased area is ready to accept new information without the necessity for a prime cycle.
  • the target voltage is about +250 volts. At this voltage, the electrons from the beam which impinge on the silicon dioxide layer 26 cause secondary emission of the order of 5:1 and the net electron current to the silicon dioxide is negative. At increased target voltage. the secondary emission ratio decreases because secondary electrons are formed deep in the silicon dioxide and have difficulty escaping.
  • the Write cycle is performed in the flat portion of the curve which plots electronic current to the silicon dioxide against target voltage, namely, about +250 volts. There is another flat portion of the curve at about L000 to 2,000 volts.
  • the Write cycle is carried on at the flat region of the curve so that the surface of the silicon dioxide is charged positively.
  • This positive charge is proportional to the number of electrons impinging on that area of the target. This yields a positive, linear relationship between the electron current from the gun and the positive charge on the target.
  • the silicon (conducting portion) plate or substrate 24 is returned to a potential which sets the insulating portion 26 negative with respect to cathode 16.
  • the regions that are very negative prevent any current flow to the silicon (corresponding to a "black” picture).
  • the regions which are only slightly negative will allow a significant current flow to the silicon (corresponding to a "white picture). Since the signal from the target may be inverted electrically, if desired, the very negative regions (no current flow) may correspond to a white" signal and the slightly negative regions (significant current flow) may correspond to a black" signal.
  • the Erase cycle simply charges the surface of the insulating areas to a uniformly negative value so that no electronic current can flow to the conducting substrate because of the repulsion effect of the coplanar insulating grid.
  • An electronic storage tube including a target which is comprised of a pattern of conducting and insulating areas, the tube comprising:
  • the insulating areas are formed of silicon dioxide.
  • the pattern comprises a plurality of alternating insulating and conducting stripes.
  • the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
  • the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  • the invention of claim 1 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
  • the pattern comprises a plurality of alternating insulating and conducting stripes.
  • the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
  • the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  • the invention of claim 8 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
  • the invention of claim 12 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  • the conducting layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  • the pattern comprises a plurality of alternating and insulating and conducting stripes.
  • the pattern comprises a plurality of alternating insulating and conducting stripes.
  • An electronic storage tube comprising:
  • a target having a pattern of alternating conducting areas and insulating areas
  • the conducting areas being electrically connected to the output terminal
  • the insulating areas are formed of silicon dioxide.

Abstract

An electronic storage tube having a target whose conducting areas are silicon and whose insulating areas are silicon dioxide. One configuration of the target is a pattern of alternating strips of conducting areas and insulating areas.

Description

United States Patent [56] References Cited UNITED STATES PATENTS 2,859,376 12/1958 Kirkpatrick..................
Steven R. I-Ioi'steln Princeton, NJ. Appl. No. 840,698
315/12 X 2,912,615 12/1959 Lubszynski... 313/89 X 3,277,333 10/1966 Williams et al.. 315/12 3,293,474 12/1966 Gibson 315/12 X 3,339,099 8/1967 Anderson. 315/12 X 3,401,293 9/1968 Morris.......................... 315/12 X 3,428,850 2/1969 Crowell et 315/12 3,480,482 11/1969 Picker.......................... 315/12 X Primary Examiner-Rodney D. Bennett, Jr. Assistant Examiner-J. M. Potenza Attorney-Samuelson & Jacob [72] Inventor [22] Filed July 10, 1969 [45] Patented Dec. 28, 1971 [73] Assignee Princeton Electronic Products, Inc.
Princeton, NJ.
[54] ELECTRONIC STORAGE TUBE UTILIZING A TARGET COMPRISING BOTH SILICON AND SILICON DIOXIDE AREAS 23 Claims, 8 Drawing Figs.
20 7 ll 59 12 31. l 0 H ABSTRACT: An electronic storage tube having a target whose conducting areas are silicon and whose insulating areas are silicon dioxide. One configuration of the target is a pattern of alternating strips of conducting areas and insulating areas.
PATENTEDBEBZBIQYI 3631.294
SHEET 1 OF 2 INVENTOR. STEVEN R. l-IOFS IYEIN 3 id w" W ELECTRONIC STORAGE TUBE UTILIZING A TARGET COMPRISING BOTH SILICON AND SILICON DIOXIDE AREAS This invention relates to electronic storage tubes. In particular, it relates to certain target configurations and target composition.
Broadly, electronic storage tubes are comprised of a target for storing information of a writing signal, means for directing the writing signal (generally an electron beam) onto the target and means for reading the stored information at an output terminal. Usually, targets of electronic storage tubes are made of a conducting mesh covered with a thin insulating film or of a continuous dielectric film with an overlay of a conductive mesh material.
The invention is directed toward providing a target pattern of alternating stripes of insulating areas and conducting areas wherein the conducting areas are silicon which has been doped with either n or p material and the insulating areas are silicon dioxide. One such pattern is in the form of alternating stripes of conducting areas and insulating areas. In one form of the invention the silicon dioxide is genetically derived from the silicon.
It is an important object of the invention to provide an electronic storage tube wherein the target is formed of alternating conducting areas and insulating areas and wherein the conducting areas are formed of silicon and the insulating areas are formed of silicon dioxide.
It is another important object of the invention to provide a target for an electronic storage tube as described above wherein the target is formed of alternating stripes of conducting areas and insulating areas and the scanning directions of the writing beam and reading beam across the target are transverse to the longitudinal dimension of the stripes.
It is a further object of the invention to provide a target of silicon and silicon dioxide wherein the silicon dioxide is genetically derived from the silicon.
These and other objects, advantages, features and uses will be apparent during the course of the following description when taken in conjunction with the accompanying drawings wherein:
FIG. I is a diagrammatic, elevational view of an electron storage tube utilizing the targets of the invention;
FIG. 2 is a plan view of a target of the invention wherein the pattern is comprised of alternating stripes of conducting areas and insulating areas;
FIG. 3 is a sectional view taken along the lines 3-3 of FIG. 2, viewed in the direction of the arrows;
FIG. 4 is a sectional view illustrating the steps of a preferred method for producing targets of the invention;
FIG. 5 is a plan view of another embodiment of target of the invention;
FIG. 6 is a sectional view taken along the lines 6-6 of FIG. 5, viewed in the direction of the arrows;
FIG. 7 is a view similar to that of FIG. 6 of a further embodiment of the target of the invention; and
FIG. Bis a view similar to that of FIG. 6 ofa still further embodiment of the target of the invention.
In the drawings, wherein, for the purpose of illustration, there are shown various embodiments of the invention, the numeral l0 designates an electronic storage tube of the invention, generally. Storage tube 10 is seen to comprise (FIG. 1) envelope 12, control grid 14, cathode l6, accelerating anode 18, wall anode 20, target 22 which comprises substrate 24 and mosaic layer 26, deflecting coil 28, focusing coil 30, output terminal 32 and grid mesh 34.
The Write signal is applied to the target by either x-y deflection of the electron beam emitted by the cathode 16 or by zaxis modulation of a raster scanned beam. The Read signal is a normal raster scan electron beam which is applied to the target. During the Read cycle, output current proportional to the charge pattern on the target (the distribution of charge on the insulating areas of the target) is obtained at output terminal 32 when the normal raster scan electron beam sweeps the target 22.
During the Read cycle, the insulating mosaic of the target acts essentially as a coplanar grid so that the more negative the potential on the insulating areas is, the lower the current on the conducting areas. It is possible to completely cut off the current to the conducting areas by placing a sufficiently high negative potential on the insulating areas.
To Erase the stored signal, it is necessary to reestablish a uniform charge pattern on the insulating mosaic. This charge pattern may be positive, negative or zero depending on the requirement of the Write mode. For the high-velocity Write mode described above, a uniform, high, negative charge is required to be left on the insulating mosaic after the Erase mode is completed. If Equilibrium or low-velocity" Write signals are used, a zero or slightly negative charge should remain on the insulating mosaic after the Erase mode is completed.
In FIGS. 2 and 3 there is illustrated a preferred embodiment of target which may be employed in practicing the invention. Target 40 comprises conducting substrate 42 and insulating stripes 44. The conducting substrate 42 is silicon. The silicon may be of the P-type or N-type. The insulating stripes are preferably formed of silicon dioxide.
Targets, which are formed with the pattern of alternating insulating stripes and conducting stripes have some advantage over other target mosaic configurations such as are illustrated in FIGS. 5-8. Where the pattern of target 50 is formed, as is illustrated in FIGS. 5 and 6, with a mosaic of insulating pads 54 on a conducting substrate 52, certain limitations in operation exist. a
The exposed conducting areas 52 actually comprise crossed grid of both vertical and horizontal stripes; This crossed or double grid increases the possibility of failure due to insulator crossovers or insulator gaps. Furthermore, both the horizontal and vertical resolution are determined by the structure of the target, namely, the vertical and horizontal spacing dimensions.
To obtain maximum resolution from the configuration of FIGS. 5 and 6, the horizontal dimensions A and B of both the conducting and insulating areas should be minimized. If the minimum dimension consistent with edge resolution is defined as C, then A=C and B=C or A=B=C. However, then the ratio of conducting area to insulating area is 3:1 which is not ideal for information storage. This disparity between the conducting area and the insulating area results in nonuniform, relatively poor control of the Read electron beam by the storedcharge image.
In the improved structure of FIGS. 2 and 3, the widths of the insulating stripes 44 and the conducting stripes 43 are approximately equal. With this striped configuration, the dimensions may be made equal and minimized for maximum resolution while maintaining the area ratio at lzl. This ratio is optimum for satisfactory control of the Read beam. Moreover, because the electron beam traverses the target in a direction transverse to the longitudinal direction of the stripes, an additional advantage resides in the fact that resolution in the longitudinal direction of the stripes is no longer limited by the target structure, resulting in higher resolution capability. Since thisconstruction is a single grid, only one failure or bridging" mode is possible, namely, that across the stripes.
It is preferable to form the target of FIGS. 2 and 3 of doped silicon and silicon dioxide. The conducting areas are formed of the doped silicon, either P or N, and the insulating areas are formed of the silicon dioxide. Excellent targets of the type described are obtained when the silicon dioxide layer 'is genetically derived from the silicon. A genetically derived layer is one in which the insulating layer is derived from the conducting base or substrate material. This can be accomplished, for example, by immersing the silicon in a chemical solution such as N-Methyl-Acetamide or similar materials while applying a voltage to the silicon (anodically grown). Other methods of genetically deriving the insulating layer may also be used. I
A preferred process for forming a genetically derived target of the invention is illustrated in FIG. 4. A silicon wafer of doped silicon is specially cleaned with a suitable solvent to eliminate all surface imperfections and contaminants. It is then oxidized at temperatures of the order of l,ll ,250 C. so that a high quality silicon dioxide layer 62 is formed on silicon substrate 60. Layer 62 is about l micron thick.
The silicon dioxide surface is coated with a photosensitive lacquer 64. The unit is exposed to light through an optical mask of the desired pattern and then developed. The exposed portions of silicon dioxide layer 62 are then removed by dilute hydrofluoric .acid and the photoresist 64 is stripped from the surfaces of the stripes of silicon dioxide. This leaves a substrate of conducting silicon with a mosaic layer of insulating silicon dioxide. in the stripe configuration of FIGS. 2 and 3. the width of each of the stripes 43 is of the order of 3-7 microns.
It is also within the contemplation of the invention to form targets of silicon and silicon dioxide which have the pattern illustrated in FIGS. 5 and 6.
In FIG. 7 there is illustrated a target wherein the substrate 70 is conductive and the insulator film 72 is provided with holes 73 so that the desired pattern of substrate 70 is exposed to the electron beam.
In FIG. 8, substrate 74 is an insulator and conductive film 76 is provided with holes 77 so that the desired pattern of substrate 74 is exposed to the electron beam.
The embodiment of FIGS. 7 and 8 may be used with the particular patterns illustrated in FIGS. 2 and 5 or with any other desired pattern.
The desired target of one of the types described is installed in electron tube 10 which is produced in any manner which is well known in the art. By way of illustration. operation of electronic storage tubes of the invention may then proceed as follows.
To Write, target 22 is placed at about +250 volts and grid 14 is kept at approximately -60 volts. The information to be stored is placed on grid 14 with a peak-to-peak signal of approximately 10 volts. Under these conditions the information can be written in about one-thirtieth of a second (I TV frame).
For readout, the target is returned to about +8 volts. It is scanned in conventional raster format with the voltage on grid 14 adjusted to yield an output signal at terminal 32 of approximately 200 n. Continuous readout is possible under the above conditions for more than [0 minutes. Longer storage time is possible if the readout signals are smaller. Because of the dielectric relaxation time of silicon dioxide, with the beam off, the storage time will be a week or more.
The storage signal on the target can be erased by applying about volts to target 22, setting grid M at approximately zero volts to yield maximum beam current and scanning the area to be erased. Now, the erased area is ready to accept new information without the necessity for a prime cycle.
During the Write cycle the target voltage is about +250 volts. At this voltage, the electrons from the beam which impinge on the silicon dioxide layer 26 cause secondary emission of the order of 5:1 and the net electron current to the silicon dioxide is negative. At increased target voltage. the secondary emission ratio decreases because secondary electrons are formed deep in the silicon dioxide and have difficulty escaping. The Write cycle is performed in the flat portion of the curve which plots electronic current to the silicon dioxide against target voltage, namely, about +250 volts. There is another flat portion of the curve at about L000 to 2,000 volts.
The Write cycle is carried on at the flat region of the curve so that the surface of the silicon dioxide is charged positively. This positive charge is proportional to the number of electrons impinging on that area of the target. This yields a positive, linear relationship between the electron current from the gun and the positive charge on the target.
During the Read cycle, the silicon (conducting portion) plate or substrate 24 is returned to a potential which sets the insulating portion 26 negative with respect to cathode 16. The regions that are very negative prevent any current flow to the silicon (corresponding to a "black" picture). The regions which are only slightly negative will allow a significant current flow to the silicon (corresponding to a "white picture). Since the signal from the target may be inverted electrically, if desired, the very negative regions (no current flow) may correspond to a white" signal and the slightly negative regions (significant current flow) may correspond to a black" signal.
The Erase cycle simply charges the surface of the insulating areas to a uniformly negative value so that no electronic current can flow to the conducting substrate because of the repulsion effect of the coplanar insulating grid.
While particular embodiments and examples of the invention have been shown and described, it will be apparent to those skilled in the art that modifications are possible without departing from the spirit and scope of the invention.
The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. An electronic storage tube including a target which is comprised of a pattern of conducting and insulating areas, the tube comprising:
means for applying a signal to the target to establish a desired stored charge distribution on the insulating areas; and
means for detecting the stored charge distribution established on the target; and wherein the conducting areas are electrically connected to each other and are formed of silicon; and
the insulating areas are formed of silicon dioxide.
2. The invention of claim I wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
3. The invention of claim I wherein the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
4. The invention of claim 1 including:
a conducting substrate; and
an insulating layer overlying the conducting substrate;
the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
5. The invention of claim 1 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
6. The invention of claim 5 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
7. The invention of claim 5 wherein the pattern comprises a plurality of discrete insulating areas.
8. The invention of claim 1 wherein the insulating area is genetically derived from the conducting area.
9. The invention of claim 8 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
10. The invention of claim 8 wherein the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
11. The invention of claim 8 including:
a conducting substrate; and
an insulating layer overlying the conducting substrate;
the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
12. The invention of claim 8 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
13. The invention of claim 12 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
14. The invention of claim 12 wherein the pattern comprises a plurality of discrete insulating areas.
15. The invention of claim I including:
an insulating substrate; and
a conducting layer overlying the insulating substrate;
the conducting layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
16. The invention of claim wherein the pattern comprises a plurality of alternating and insulating and conducting stripes.
17. The invention of claim 15 wherein the pattern comprises a plurality of discrete insulating areas.
18. The invention of claim 15 wherein the insulating areas are genetically derived from the conducting layer.
19. The invention of claim 18 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
20. The invention of claim 18 wherein the pattern comprises a plurality of discrete insulating areas.
217 An electronic storage tube comprising:
a target having a pattern of alternating conducting areas and insulating areas;
an output terminal;
the conducting areas being electrically connected to the output terminal;
means for applying an input signal to the target such that a signal is stored thereon in the form of a desired stored charge distribution on the insulating areas;
means for scanning the target and obtaining an output signal at the output terminal which output signal is a function of the stored charge distribution on the insulating areas; and wherein the conducting areas are formed of silicon; and
the insulating areas are formed of silicon dioxide.
22. The invention of claim 21 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
23. The invention of claim 22 wherein the insulating areas are genetically derived.
Notice of Adverse Decision in Interference In Interference No. 98,015, involving Patent No. 3,631,294, S. R. Hofstein, ELECTRONIC STORAGE TUBE UTILIZING A TARGET COMPRISING BOTH SILICON AND SILICON DIOXIDE AREAS, final judgment adverse to the patentee was rendered Mar. 30, 1978, as to claims 2, 3, 6, 7, 9, 10, 13, 20, 22 and 23.
[Official Gazette April 14, 1981.]

Claims (22)

  1. 2. The invention of claim 1 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  2. 3. The invention of claim 1 wherein the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
  3. 4. The invention of claim 1 including: a conducting substrate; and an insulating layer overlying the conducting substrate; the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  4. 5. The invention of claim 1 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
  5. 6. The invention of claim 5 wherein the pattern comprises a plurality of alterNating insulating and conducting stripes.
  6. 7. The invention of claim 5 wherein the pattern comprises a plurality of discrete insulating areas.
  7. 8. The invention of claim 1 wherein the insulating area is genetically derived from the conducting area.
  8. 9. The invention of claim 8 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  9. 10. The invention of claim 8 wherein the pattern comprises a plurality of discrete insulating areas overlying a conducting substrate.
  10. 11. The invention of claim 8 including: a conducting substrate; and an insulating layer overlying the conducting substrate; the insulating layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  11. 12. The invention of claim 8 including a conducting substrate of silicon and insulating areas overlying the conducting substrate such that the pattern of conducting and insulating areas is formed thereby.
  12. 13. The invention of claim 12 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  13. 14. The invention of claim 12 wherein the pattern comprises a plurality of discrete insulating areas.
  14. 15. The invention of claim 1 including: an insulating substrate; and a conducting layer overlying the insulating substrate; the conducting layer having openings therein such that the pattern of conducting and insulating areas is formed thereby.
  15. 16. The invention of claim 15 wherein the pattern comprises a plurality of alternating and insulating and conducting stripes.
  16. 17. The invention of claim 15 wherein the pattern comprises a plurality of discrete insulating areas.
  17. 18. The invention of claim 15 wherein the insulating areas are genetically derived from the conducting layer.
  18. 19. The invention of claim 18 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  19. 20. The invention of claim 18 wherein the pattern comprises a plurality of discrete insulating areas.
  20. 21. An electronic storage tube comprising: a target having a pattern of alternating conducting areas and insulating areas; an output terminal; the conducting areas being electrically connected to the output terminal; means for applying an input signal to the target such that a signal is stored thereon in the form of a desired stored charge distribution on the insulating areas; means for scanning the target and obtaining an output signal at the output terminal which output signal is a function of the stored charge distribution on the insulating areas; and wherein the conducting areas are formed of silicon; and the insulating areas are formed of silicon dioxide.
  21. 22. The invention of claim 21 wherein the pattern comprises a plurality of alternating insulating and conducting stripes.
  22. 23. The invention of claim 22 wherein the insulating areas are genetically derived.
US840698A 1969-07-10 1969-07-10 Electronic storage tube utilizing a target comprising both silicon and silicon dioxide areas Expired - Lifetime US3631294A (en)

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US (1) US3631294A (en)
CA (1) CA1006568A (en)
DE (1) DE1964058B2 (en)
FR (1) FR2034086A1 (en)
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NL (1) NL7000313A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737715A (en) * 1970-02-02 1973-06-05 Rca Corp Bistable storage device and method of operation utilizing a storage target exhibiting electrical breakdown
US3740465A (en) * 1971-06-14 1973-06-19 Rca Corp Television frame storage apparatus
US3886530A (en) * 1969-06-02 1975-05-27 Massachusetts Inst Technology Signal storage device
US3892454A (en) * 1972-06-28 1975-07-01 Raytheon Co Method of forming silicon storage target
JPS50137028A (en) * 1974-04-17 1975-10-30
US3940651A (en) * 1974-03-08 1976-02-24 Princeton Electronics Products, Inc. Target structure for electronic storage tubes of the coplanar grid type having a grid structure of at least one pedestal mounted layer
JPS5136017A (en) * 1974-09-20 1976-03-26 Matsushita Electronics Corp NIDENSHI JUGATASOSAHENKANKAN
JPS5252519A (en) * 1975-10-27 1977-04-27 Matsushita Electric Ind Co Ltd Pickup storage tube and camera equipment
US4051406A (en) * 1974-01-02 1977-09-27 Princeton Electronic Products, Inc. Electronic storage tube target having a radiation insensitive layer
US4302703A (en) * 1969-11-10 1981-11-24 Bell Telephone Laboratories, Incorporated Video storage system
US4389591A (en) * 1978-02-08 1983-06-21 Matsushita Electric Industrial Company, Limited Image storage target and image pick-up and storage tube
US4490643A (en) * 1969-01-08 1984-12-25 Rca Corporation Storage device having a semiconductor target

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US2859376A (en) * 1955-05-19 1958-11-04 Bell Telephone Labor Inc Electron discharge storage device
US2912615A (en) * 1957-02-28 1959-11-10 Emi Ltd Cathode ray tubes for colour television
US3277333A (en) * 1963-12-13 1966-10-04 Itt Storage tube system and method
US3293474A (en) * 1963-08-01 1966-12-20 Tektronix Inc Phosphor dielectric storage target for cathode ray tube
US3339099A (en) * 1966-05-31 1967-08-29 Tektronix Inc Combined direct viewing storage target and fluorescent screen display structure
US3401293A (en) * 1966-11-28 1968-09-10 Tektronix Inc Mesa type combined direct viewing storage target and fluorescent screen for cathode ray tube
US3428850A (en) * 1967-09-12 1969-02-18 Bell Telephone Labor Inc Cathode ray storage devices
US3480482A (en) * 1967-10-18 1969-11-25 Hughes Aircraft Co Method for making storage targets for cathode ray tubes

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2859376A (en) * 1955-05-19 1958-11-04 Bell Telephone Labor Inc Electron discharge storage device
US2912615A (en) * 1957-02-28 1959-11-10 Emi Ltd Cathode ray tubes for colour television
US3293474A (en) * 1963-08-01 1966-12-20 Tektronix Inc Phosphor dielectric storage target for cathode ray tube
US3277333A (en) * 1963-12-13 1966-10-04 Itt Storage tube system and method
US3339099A (en) * 1966-05-31 1967-08-29 Tektronix Inc Combined direct viewing storage target and fluorescent screen display structure
US3401293A (en) * 1966-11-28 1968-09-10 Tektronix Inc Mesa type combined direct viewing storage target and fluorescent screen for cathode ray tube
US3428850A (en) * 1967-09-12 1969-02-18 Bell Telephone Labor Inc Cathode ray storage devices
US3480482A (en) * 1967-10-18 1969-11-25 Hughes Aircraft Co Method for making storage targets for cathode ray tubes

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490643A (en) * 1969-01-08 1984-12-25 Rca Corporation Storage device having a semiconductor target
US3886530A (en) * 1969-06-02 1975-05-27 Massachusetts Inst Technology Signal storage device
US4302703A (en) * 1969-11-10 1981-11-24 Bell Telephone Laboratories, Incorporated Video storage system
US3737715A (en) * 1970-02-02 1973-06-05 Rca Corp Bistable storage device and method of operation utilizing a storage target exhibiting electrical breakdown
US3740465A (en) * 1971-06-14 1973-06-19 Rca Corp Television frame storage apparatus
US3892454A (en) * 1972-06-28 1975-07-01 Raytheon Co Method of forming silicon storage target
US4051406A (en) * 1974-01-02 1977-09-27 Princeton Electronic Products, Inc. Electronic storage tube target having a radiation insensitive layer
US3940651A (en) * 1974-03-08 1976-02-24 Princeton Electronics Products, Inc. Target structure for electronic storage tubes of the coplanar grid type having a grid structure of at least one pedestal mounted layer
JPS50137028A (en) * 1974-04-17 1975-10-30
JPS5136017A (en) * 1974-09-20 1976-03-26 Matsushita Electronics Corp NIDENSHI JUGATASOSAHENKANKAN
JPS5513104B2 (en) * 1974-09-20 1980-04-07
JPS5252519A (en) * 1975-10-27 1977-04-27 Matsushita Electric Ind Co Ltd Pickup storage tube and camera equipment
US4389591A (en) * 1978-02-08 1983-06-21 Matsushita Electric Industrial Company, Limited Image storage target and image pick-up and storage tube

Also Published As

Publication number Publication date
DE1964058B2 (en) 1972-04-20
DE1964058A1 (en) 1971-01-28
GB1288049A (en) 1972-09-06
NL7000313A (en) 1971-01-12
FR2034086A1 (en) 1970-12-11
CA1006568A (en) 1977-03-08

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