US3576533A

US3576533A - Comparison of contents of two registers

Info

Publication number: US3576533A
Application number: US665595A
Authority: US
Inventors: Akira Yokoyama
Original assignee: Gencorp Inc
Current assignee: Fujitsu General Ltd; Aerojet Rocketdyne Holdings Inc
Priority date: 1966-09-06
Filing date: 1967-09-05
Publication date: 1971-04-27
Anticipated expiration: 1988-04-27

Abstract

A system in calculating devices for performing a comparison of the contents of two registers decided by priority of output between progress type registers, the numerical contents of the registers being fixed by the delay from standard timing of an output produced when constant periodic stepping pulses are supplied.

Description

United States Patent Inventor Akira Yokoyama Kawasaki-shi, Japan Appl. No. 665,595 Filed Sept. 5,1967 Patented Apr. 27, 1971 Assignee The General Corporation Kawasaki-shi, Kanagawa-ken, Japan Priority Sept. 6,1966, Sept. 17, 1966, June 10,

Japan 4168454, 41-61096 and 42-36780 COMPARISON OF CONTENTS OF TWO REGISTERS 10 Claims, 13 Drawing Figs.

U.S. Cl 340/ 146.2,

235/160, 235/177 Int. Cl G061 7/02 Field of Search 340/1462;

[56] References Cited UNITED STATES PATENTS 3,006,549 10/ 1 961 Hughes 235/160 3,126,475 3/1964 Coddington et al. 235/160 3,161,765 12/1964 Hoberg et al. 235/1 77X 2,694,801 1 1/ 1954 Bachelet 340/146.2X 3,439,336 4/1969 Toifl et al. 340/1462 OTHER REFERENCES Kintner, Electronic Digital Techniques, 1968, pp. 159- 162.

Primary Examiner-Malcolm A. Morrison Assistant ExaminerDavid H. Malzahn Attorney-Ernest G. Montague ABSTRACT: A system in calculating devices for performing a comparison of the contents of two registers decided by priority of output between progress type registers, the numerical contents of the registers being fixed by the delay from standard timing of an output produced when constant periodic stepping pulses are supplied.

@Fdr ur l5 SR Stepping pulse means RJFLL 0 Timing pulse of m;

Stepping pulse PATENTEU APR 2 7 1971 SHEET 1 BF 6 -)6 Shift down 5 Quotient I FIG.2.

Quotient ae: Adding back A'k I'm (not to be counted) t2 not to be counted) l VENTOR okoya 'nd Mfom t Pmiman zmn 3.576.533

SHEET 3 OF 6 r A .FIG .50 And p n. And 2 Output I 3 I g If SP x S R i Y I Q s Ste in pui Register means 2 Register 6 0 Timing pulse of the Stepping pulses FIG. 5b

iO98T65432IO98T65432IO9 SteppingpuisesJlll lillllllltltl'lllil Re isteri i i i i v i put i l I i Register 2 i 1 output l t t i I flip- Hop l I 5 reset 1 And i 4 open .i

And 1 I i i i 5 open j I I j I I Output B l v I When the content of register i is 7 and the content of register 2 is 5.

INVENTOR Ak n) Vvkoyama BY Mi- Plinth Mfume uinn? 1 A wmmsmzm 31313516553 SHEET u. 0F 6 -l l 1 I ppi g pulse; 1 Regi sfe I;

r Output, 'Register1 '2 T j s'e'f 1 T? And I ,When -the g:omem' of r e'gifjril (and the content .of register 7 2' is T s epping m 1098765432 osers-5 pal-:5 ill 1 I I 1 1 1'' 1' 1 H.

nd 1-1 I puisg- Register I 0y tput INVENTOR A' Y0 k0 ya PATENTED m2? 15m 3:576; 533

SHEET 8 0F 6 FIG .80

i 3i Stepping pulse means b I WA WA output Adding pulses open close 9 timing puise 0 E out w of the stepping WE p pulses FIG. 8b

Stepping pulse I WE output 9 l i i i i i Adding pulse I 8 l i i i G open Adding pulse input to WA i I I i i i When 7+5==i all input to WA I INVENTOR Mira Yo k0 ya m;

BY Mi- How/1 9 WWW;

COMPARISON OF CONTENTS OF TWO REGISTERS The present invention relates to a system for the control of electronic calculating devices, such as desk calculators, and the like.

In ordinary arithmetic operations, it is often necessary to make a comparison of the contents between two numbers. Conventional methods of comparison, however, have been rather complicated.

One object of the present invention is to provide a simplified method of comparison between two numbers stored in two registers.

The present invention is especially efficient when applied to small-scale devices employing decimal numbers. In devices of this kind, registers of plural numbers are ordinarily equipped, and among the numerical values stored in each register, a calculation is performed by carrying out a variety of operations. When the calculation is performed, it is often convenient if the comparison of the contents of two registers is performed.

It is one object of the present invention to provide a system for comparing the numerical value contents of two register contents in which the comparison of the register contents is performed by the priority of outputs among progress type registers by the delay from timing of the produced output when constant period stepping pulses are supplied as the input.

It is another object of the present invention to provide a comparison system of register contents in accordance with the above-mentioned object wherein by the output of one of two registers, flip-flop circuits are set, and by the other output, the flip-flop circuit is reset, and depending upon which of the two output terminals produces the output, which output terminals may be switched by the condition of the flip-flop at a reference timing pulse of the stepping pulses, the comparison of the contents of the two registers is determined. It is yet another object of the present invention to provide a comparison system of register contents in accordance with the above-mentioned objects wherein, when the contents of both registers coincide, the equality of the contents of both registers are obtained by coinciding outputs in the output of both registers.

Since the comparison becomes more complicated when the two numbers to be compared are of a plurality of units, it has been customary to make an indirect comparison by calculating-the difference of the two numbers first and then obtaining as the result a symbol of either positive or negative.

Accordingly, another object of the present invention is to make a direct comparison of the contents between two numbers stored in two plural-unit registers, and simplify the operation circuits by eliminating an extra subtraction.

In the arithmetic operation it is the operation of division that especially requires a comparison between two numbers. As to the method of division, the restoring method and the nonrestoring method have been known, which will be described hereinafter. In these methods the comparison is made indirectly between two numbers and the control is complicated.

Accordingly, it is a further object of the present invention to provide a simplified system for applying the above-mentioned comparison to the division operation.

With these and other objects in view which will become apparent in the following detailed description, the present invention will be clearly understood in connection with the accompanying drawings, in which:

FIG. 1 illustrates a desirable method of division in calculating devices;

FIG. 2 illustrates division by the restoring method;

FIG. 3 illustrates division by the nonrestoring method or the Von Neuman's method;

FIG. 4a is a block diagram of a dynamic register used in the present invention for the decimal system;

FIG. 4b is a graph showing the stepping pulses and the register output;

FIG. 5a is a block diagram of a circuit for perfonning a comparison of the contents of two dynamic registers;

FIGS. 5b 1 and 5b 2 are time graphs illustrating the operation of the circuit of FIG. 5 for two different examples, respectively;

FIG. 6 is a circuit for performing the method of comparison of the magnitude of the contents of two n-unit registers;

FIG. 7a is a block diagram illustrating addition in a dynamic register;

FIG. 7b is a time graph explaining the circuit of FIG. 7a;

FIG. 8a is a block diagram of a circuit for performing an automatic comparison between the divisor and the partial remainder of the subtraction carried out in the division; and

FIG. 8b is a time graph illustrating the operation of the circuit of FIG. 80.

Referring now to the drawings, and more particularly to FIG. I, a simplified method of division, for example, performed by a desk calculator is illustrated. Division is usually carried out by a repetitive process of subtraction. Namely, a dividend is placed in a register A (not shown) and a divisor, in a register E (not shown), and after lining-up the most significant digits of both, the quotient is obtained by counting the frequency of the subtractions until the partial remainder in register A becomes less than the divisor in register E, the frequencies of the subtractions being stored in a Q-register in which the quotient is received. Then the digits are shifted down (to the right) and then, the same process as above-mentioned is repeated, as illustrated, for example, in the instance of the operation 430535, shown in FIG. 1. (Every shift down, the unit of the Q-register in which the subtraction frequencies are stored is shifted one by one to the right.)

It is clearly understood that in this step of the operation a comparison is needed between the contents of the A-register and the E-register.

There are two methods described below for carrying out division without employing a method of comparison.

In the restoring method shown in FIG. 2 subtraction is carried out until the partial remainder becomes negative. When the partial remainder has become negative, the following two items are to be considered. Firstly, the subtraction frequencies are larger by one than the number representing the quotient. Secondly, a process to restore the partial remainder to the proper numerical value is required. These processes obviously constitute extra operations when compared with that of the first method.

In the nonrestoring or Von Neuman's method shownin FIG. 3, the partial remainder is not restored to the proper numerical value before the shift-down, unlike the restoring method, even when it has become negative.

In the next A unit the divisor is added until the partial remainder turns from negative to positive and the complement of the number of addition frequencies is made to be the next unit of the quotient. Then the subtraction and the addition follow alternately in the same way. The reason why the proper quotient is obtained in this method is very well known.

The nonrestoring method is easier to employ in some cases than the restoring method, but it is still complicated when compared with the first method.

In the present invention a process for carrying out the first method in a simple way is disclosed.

According to the present invention, however, a comparison of the contents of two registers may be made very simply, and especially, since checking is made from the lowest units. Still further, in the subtraction process, a comparison of a partial remainder and divisor may be made, and a signal of the possibility of a succeeding subtraction may be obtained during an operating subtraction, thereby simplifying the division control exceedingly.

The register employed in the present invention is of an n progress counter type for each unit, which produces one output per n inputs. The content of the register is determined by the output phase (i.e., the delay of the output timing with respect to reference intervals) when the stepping pulses of a constant interval or period are supplied as the input. Such a register is hereinafter referred to as a dynamic register.

FIG. 4a illustrates the decimal dynamic register showing a stepping pulses sent to the register producing an output. In FIG. 412 time is shown on the abscissa and one cycle of the stepping pulses is one phase interval. The reference timing is the timing, and the other timings are assigned numbers as shown therein. For instance, if the register content is 7 at the 0 timing, the output is produced at the 7 timing when three inputs are supplied. That is, the number of the phase at which the output is produced represents the register content at the reference timing.

When such dynamic registers as above are employed, a magnitude comparison of the contents is performed according to the priority of output of both produced when the same stepping pulses are supplied thereto.

Referring now to the drawings, and more particularly to FIG. a, a circuit which can perform the comparison of the numerical contents of two registers comprises register 1 and register 2, to both of which stepping pulses are simultaneously supplied from a stepping pulse means SP. A flip-flop circuit 3 is provided, and the output of both of the

registers

1 and 2 triggers S on the set side and R on the reset side of the flip-flop circuit 3, respectively. The set state of flip-flop 3 opens an AND gate 4 and the reset state opens an AND gate 5.

Referring now to FIG. 5b 1, for example, when the contents of register 1 are greater than those of register 2, after a certain reference timing, the output of register 1 is produced earlier than the output of register 2 and flip-flop 3 is set, in the first place, by the output of register 1. Next the flip-flop 3 is reset by the output of register 2. A 0 timing pulse means SP, of the stepping pulses sends the next 0 timing pulse together to the AND

gates

4 and 5. Accordingly, when the next 0 timing pulse of the stepping pulses occurs it passes through the then open AND gate 5 and produces output B.

Referring now to FIG. 5b 2, on the other hand, when the contents of register 1 are less than those of register 2, flip-flop 3 produces output A upon the occurrence of a 0 timing pulse of the stepping pulses since it is set by the output of the register 1 after being reset by the output of register 2. Consequently, according to which of output A or output B is produced, the comparison of the numerical value contents of the

registers

1 and 2 is made.

When the contents of two registers are equal, the outputs in both registers are produced at the same time. The treatment in this case varies depending on the object of the operation. One example will be described later, and it would be enough for now to say that the coincident circuit, the delay circuit, and the inhibit circuit universally known are employed for the process.

The explanation as mentioned above refers to a comparison method between contents of a one unit register. Using this alone, there exists a number of useful applications.

Referring now again to the drawings, and more particularly to FIG. 6, a method of comparison of the contents of plural register units are explained. The numeral value contents of register ll of n register units, and of register 12 of n register units are to be compared. The input to registers 11 and 12 from the stepping pulse SP is switched in turn from the lowest unit to the next upper unit, by means of the output of a stepcounter 22 which proceeds at each 0 timing pulse of the stepping pulses.

Every time the step-counter 22 proceeds respective corresponding AND gates and 21 are switched over from the lowest unit toward the higher unit. Accordingly, l0 stepping pulses are supplied in turn from the lowest unit toward the next higher unit of the registers 11 and 12. The outputs of both registers are sent to the flip-flop 13 through the delay-

circuits

26 and 27 and inhibit-

gates

17 and 18. The flip-flop 13 and AND

gates

14 and 15 correspond to the flip-flop 3, and AND

gates

4 and 5 of FIG. 5a.

In the interval from the first 0 timing pulse to the next 0 timing pulse, a magnitude decision among the lowest units of registers l1 and 12 is made, as stated already, and at the end of the interval, flip-flop circuit 13 is in a state of set or reset according to the result comparing their numerical value contents. During the interval from the next 0 timing pulse, a comparison of the numerical value contents of the two second units is made, and the state of flip-flop 13 is fixed anew from the result. Thus, the result of the comparison of the numerical value contents of any unit is of no use in the next unit, and the existing state of the flip-flop 13 is cancelled and is fixed again according to the numerical value contents of the next unit. If the units were equal, an output is produced from AND gate 16, closing inhibit-

gates

17 and 18; and the output of registers 11 and 12 fails to reach flip-flop 13, which is retained in the unchanged state. Delay

circuits

26 and 27 ensure the closing of inhibit-

gates

17 and 18 before the outputs of registers 11 and 12 reach inhibit-

gates

17 and 18.

In this way, after making comparison of the numerical value contents of the entire plural unit registers, the state of flip-flop 13 is fixed depending upon the result of the unequal and highest unit, which serves to correctly compare the numerical value contents of both registers. Accordingly, at the last unit, by checking AND

gates

14 and 15 by a 0 timing pulse of the stepping pulses, output A or B is produced according to the comparison of the numerical value contents of plural unit registers l1 and 12. AND gate 19 is the circuit which supplies pulses to AND

gates

14 and 15 only after the last unit has been finished when a 0 timing pulse is sent to AND gate 14 from the last stage of the step counter 22.

When the contents of both registers are equal, the output is produced n times from the AND gate 16. Accordingly, one of the methods to know if the contents of both registers are equal is to ascertain if the number ofthe output from the AND gate 16 is equal to n.

The plurality of AND

gates

20 and 21 connected between the step counter 22 of stepping pulse means SP, and the units of the registers 11 and 12 comprise part of the switching means for sending the stepping pulses to the corresponding units of the registers, in turn, and the

OR gates

23 and 24 are connected to the outputs of the units of the registers 11 and 12, respectively.

By way of another example, when the content of register 11 equal or greater than the content of register 12 and the content of the register 11 less than the content of the register 12 content are to be decided, the flip-flop 13 has only to be reset at the beginning of the operation. By doing so the output B is produced either in the case where the content of the register 11 is larger than the content of the register 12 or in the case where they are equal.

There are many applications of such a method for comparison. One of the most useful applications of this process is seen in the case ofdivision.

In this case, the method is adopted in which, as mentioned above, dividend and divisor are received respectively in registers A and E (not shown). The corresponding unit of each register A and E is transferred into one unit operating registers W and W unit by unit. After the operation these contents are restored to the registers A and E. In order to manage the carry from each unit, this operation should begin at the lowest unit and proceed toward the higher unit. The numerical value remaining in working register W immediately after the operation is a partial remainder, so that the comparison carried out between the numerical values in the working registers W A and W (divisor) by means of the above-mentioned method before they are restored to the registers A and E, corresponds to the comparison carried out between the partial remainder and the divisor in order to help decide which of the subtraction and the shift-down should follow. Accordingly, the method shown in FIG. 1 is realized in a simple way.

The foregoing is a description about the 4-step process of reading-out, operation, comparison, and restoring. It is also possible to carry out the operation and the comparison at the same time, which will be described hereinafter.

As mentioned above, the content x in a dynamic register means that the state .in the register is x at the 0 timing pulse of the stepping pulses and that the output is produced at the x timing of the stepping pulses. Since there exist 10 stepping pulses (one timing pulse to the next 0 timing pulse), the value of the register remains unchanged so long as the stepping pulses are supplied constantly to the register.

Now, if y adding pulses are added besides the stepping pulses, (10+ pulses are supplied as input to the register in the interval from one 0 timing pulse to the next 0 timing pulse, and the content of the register turns into (x+y). (Since a dynamic register is a counter type, the addition of mod. 10 is performed). That is, by adding additional y adding pulses the operation of (x+y) is carried out. FIG. 7b shows an example of operation in the case of +3=8. When the carry occurs the content of the register becomes x+y (mod. l0). The comparison is made with x+y (mod. l0), and it does not affect the circuits in the present invention whether the carry occurs or not.

The subtraction is carried out in general by adding the complement. Let the 9s complement of y, then xy is substituted by x+31 A method in which the operation and the comparison are carried out at the same time in the division is shown in FIG. 80. When x is read on W A of working register 31, and y on W,.; of working register 32, the circuit performing x+y is shown in FIG. 8a, and its time chart on FlG. 8b.

The stepping pulses are sent in common to the working registers 31(W,,) and 32 (W and they are also sent to the gate-circuit 34 through a delay circuit 33. The gate-circuit 34 opens at the 9" timing pulse of the stepping pulses and is closed by the output of the working register 32; accordingly the number of pulses passing through the gate-circuit 34 in the interval becomes the 9's complement of the content of the working register 32 as shown in FIG. 8b. Accordingly, when these pulses are supplied to the working register 31, as adding pulses, it follows that the difference between the two remains as the dividend.

Therefore, it will be easily understood referring to FIG. 8b that the number of adding pulses passing through gate 34 corresponds to y. FIG. 8b shows the case of an operation 7-5=7 +5. The output of working register 31 is produced at every 7 timing pulses if no adding pulse exists, but, on account of the entrance of an adding pulse, the first output after the gate 34 opens is produced at the 8" timing pulse. Thereafter, by the addition of still three more stepping pulses, before the gate 34 closes, there is produced an output at the next 1" timing pulse. Afterwards, since no adding pulse exists, the contents of the working register 31 becomes l, namely 7+5 (mod. 10). (The reason that 7-5 does not become 2, but l, is due to complement adding, and is correct). After gate 34 is closed, since no adding pulse exists, and afterwards, in the cases when the output is produced from working register 31, it is always x+ y (mod. l0) y, and when the output is not produced, it is x+y (mod. l0) y. In the latter case, the output is always produced before the output production of working register 32.

Since the working register 32 produces the output and the content of the working register 31 turns into the partial remainder when the gate-circuit 34 closes, the partial remainder is always less than the content of the working register 32 if the output of the working register 31 is produced from the output of working register 32, until the next 0 timing pulse. If the output is not produced, the partial remainder is al ways larger than the content of the working register 32. In this way, by employing the output of the working register 31 produced in the operation, the comparison between the partial remainder and the divisor can be made, and the process can be simplified in 3 steps of the reading'out, the operation,

and restoring.

As described above, in the present invention the comparison between two register contents can be made very quickly and easily, and an extremely simplified system can be organized especially when applied to division.

While I have disclosed several embodiments of the present invention it is to be understood that these embodiments are given by example only and not in a limiting sense.

1 claim:

1. A comparison decision system of register contents comprising: 7

two registers of the n-progress type each storing a numerical value content to be compared with each other; means for simultaneously applying the same constant period stepping pulses to said two registers; each of said two registers producing an output in response to an applied stepping pulse corresponding to its numerical value content; and means for receiving said outputs of said two registers in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two registers, which comparison output signal is dependent upon said time priority of said outputs of said two registers. 2. The system, as set forth in claim 1 wherein when the contents of said registers are equal, the equality of said contents of said registers is determined by a coincident output from the output of said registers. 3. The system, as set forth in claim 1, wherein said means for receiving the outputs of said registers and for producing said comparison output signal comprises:

a flip-flop means operatively connected to said registers for changing the state of said flip-flop means and providing change of state output signals upon receiving the respective outputs from said registers;

AND gates, each connected, respectively, for receiving said change of state output signals from said flip-flop means; and

means for sending a 0 reference pulse of said stepping pulses simultaneously to said AND gates.

4. The system, as set forth in claim 1, further comprising;

two plural unit registers and circuit means for carrying out division by a plurality of subtractions in which the subtractions are performed from the lowest unit toward the highest unit; and

said two registers of the n-progress type constituting single unit registers, and receiving readouts of corresponding units of said plural unit registers from the lowest corresponding units to the highest corresponding units, the possibility or impossibility of a subsequent subtraction being detemiined by the comparison decision of the numerical value contents of said single unit registers.

5. The system, as set forth in claim 1, for division by a plurality of subtractions and for determining the possibility or impossibility of subsequent subtraction by comparison between the partial remainder and the divisor, comprising:

two plural unit registers and circuit means for carrying out division by a plurality of subtractions performed by adding to the dividend the same number of adding pulses as that of the complement of the divisor;

said two registers of the n-progress type constituting single unit working registers and receiving readouts of corresponding units of said plural unit registers in turn from the lowest corresponding units to the highest corresponding units; and

the means for receiving the outputs comprising a flip-flop for being set and reset by said outputs, respectively, the possibility or impossibility of subsequent subtraction being decided by comparison of the partial remainder and the divisor, by a comparison of said outputs of said working registers.

6. A comparison decision system of register contents, comprising: two plural unit registers each comprising a plurality of said n-progress type register units, each storing a numerical value content and constituting a plurality of ordered register units, covering from a lowest register unit to a highest register unit;

means for simultaneously applying the same cons'tanbperiod stepping pulses to two corresponding ordered register units of said two plural unit registers;

each of said two corresponding ordered register =units producing an output in response to an applied stepping pulse corresponding to its numerical value content;

means for receiving said outputs of said two corresponding ordered register units in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two corresponding ordered register units, which comparison output signal is dependent upon said time priority of said outputs of said two corresponding ordered register units; and

means for switching said stepping pulses so that the latter are sent in turn to said plurality of corresponding ordered register units of said plural unit registers from the lowest register unit to the highest register unit.

7. The system, as set forth in claim 6, wherein said means for receiving said outputs comprises a flip-flop means operatively connected to the outputs of each of said plurality of ordered register units of said plural unit registers for being set or reset in accordance with the comparative magnitude of the numerical value contents of said corresponding ordered rcgister units of said plural unit registers, and being set or reset again in turn when said stepping pulses are switched to next corresponding ordered register units of said plural unit registers; and means for inhibiting a change in condition of said flip-flop means when the magnitude of the numerical value contents are equal in corresponding ordered register units of said plural unit registers which are then receiving said stepping pulses, whereby the relative magnitude of the ordered numerical value contents of said plural unit registers are determined by the condition of said flip-flop means after the comparison of the highest corresponding ordered register units of said plural unit registers receiving said stepping pulses.

8. The system, as set forth in claim 7, wherein said inhibiting means includes:

an AND gate operatively connected to the outputs of corresponding ordered register units of said plural unit registers;

an inhibit gate connected to the output of said AND gate and to said flip-flop means; and

a delay circuit connected between the outputs of said ordered register units and said inhibit gate,

9. The system, as set fonh in claim 7, wherein:

said switching means is a step counter;

means for sending a plurality of periodic 0 reference pulses of said stepping pulses to said step counter;

said step counter switching said sending of said stepping pulses in turn to said plurality of ordered register units, respectively, upon receiving each of said 0 reference pulses; and

said switching means further includes a plurality of AND gates each connected at its output to one of said ordered register units, respectively, and each connected at its input to said means for applying a plurality of stepping pulses and to the output of a stage of said step counter corresponding to the respective ordered register unit to which said AND gate is connected.

10. A system for division by a plurality of subtractions in which the subtraction and comparison are performed together, comprising:

a first working register of the n-progress type storing a numerical value content;

a second working register of the n-progress type storing a numerical value content;

a delay circuit;

means for simultaneously applying the same constant period stepping pulses to said first and second working registers and said delay circuit;

each of said registers producing an output in response to an applied stepping pulse corresponding to its numerical value content;

a gate means receiving delayed pulses from said delay circult;

means for supplying a 9th timing pulse of said stepping pulses to said gate circuit for opening same;

said gate means operatively connected to said second working register for being closed upon receiving an output signal from said second working register; and said gate means operatively connected to said first working register and for sending said delayed pulses to said first working register when it is open.

Claims

1. A comparison decision system of register contents comprising: two registers of the n-progress type each storing a numerical value content to be compared with each other; means for simultaneously applying the same constant period stepping pulses to said two registers; each of said two registers producing an output in response to an applied stepping pulse corresponding to its numerical value content; and means for receiving said outputs of said two registers in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two registers, which comparison output signal is dependent upon said time priority of said outputs of said two registers.

2. The system, as set forth in claim 1 wherein when the contents of said registers are equal, the equality of said contents of said registers is determined by a coincident output from the output of said registers.

3. The system, as set forth in claim 1, wherein said means for receiving the outputs of said registers and for producing said comparison output signal comprises: a flip-flop means operatively connected to said registers for changing the state of said flip-flop means and providing change of state output signals upon receiving the respective outputs from said registers; AND gates, each connected, respectively, for receiving said chaNge of state output signals from said flip-flop means; and means for sending a 0 reference pulse of said stepping pulses simultaneously to said AND gates.

4. The system, as set forth in claim 1, further comprising; two plural unit registers and circuit means for carrying out division by a plurality of subtractions in which the subtractions are performed from the lowest unit toward the highest unit; and said two registers of the n-progress type constituting single unit registers, and receiving readouts of corresponding units of said plural unit registers from the lowest corresponding units to the highest corresponding units, the possibility or impossibility of a subsequent subtraction being determined by the comparison decision of the numerical value contents of said single unit registers.

5. The system, as set forth in claim 1, for division by a plurality of subtractions and for determining the possibility or impossibility of subsequent subtraction by comparison between the partial remainder and the divisor, comprising: two plural unit registers and circuit means for carrying out division by a plurality of subtractions performed by adding to the dividend the same number of adding pulses as that of the complement of the divisor; said two registers of the n-progress type constituting single unit working registers and receiving readouts of corresponding units of said plural unit registers in turn from the lowest corresponding units to the highest corresponding units; and the means for receiving the outputs comprising a flip-flop for being set and reset by said outputs, respectively, the possibility or impossibility of subsequent subtraction being decided by comparison of the partial remainder and the divisor, by a comparison of said outputs of said working registers.

6. A comparison decision system of register contents, comprising: two plural unit registers each comprising a plurality of said n-progress type register units, each storing a numerical value content and constituting a plurality of ordered register units, covering from a lowest register unit to a highest register unit; means for simultaneously applying the same constant period stepping pulses to two corresponding ordered register units of said two plural unit registers; each of said two corresponding ordered register units producing an output in response to an applied stepping pulse corresponding to its numerical value content; means for receiving said outputs of said two corresponding ordered register units in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two corresponding ordered register units, which comparison output signal is dependent upon said time priority of said outputs of said two corresponding ordered register units; and means for switching said stepping pulses so that the latter are sent in turn to said plurality of corresponding ordered register units of said plural unit registers from the lowest register unit to the highest register unit.

7. The system, as set forth in claim 6, wherein said means for receiving said outputs comprises a flip-flop means operatively connected to the outputs of each of said plurality of ordered register units of said plural unit registers for being set or reset in accordance with the comparative magnitude of the numerical value contents of said corresponding ordered register units of said plural unit registers, and being set or reset again in turn when said stepping pulses are switched to next corresponding ordered register units of said plural unit registers; and means for inhibiting a change in condition of said flip-flop means when the magnitude of the numerical value contents are equal in corresponding ordered register units of said plural unit registers which are then receiving said stepping pulses, whereby the relative magnitude of the ordered numerical value contents of said plural uniT registers are determined by the condition of said flip-flop means after the comparison of the highest corresponding ordered register units of said plural unit registers receiving said stepping pulses.

8. The system, as set forth in claim 7, wherein said inhibiting means includes: an AND gate operatively connected to the outputs of corresponding ordered register units of said plural unit registers; an inhibit gate connected to the output of said AND gate and to said flip-flop means; and a delay circuit connected between the outputs of said ordered register units and said inhibit gate.

9. The system, as set forth in claim 7, wherein: said switching means is a step counter; means for sending a plurality of periodic 0 reference pulses of said stepping pulses to said step counter; said step counter switching said sending of said stepping pulses in turn to said plurality of ordered register units, respectively, upon receiving each of said 0 reference pulses; and said switching means further includes a plurality of AND gates each connected at its output to one of said ordered register units, respectively, and each connected at its input to said means for applying a plurality of stepping pulses and to the output of a stage of said step counter corresponding to the respective ordered register unit to which said AND gate is connected.

10. A system for division by a plurality of subtractions in which the subtraction and comparison are performed together, comprising: a first working register of the n-progress type storing a numerical value content; a second working register of the n-progress type storing a numerical value content; a delay circuit; means for simultaneously applying the same constant period stepping pulses to said first and second working registers and said delay circuit; each of said registers producing an output in response to an applied stepping pulse corresponding to its numerical value content; a gate means receiving delayed pulses from said delay circuit; means for supplying a 9th timing pulse of said stepping pulses to said gate circuit for opening same; said gate means operatively connected to said second working register for being closed upon receiving an output signal from said second working register; and said gate means operatively connected to said first working register and for sending said delayed pulses to said first working register when it is open.