US3548405A - Receiving distributor circuit - Google Patents

Description

Dec. 15,' 1970 c3. J. HOLLOMAN 3,548,405

RECEIVING DISTRIBUTOR CIRCUIT Filed Dec. l2, 1966 'United States Patent O 3,548,405 RECEIVING DISTRIBUTOR CIRCUIT Charles J. Holloman, Stamford, Conn., assignor to Trans- Lux Corporation, New York, N.Y., a corporation of Delaware Filed Dec. 12, 1966, Ser. No. 600,875 Int. Cl. H03k 13/258 U.S. Cl. 340-347 4 Claims ABSTRACT F THE DISCLOSURE This invention is directed to a receiving distributor circuit for allocating different portions of received signal series to different output positions for recreating the signal information in its visual representations. Circuitry is provided by which a series of coded signal representations may be supplied through a shift register circuit of a selected number of stages formed from a plurality of cascaded flip-flop circuits which are controlled by pulsing. The signals are serially impressed as binary information and applied under the control of the pulses to shift the signal series from one end of the register to the other prior to its release. The operation is controlled by an oscillator which is activated under the influence of a start input signal, with operating continuing until the full signal series is received and message storage effects are maintained until the signals can be displayed on any appropriately controlled viewing unit.

FIELD OF THE INVENTION The invention describes circuitry for controlling the inversion of received electrical signals into controlled pulse or the like to provide for the development of visual portrayals of the signaling information.

THE CIRCUITRY TO CONTROL SIGNAL DISTRIBUTION To transmit information from a point of origin to various receiving points, codes are frequently established and set up. From these different functional representations, observable effects in the form of letters, figures, symbols, pictures and the like can be recreated. These signal series are generally known as character assembled coding systems. The technique herein embodied finds many uses, but one such use is in the distribution of information concerning stock transactions. By these transactions, the different stocks which have been traded are identified by coded letter identifications and by the price at which the transaction is completed. In many instances, special designations are also provided to portray what might be considered as non-routine dealings, such as dealings in preferred stocks, dealings in rights, dealings in stocks to be issued and so on.

The various codes make possible information distribution for recreating the transactions by lighting controls or by controls of indicating mechanisms printing directly to a ticker tape. In the case of stock transactions, these codings are established by the New York Stock Exchange. They usually comprise, for each letter or gure, a starting sync pulse which is followed by control pulses which are present or absent in any of six (for the majority of codes) different equal time-spaced positions. The signal series isI then usually followed by a rest period which may consist of one, two or more pulse periods. Normally, for letter designations, the pulse in the so-called sixth position is missing. Wherever the sixth pulse is present in the pulse series, it usually indicates that a `figure is to be printed or represented. The preceding presence or absence of pulses in any of the selected first five positions, in the absence of the sixth pulse, normally indicates that letters ICC are to be formed. The sixth pulse (with one or more pulses in the first five positions) indicates different figures. Illustratively, for marking the letter A, a pulse may be considered to appear in each of the first two positions, following the start sync pulse, and for each of the last four positions (that is, positions 3 through 6) there is an absence of pulses and this is followed by the rest pulse or pulses. Thus, the letter A can be considered as being represented by a pulse series 11G-000.

Instead of indicating the letter A, if it were desired to indicate the figure 1, the pulse series could be the same except for the fact that a 'pulse could appear also in the sixth position. The pulse series for the figure l would thus be 11G-001. The foregoing exemplifies the fact that for one code, the letter A pulses appear only in positions one and two, while for the number l pulses appear in positions one, two and six.

Considering still another letter and figure as illustrative, the letter F is usually represented by a pulse in the first, third and fourth positions; while the numeral 6 is represented by a pulse in the first, third, fourth and sixth positions. Other letters and characters follow in accordance with the present operational development plan. The examples here given are purely illustrative and in no sense limiting, although it is to be understood that the operation of the system and circuit here to be disclosed is conditioned to accept in a registering medium any types of supplied coded signals and to allocate the signals of each grouping to appropriate controls whereby the desired information can be recreated for viewing.

As the circuitry here to be described is constituted, the incoming pulse series of signal energy, illustratively, of the type above described, is fed into a shift register of the requisite number of stages. The shift register, as is well known, is a circuit composed of a plurality of flipflops which are collectively capable of serially translating the data to be stored and then shifting itto the right or to the left. The data initially supplied may be either serially or parallelly impressed. As this invention is to be described, it will be considered that the data are serially impressed and the serial binary information is then applied to the rst of a series of cascaded flip-flops and gradually applied through the series by the operation of trigger circuits and the like under the control of pulses to shift the signal series from one end of the shift register to the other prior to its release.

The configuration of such circuitry, isquite arbitrary. That circuitry here described is illustrative of one form which has been found particularly suitable. The receiving distributor is predicated on the basis of adapting it to a non-synchronous telegraph transmission wherein a starting bit and variable length bits, with a rest synchronizing bit of one or more pulse lengths are applied as the input signal energy. The operation is controlled by an oscillator unit so functioning as to be started under the control of the start input signal. Following the start of operation, there is brought about a shifting of each stage of the shift register so that the input can be preset to a selected control position. The functioning is such as to continue until the last position of the pulse series is shifted down to what may be determined a redundant position at which time the desired input code may be released to suitable forms of circuitry and caused to portray visible indications of the selected code. The contact circuitry for portraying the input signals usually comprises a storage matrix with the various storage elements so interconnected as to contact a subsequent release of control conditions to provide a visible portrayal of the desired character. Following creation, the visible image may be maintained within a viewing area for selected and controllable time periods, and, in addition, caused to travel over a desired field of View in a controlled pattern.

Various forms of display combinations may be provided but one form which has been found particularly suitable utilizes a plurality of movable panels each formed of a selected number of turnable disc or other shape display elements arranged in a series of rows and columns. For conditions where the impressed input coded information consists of the presence or absence of pulse information in any one of six adjacent positions, as above inferred from the signal form proposed, each panel preferably comprises a group of display elements arranged in a plurality of rows and columns. The columns may comprise any number of elements depending upon the number of characters to be reproduced. Where the reproduction of letter characters, for instance, is to be spaced apart from numerical characters, more display elements are required. In this use, the columns may be of various selected lengths. For one condition that has been utilized to some extent, a column of twenty-three such display elements has been found suitable, thereby permitting letters to be designated above figures and alloting, for instance, ten vertical spaces for letters and the remaining number of figures and fractions. The display elements so used gene-rally have a lightabsorbing and non-reflecting ccating on one side and a glowing or phosphorescent coating on the opposite side. The selected signal information, as determined by the invention here to be described, is utilized in an appropriate fashion not herein set forth to provide storage information which can be released to control the positioning of the individual display elements to turn them to one side or the other with each received pulse series.

From the foregoing, it will be apparent that the invention here to be described includes circuit means for improving the rapidity and the accuracy with which intelligence developed from coded input signals may be recreated in a dot field thereby to portr-ay for visible reference any type of letters, figures, symbols, pictures or the like resulting from information derived from a character coding signal system. Other objects are those of providing the selection of control information according to a simplified signal pattern which is relatively simple in its arrangement and construction, and which operates to provide the control through the use of solid state components and to provide a, control system occupying minimal space and which is still capable of assuming high operational efficiency.

The invention has been illustrated schematically in one of its preferred circuit forms by the accompanying drawings wherein FIG. 1 is a diagrammatic showing of the shift register circuit employed together with the control established therefor by the incoming pulse signal series; and wherein FIG. 2 represents a suggested code used for identification of letters, numerals and other characters which is a six-unit code followed by a terminating or synchronizing pulse which is provided in order that the operation may be such as to provide for midpoint sampling of the incoming signal, where the various periods may be considered to be divided, purely for illustration, so that the pulse conditions fall into the positions and pattern above discussed. By this figure, the numeral 1 code is shown with the Roman numerals representing the different pulses and the Arabic numerals adjacent to the arrows representing the beginning and end of a pulse as well as a condition midway between these states, with it being mentioned that the numerals 11 and 15 used in this illustration are not to be confused with the same numerals used in respect of FIG. 1.

If reference is now made to the accompanying drawing, input signals comprising a signal series embodying the start sync pulse, followed by pulses in any selected number of possible signal positions, followed by a rest period are impressed at the input terminal 11. The signals are then supplied at terminal 11 through conductor 12 to one input terminal J of the first stage of a shift register, generally designated 1S, which will later be discussed. The same signals are also supplied by Way of Conductor 16 to an amplifier, with inversion, represented at 17. The output of the amplifier inverter 17 supplies these same signals in opposite polarity to the signals at input terminal J to the second input terminal K to trigger the first flipop 76 of the shift register 15. The latter signal polarity is also supplied by way of a conductor 18 to a gate 19 and then to the amplifier inverter 20 to control the operation and timing of an oscillator circuit, generally designated as 25. The signals are usually supplied at terminal 11 so that the signal is of ground level and extends in the up or positive direction for spacing conditions.

The oscillator 25 is in the form of a unijunction transistor element 26 having the usual base No. l electrode 27, the base No. 2 electrode 28 and the signal rectifying contact 29, commonly known as the emitter element. The base No. l contact 27 connects to ground 30 through resistor 31 and conductor 32. Base No. 2 contact 28 connects to terminal 35 to which a suitable source (not shown) of positive potential relative to ground is connected by wayl of the resistor 36. The resistors 31 and 36 then form a voltage divider between the positive potential point 35 and the ground point 30.

The unijunction oscillator 26 has its emitter 29 connected between the junction of one end of resistor and one terminal of capacitor 41. The opposite terminal of resistor 40 connects to a point of positive potential 35 which generally may be considered about twenty volts. The second terminal of capacitor 41 is grounded at 30 by way of conductor 32. For these conditions, the capacitor 41 tends to charge through resistor 40 from the source connected at terminal 35 and, when the charge of capacitor 41 is sufiiciently high, the unijunction transistor 26 will pass current in well-known fashion.

By the invention, the transistor 45 has its base electrode 46 connected between resistors 47 and 51, the latter of which has its second terminal grounded at 30. The voltage available at the junction point of resistors 47 and 51 is dependent upon the potential at the output of the amplifier inverter 20. Thus, at times when the base electrode 46 is positive and the transistor 45 is conducting, no charge can accumulate on the capacitor 41, as the transistor forms a discharge path as will later be explained in more detail. When the unijunction transistor 26 develops an output during an oscillating cycle, this output voltage is fed through capacitor 57 and conductor 58 to the C terminal of the flip-flop 55. A positive voltage relative to ground is applied to the J and K terminals of this flip-flop, and the preset terminal PS receives a voltage corresponding to the output of that developed at the output of the amplifier inverter 20, this voltage being supplied by conductor 53.

To cover further an understanding of the operation of the transistor 45, it may be considered first in what can be though of as an idle condition. At this time, the input signal at terminal 11, which will be a mark position, will be considered as ground potential. This voltage will be applied to the I terminal of the flip-flop 76. The output of the amplifier inverter 17 which applies a voltage to the K terminal of the flip-Hop 76 and also to the conductor 18 is then -i-. For these conditions, the start control of the last of the series of flip-flops 70 which is available at the terminal is and this voltage is effective on the conductors 90 and 92. The output voltage of the AND gate 1'9 (with inversion) is also at ground so that the output of the amplifier inverter 20- is -i. Under these conditions, it can be seen that the transistor 45 is conducting. At this time, the terminal PS of the flip-flop is also as is the Q terminal of this flip-flop. Consequently, the `output of the AND gate (with inversion) is ground. The output of the AND gate (with inversion) 66 is also If now, for a second condition, the input signal at terminal 11 is -j- (i.e., a positive signal) representing a condition of space or start pulse, the conductor 18, by the foregoing analysis, will 4be found to be at ground poten` tial. Under the circumstances, the output of the gate 19 is positive. The output of the amplifier inverter which receives the output from the gate 19 is then also at ground potential and the transistor 45 which has its base 46 connected to receive such output voltage becomes non-conducting. At this time, the preset terminal PS of the flipfiop 55 is also at ground potential, and the Q terminal remains positive. The output of the AND gate 65 (with inversion) then remains at ground, as before. The output of the gate 66 remains positive.

The conditions for the first unijunction interval produced by the resistor 40 and capacitor 41, which is adjusted to be exactly one-half the assigned bit interval so as to set the midpoint sampling, causes the terminal C of the flip-flop 55 to become positive, which is a pulse condition. At the same time, the Q terminal of this flip-flop 55 assumes a ground potential. Consequently, the output of the gate 65 (with inversion) is positive and a pulse is formed by the combination of the capacitor 79 and resistor 80. The output of the gate 66 remains (positive) and there is also a -l- (positive) pulse present at the preset terminal PS of all of the flip-flops 70 through 76 inclusive. Each Q output of eachof these flip-flops is also (positive). For the flip-fiop 70, the terminal assumes a ground potential, which potential is applied by conductors 90 and 92 to the input of the AND gate 19 and by conductors 90 and 91 to the output terminal 48. At this time, the output of the AND gate 19 (with inversion) remains positive and, consequently, the output of the amplifier inverter 20 continues to remain at ground. The outputs of the gates 65 and 66 remain positive, as before.

Now, the second unijunction interval may be considered. At the time the second unijunction interval arrives, the flip-flop 55 will have its Q terminal -l- (positive). Following the analogy already given, it can be seen that the output of the gate 19 remains (positive) as does the output of the gate 65. However, the output of the gate 66 assumes a ground potential. There is no change occurring on the flip-flops 70 through 76 incluslve.

At the third unijunction interval, the Q terminal of hip-flop 55 assumes a ground potential. The gate 65 remains (positive) and will continue to so remain until the `Q terminal of flip-flop 70 assumes a ground potential. This is true also of the output of the gate 19. The gate `66 has its output at such time (positive) and the input at terminal C for the flip-flops 70 through 76 becomes (positive). With this occurring, the Q terminal of the fiip-flop 76 has its potential correspond to the signal input of the I terminal of this flip-flop at this particular time. The Q terminal of the second flip-fiop 75, however, assumes a ground potential as it is transferred from the prior preset condition. The Q terminals of the remaining ip-flops 70 through 74 all remain -l- (positive). As used herein, it may be assumed that the terms and positive are equivalent and synonymous.

In the fourth unijunction interval, the Q terminal of the flip-flop 55 is again The gate 66 has its output at ground potential and there is no change in the hip-flops 70 through 76.

At the fifth and all subsequent odd unijunction intervals, the Q terminal of the ip-op 55 will be found to be at ground potential and the output of the gate 66 is then The input to all the flip-flops 70 through 76, as applied at terminal C by conductor 78, is in all instances. The potential at the vQ1 termial of flip-flop 76 matches or corresponds to the I signal input from conductor 12. For flip-flop 75, at this time, the Q terminal potential matches the flip-flop 76 before the input. The Q terminal of ipflop 74 becomes ground, which is the initial start pulse being transferred through the shift register. All of flipflops 73, 72, 71 and 70 have their Q terminal remaining 'The next condition occurs for the sixth and al1 subsequent unijunction intervals. The Q terminal of the flipflop 55 becomes '-fand the gate output 66 becomes ground. There is no change in any of the flip-flops 70 through 76.

Next, for the thirteenth interval for the unijunction, the fiip-flop 55 has its Q terminal again brought to a ground potential. The output of the gate 66 is -i-. The C input to each of the flip-flops 70 through 76 is -iand, at this time, the Q terminals of liip-op 76 records the sixth pulse; the Q terminal of the flip-flop 75 records the fifth pulse; the Q terminal of the flip-flop 74 records the fourth pulse; the Q terminal of the flip-flop 73 records the third pulse; the Q terminal of the Hip-flop 72 records the second pulse;

. the Q terminal of the flip-op 71 records the first pulse and the Q terminal of the Hip-flop 70 assumes a ground potential which is the initial start pulse.

At this time, it may be assumed that the sixth pulse spacing condition arrives and the gate 19 output is Consequently, outputs are available at each of the terminals 48 and 49. This is to signal that a character is now in storage in the flip-flops 71 through 76. At this time, the gate 66 has its output remain -1- because of the condition at the Q terminal at flip-flop 70 and because of the condition at the Q terminal of flip-flop 55.

It is now desirable to consider the conditions at the fourteenth unijunction interval without signal input going to the marking state after the twelfth interval. At this time, the flip-flop 55 has its Q terminal The output of the gate 66 remains -1- and the output of the gate 65 is ground. This serves to permit the capacitor 79 to recharge and the gate 19 output remains because of the signal input.

At the fifteenth unijunction interval, the Q terminal of the flip-flop 55 becomes ground and the output of the gate 66 still remains although the output of the gate 65 also becomes -i-. Following this, all action is now the same as step 3 and those described above subsequent thereto.

From the foregoing, it may be assumed that the timing sequence above mentioned states in effect that if a marl@ ing rest interval is not received, the receiving distributor will reset and absorb the normal rest interval. This fact insures that the receiving distributor will again synchronize within three characters under the worst conditions. In this respect, it may be noted that this then allows the transmission of blanks which are customarily not dealt with.

Now, assume that the sixth pulse marking at the thirteenth unijunction interval is shown by FIG. 2. It will be noted that the gate 19 output remains at ground. The output of the amplifier inverter 20 is then This carries the transistor 45 to a conducting state and also provides a positive potential at the preset terminal PS of the fipiiop 55. Here, the Q terminal remains -iand the oscillator stops and there is no further action to take place for the moment.

Now, it may be assumed that the input signal reverts to a rest position after the fourteenth unijunction interval but before the fifteenth. The action above expained for the assumed fourteenth unijunction interval will apply. Then, the input signal of terminal 11 assumes a ground potential and the output of the gate 19 as applied to the input of the amplifier inverter 20 is at ground which provides a potential output from the amplifier inverter 20 and carries the preset terminal PS of the fiip-flop 55 -lwith the Q terminal remaining The transistor 45 then remains in a conducting state and, as before, no further oscillations occur until the output potential of the amplifier inverter 20 is changed. This operation thus permits a rest pulse variation of any amount from practically zero time through to almost an infinite time and yet, it insures a rapid resynchroniaztion in the event of a false start. It also permits blanks and open line controls to be transmitted. It is important that the start pulse shall be a one-half interval out as already described in order that the unit will start. This constitutes a most significant fea- 7 ture. It has the advantage of having substantial tolerance to noise and prevents false starts. It makes auxiliary controls and counters unnecessary. It makes the system adaptable to any code lengths by adding storage stages as required and it is capable of accepting the transmission of blanks or open line conditions.

Various circuit modifications, of course, are contemplated within the scope of this invention and it is therefore to be understood that the invention and the appended claims are to be interpreted as broadly as the state of the art will permit.

Having now described the invention, what is claimed is:

1. A distributing circuit for binary coded signals of any selected code length comprising a shift register including a cascade of count tiip-tlop circuits corresponding in number to the pulse positions in the selected code,

a first count iiip-oppcircuit,

an oscillator,

a control iiip-iiop circuit connected at one input t0 said oscillator output to be activated at a rate corresponding to the oscillatory cycles of said oscillator,

means for supplying input signals to said irst count flip-iiop circuit and the remaining input of said control flip-flop circuit,

means for supplying the output of said control iiip-op circuit to said count flip-flop circuits for advancing the applied pulses through said count flip-flop circuits in sequence in accordance with said oscillator and said input signals,

a starter flip-flop, said starter flip-Hop being operatively connected with said oscillator and the ip-tiop circuits of said shift register,

means whereby said starter flip-flop receives said input signals a first condition of said starter iiip-op whereby said oscillator is locked in a non-conducting condition,

a second condition of said starter ip-iiop whereby said oscillator is free to oscillate, and

means applying said input signals to said starter flipliop whereby the conditions thereof can be changed from said lirst condition to said second condition.

2. The circuit claimed in claim 1 comprising, in addition,

means to control the oscillator jointly by the input signals and derived storage control signals.

3. The circuit claimed in claim 2 wherein the oscillator comprises a unijunction transistor and wherein, in addition, a second transistor controlled in its opperation by the control signals and the input signals determines the operating period of the unijunction transistor oscillator.

4. The circuit claimed in claim 1 wherein the oscillator circuit comprises the combination of a unijunction transistor and capacitor means for normally controlling the oscillating period of said unijunction transistor,

a second transistor connected to have its output circuit shunt said capacitor and thereby to short-circuit said capacitor during transistor conducting periods, and

means to control the conducting periods of the transistor in accordance `with supplied signal information.

References Cited UNITED STATES PATENTS 3,146,345 8/1964 Conover, Jr 23S-92 3,026,422 3/ 1962 Phylip-I ones 307-221 3,178,586 4/1965 Rosenfeld 328-37 3,416,133 12/1968 Hunkins et al 235-92 MAYNARD R. WILBUR, Primary Examiner C. D. MILLER, Assistant Examiner U.S. Cl. XR. 235-92

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